efm32pg1b200_pac/cmu/
hfclksel.rs

1#[doc = "Register `HFCLKSEL` writer"]
2pub struct W(crate::W<HFCLKSEL_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<HFCLKSEL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<HFCLKSEL_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<HFCLKSEL_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "HFCLK Select\n\nValue on reset: 0"]
23#[derive(Clone, Copy, Debug, PartialEq)]
24#[repr(u8)]
25pub enum HF_AW {
26    #[doc = "1: Select HFRCO as HFCLK"]
27    HFRCO = 1,
28    #[doc = "2: Select HFXO as HFCLK"]
29    HFXO = 2,
30    #[doc = "3: Select LFRCO as HFCLK"]
31    LFRCO = 3,
32    #[doc = "4: Select LFXO as HFCLK"]
33    LFXO = 4,
34}
35impl From<HF_AW> for u8 {
36    #[inline(always)]
37    fn from(variant: HF_AW) -> Self {
38        variant as _
39    }
40}
41#[doc = "Field `HF` writer - HFCLK Select"]
42pub type HF_W<'a> = crate::FieldWriter<'a, u32, HFCLKSEL_SPEC, u8, HF_AW, 3, 0>;
43impl<'a> HF_W<'a> {
44    #[doc = "Select HFRCO as HFCLK"]
45    #[inline(always)]
46    pub fn hfrco(self) -> &'a mut W {
47        self.variant(HF_AW::HFRCO)
48    }
49    #[doc = "Select HFXO as HFCLK"]
50    #[inline(always)]
51    pub fn hfxo(self) -> &'a mut W {
52        self.variant(HF_AW::HFXO)
53    }
54    #[doc = "Select LFRCO as HFCLK"]
55    #[inline(always)]
56    pub fn lfrco(self) -> &'a mut W {
57        self.variant(HF_AW::LFRCO)
58    }
59    #[doc = "Select LFXO as HFCLK"]
60    #[inline(always)]
61    pub fn lfxo(self) -> &'a mut W {
62        self.variant(HF_AW::LFXO)
63    }
64}
65impl W {
66    #[doc = "Bits 0:2 - HFCLK Select"]
67    #[inline(always)]
68    pub fn hf(&mut self) -> HF_W {
69        HF_W::new(self)
70    }
71    #[doc = "Writes raw bits to the register."]
72    #[inline(always)]
73    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
74        self.0.bits(bits);
75        self
76    }
77}
78#[doc = "High Frequency Clock Select Command Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfclksel](index.html) module"]
79pub struct HFCLKSEL_SPEC;
80impl crate::RegisterSpec for HFCLKSEL_SPEC {
81    type Ux = u32;
82}
83#[doc = "`write(|w| ..)` method takes [hfclksel::W](W) writer structure"]
84impl crate::Writable for HFCLKSEL_SPEC {
85    type Writer = W;
86}
87#[doc = "`reset()` method sets HFCLKSEL to value 0"]
88impl crate::Resettable for HFCLKSEL_SPEC {
89    #[inline(always)]
90    fn reset_value() -> Self::Ux {
91        0
92    }
93}
efm32pg1b200_pac/cmu/hfclksel.rs

efm32pg1b200_pac/cmu/
hfclksel.rs
