efm32pg1b200_pac/msc/
readctrl.rs

1#[doc = "Register `READCTRL` reader"]
2pub struct R(crate::R<READCTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<READCTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<READCTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<READCTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `READCTRL` writer"]
17pub struct W(crate::W<READCTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<READCTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<READCTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<READCTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `IFCDIS` reader - Internal Flash Cache Disable"]
38pub type IFCDIS_R = crate::BitReader<bool>;
39#[doc = "Field `IFCDIS` writer - Internal Flash Cache Disable"]
40pub type IFCDIS_W<'a> = crate::BitWriter<'a, u32, READCTRL_SPEC, bool, 3>;
41#[doc = "Field `AIDIS` reader - Automatic Invalidate Disable"]
42pub type AIDIS_R = crate::BitReader<bool>;
43#[doc = "Field `AIDIS` writer - Automatic Invalidate Disable"]
44pub type AIDIS_W<'a> = crate::BitWriter<'a, u32, READCTRL_SPEC, bool, 4>;
45#[doc = "Field `ICCDIS` reader - Interrupt Context Cache Disable"]
46pub type ICCDIS_R = crate::BitReader<bool>;
47#[doc = "Field `ICCDIS` writer - Interrupt Context Cache Disable"]
48pub type ICCDIS_W<'a> = crate::BitWriter<'a, u32, READCTRL_SPEC, bool, 5>;
49#[doc = "Field `PREFETCH` reader - Prefetch Mode"]
50pub type PREFETCH_R = crate::BitReader<bool>;
51#[doc = "Field `PREFETCH` writer - Prefetch Mode"]
52pub type PREFETCH_W<'a> = crate::BitWriter<'a, u32, READCTRL_SPEC, bool, 8>;
53#[doc = "Field `USEHPROT` reader - AHB_HPROT Mode"]
54pub type USEHPROT_R = crate::BitReader<bool>;
55#[doc = "Field `USEHPROT` writer - AHB_HPROT Mode"]
56pub type USEHPROT_W<'a> = crate::BitWriter<'a, u32, READCTRL_SPEC, bool, 9>;
57#[doc = "Read Mode\n\nValue on reset: 1"]
58#[derive(Clone, Copy, Debug, PartialEq)]
59#[repr(u8)]
60pub enum MODE_A {
61    #[doc = "0: Zero wait-states inserted in fetch or read transfers"]
62    WS0 = 0,
63    #[doc = "1: One wait-state inserted for each fetch or read transfer. See Flash Wait-States table for details"]
64    WS1 = 1,
65}
66impl From<MODE_A> for u8 {
67    #[inline(always)]
68    fn from(variant: MODE_A) -> Self {
69        variant as _
70    }
71}
72#[doc = "Field `MODE` reader - Read Mode"]
73pub type MODE_R = crate::FieldReader<u8, MODE_A>;
74impl MODE_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub fn variant(&self) -> Option<MODE_A> {
78        match self.bits {
79            0 => Some(MODE_A::WS0),
80            1 => Some(MODE_A::WS1),
81            _ => None,
82        }
83    }
84    #[doc = "Checks if the value of the field is `WS0`"]
85    #[inline(always)]
86    pub fn is_ws0(&self) -> bool {
87        *self == MODE_A::WS0
88    }
89    #[doc = "Checks if the value of the field is `WS1`"]
90    #[inline(always)]
91    pub fn is_ws1(&self) -> bool {
92        *self == MODE_A::WS1
93    }
94}
95#[doc = "Field `MODE` writer - Read Mode"]
96pub type MODE_W<'a> = crate::FieldWriter<'a, u32, READCTRL_SPEC, u8, MODE_A, 2, 24>;
97impl<'a> MODE_W<'a> {
98    #[doc = "Zero wait-states inserted in fetch or read transfers"]
99    #[inline(always)]
100    pub fn ws0(self) -> &'a mut W {
101        self.variant(MODE_A::WS0)
102    }
103    #[doc = "One wait-state inserted for each fetch or read transfer. See Flash Wait-States table for details"]
104    #[inline(always)]
105    pub fn ws1(self) -> &'a mut W {
106        self.variant(MODE_A::WS1)
107    }
108}
109#[doc = "Field `SCBTP` reader - Suppress Conditional Branch Target Perfetch"]
110pub type SCBTP_R = crate::BitReader<bool>;
111#[doc = "Field `SCBTP` writer - Suppress Conditional Branch Target Perfetch"]
112pub type SCBTP_W<'a> = crate::BitWriter<'a, u32, READCTRL_SPEC, bool, 28>;
113impl R {
114    #[doc = "Bit 3 - Internal Flash Cache Disable"]
115    #[inline(always)]
116    pub fn ifcdis(&self) -> IFCDIS_R {
117        IFCDIS_R::new(((self.bits >> 3) & 1) != 0)
118    }
119    #[doc = "Bit 4 - Automatic Invalidate Disable"]
120    #[inline(always)]
121    pub fn aidis(&self) -> AIDIS_R {
122        AIDIS_R::new(((self.bits >> 4) & 1) != 0)
123    }
124    #[doc = "Bit 5 - Interrupt Context Cache Disable"]
125    #[inline(always)]
126    pub fn iccdis(&self) -> ICCDIS_R {
127        ICCDIS_R::new(((self.bits >> 5) & 1) != 0)
128    }
129    #[doc = "Bit 8 - Prefetch Mode"]
130    #[inline(always)]
131    pub fn prefetch(&self) -> PREFETCH_R {
132        PREFETCH_R::new(((self.bits >> 8) & 1) != 0)
133    }
134    #[doc = "Bit 9 - AHB_HPROT Mode"]
135    #[inline(always)]
136    pub fn usehprot(&self) -> USEHPROT_R {
137        USEHPROT_R::new(((self.bits >> 9) & 1) != 0)
138    }
139    #[doc = "Bits 24:25 - Read Mode"]
140    #[inline(always)]
141    pub fn mode(&self) -> MODE_R {
142        MODE_R::new(((self.bits >> 24) & 3) as u8)
143    }
144    #[doc = "Bit 28 - Suppress Conditional Branch Target Perfetch"]
145    #[inline(always)]
146    pub fn scbtp(&self) -> SCBTP_R {
147        SCBTP_R::new(((self.bits >> 28) & 1) != 0)
148    }
149}
150impl W {
151    #[doc = "Bit 3 - Internal Flash Cache Disable"]
152    #[inline(always)]
153    pub fn ifcdis(&mut self) -> IFCDIS_W {
154        IFCDIS_W::new(self)
155    }
156    #[doc = "Bit 4 - Automatic Invalidate Disable"]
157    #[inline(always)]
158    pub fn aidis(&mut self) -> AIDIS_W {
159        AIDIS_W::new(self)
160    }
161    #[doc = "Bit 5 - Interrupt Context Cache Disable"]
162    #[inline(always)]
163    pub fn iccdis(&mut self) -> ICCDIS_W {
164        ICCDIS_W::new(self)
165    }
166    #[doc = "Bit 8 - Prefetch Mode"]
167    #[inline(always)]
168    pub fn prefetch(&mut self) -> PREFETCH_W {
169        PREFETCH_W::new(self)
170    }
171    #[doc = "Bit 9 - AHB_HPROT Mode"]
172    #[inline(always)]
173    pub fn usehprot(&mut self) -> USEHPROT_W {
174        USEHPROT_W::new(self)
175    }
176    #[doc = "Bits 24:25 - Read Mode"]
177    #[inline(always)]
178    pub fn mode(&mut self) -> MODE_W {
179        MODE_W::new(self)
180    }
181    #[doc = "Bit 28 - Suppress Conditional Branch Target Perfetch"]
182    #[inline(always)]
183    pub fn scbtp(&mut self) -> SCBTP_W {
184        SCBTP_W::new(self)
185    }
186    #[doc = "Writes raw bits to the register."]
187    #[inline(always)]
188    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
189        self.0.bits(bits);
190        self
191    }
192}
193#[doc = "Read Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [readctrl](index.html) module"]
194pub struct READCTRL_SPEC;
195impl crate::RegisterSpec for READCTRL_SPEC {
196    type Ux = u32;
197}
198#[doc = "`read()` method returns [readctrl::R](R) reader structure"]
199impl crate::Readable for READCTRL_SPEC {
200    type Reader = R;
201}
202#[doc = "`write(|w| ..)` method takes [readctrl::W](W) writer structure"]
203impl crate::Writable for READCTRL_SPEC {
204    type Writer = W;
205}
206#[doc = "`reset()` method sets READCTRL to value 0x0100_0100"]
207impl crate::Resettable for READCTRL_SPEC {
208    #[inline(always)]
209    fn reset_value() -> Self::Ux {
210        0x0100_0100
211    }
212}
efm32pg1b200_pac/msc/readctrl.rs

efm32pg1b200_pac/msc/
readctrl.rs
