efm32pg1b_pac/rtcc/
ctrl.rs

1///Register `CTRL` reader
2pub type R = crate::R<CTRLrs>;
3///Register `CTRL` writer
4pub type W = crate::W<CTRLrs>;
5///Field `ENABLE` reader - RTCC Enable
6pub type EnableR = crate::BitReader;
7///Field `ENABLE` writer - RTCC Enable
8pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `DEBUGRUN` reader - Debug Mode Run Enable
10pub type DebugrunR = crate::BitReader;
11///Field `DEBUGRUN` writer - Debug Mode Run Enable
12pub type DebugrunW<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `PRECCV0TOP` reader - Pre-counter CCV0 Top Value Enable
14pub type Preccv0topR = crate::BitReader;
15///Field `PRECCV0TOP` writer - Pre-counter CCV0 Top Value Enable
16pub type Preccv0topW<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `CCV1TOP` reader - CCV1 Top Value Enable
18pub type Ccv1topR = crate::BitReader;
19///Field `CCV1TOP` writer - CCV1 Top Value Enable
20pub type Ccv1topW<'a, REG> = crate::BitWriter<'a, REG>;
21///Counter Prescaler Value
22///
23///Value on reset: 0
24#[cfg_attr(feature = "defmt", derive(defmt::Format))]
25#[derive(Clone, Copy, Debug, PartialEq, Eq)]
26#[repr(u8)]
27pub enum CNTPRESC {
28    ///0: CLKCNT = LFECLKRTCC/1
29    Div1 = 0,
30    ///1: CLKCNT = LFECLKRTCC/2
31    Div2 = 1,
32    ///2: CLKCNT = LFECLKRTCC/4
33    Div4 = 2,
34    ///3: CLKCNT = LFECLKRTCC/8
35    Div8 = 3,
36    ///4: CLKCNT = LFECLKRTCC/16
37    Div16 = 4,
38    ///5: CLKCNT = LFECLKRTCC/32
39    Div32 = 5,
40    ///6: CLKCNT = LFECLKRTCC/64
41    Div64 = 6,
42    ///7: CLKCNT = LFECLKRTCC/128
43    Div128 = 7,
44    ///8: CLKCNT = LFECLKRTCC/256
45    Div256 = 8,
46    ///9: CLKCNT = LFECLKRTCC/512
47    Div512 = 9,
48    ///10: CLKCNT = LFECLKRTCC/1024
49    Div1024 = 10,
50    ///11: CLKCNT = LFECLKRTCC/2048
51    Div2048 = 11,
52    ///12: CLKCNT = LFECLKRTCC/4096
53    Div4096 = 12,
54    ///13: CLKCNT = LFECLKRTCC/8192
55    Div8192 = 13,
56    ///14: CLKCNT = LFECLKRTCC/16384
57    Div16384 = 14,
58    ///15: CLKCNT = LFECLKRTCC/32768
59    Div32768 = 15,
60}
61impl From<CNTPRESC> for u8 {
62    #[inline(always)]
63    fn from(variant: CNTPRESC) -> Self {
64        variant as _
65    }
66}
67impl crate::FieldSpec for CNTPRESC {
68    type Ux = u8;
69}
70impl crate::IsEnum for CNTPRESC {}
71///Field `CNTPRESC` reader - Counter Prescaler Value
72pub type CntprescR = crate::FieldReader<CNTPRESC>;
73impl CntprescR {
74    ///Get enumerated values variant
75    #[inline(always)]
76    pub const fn variant(&self) -> CNTPRESC {
77        match self.bits {
78            0 => CNTPRESC::Div1,
79            1 => CNTPRESC::Div2,
80            2 => CNTPRESC::Div4,
81            3 => CNTPRESC::Div8,
82            4 => CNTPRESC::Div16,
83            5 => CNTPRESC::Div32,
84            6 => CNTPRESC::Div64,
85            7 => CNTPRESC::Div128,
86            8 => CNTPRESC::Div256,
87            9 => CNTPRESC::Div512,
88            10 => CNTPRESC::Div1024,
89            11 => CNTPRESC::Div2048,
90            12 => CNTPRESC::Div4096,
91            13 => CNTPRESC::Div8192,
92            14 => CNTPRESC::Div16384,
93            15 => CNTPRESC::Div32768,
94            _ => unreachable!(),
95        }
96    }
97    ///CLKCNT = LFECLKRTCC/1
98    #[inline(always)]
99    pub fn is_div1(&self) -> bool {
100        *self == CNTPRESC::Div1
101    }
102    ///CLKCNT = LFECLKRTCC/2
103    #[inline(always)]
104    pub fn is_div2(&self) -> bool {
105        *self == CNTPRESC::Div2
106    }
107    ///CLKCNT = LFECLKRTCC/4
108    #[inline(always)]
109    pub fn is_div4(&self) -> bool {
110        *self == CNTPRESC::Div4
111    }
112    ///CLKCNT = LFECLKRTCC/8
113    #[inline(always)]
114    pub fn is_div8(&self) -> bool {
115        *self == CNTPRESC::Div8
116    }
117    ///CLKCNT = LFECLKRTCC/16
118    #[inline(always)]
119    pub fn is_div16(&self) -> bool {
120        *self == CNTPRESC::Div16
121    }
122    ///CLKCNT = LFECLKRTCC/32
123    #[inline(always)]
124    pub fn is_div32(&self) -> bool {
125        *self == CNTPRESC::Div32
126    }
127    ///CLKCNT = LFECLKRTCC/64
128    #[inline(always)]
129    pub fn is_div64(&self) -> bool {
130        *self == CNTPRESC::Div64
131    }
132    ///CLKCNT = LFECLKRTCC/128
133    #[inline(always)]
134    pub fn is_div128(&self) -> bool {
135        *self == CNTPRESC::Div128
136    }
137    ///CLKCNT = LFECLKRTCC/256
138    #[inline(always)]
139    pub fn is_div256(&self) -> bool {
140        *self == CNTPRESC::Div256
141    }
142    ///CLKCNT = LFECLKRTCC/512
143    #[inline(always)]
144    pub fn is_div512(&self) -> bool {
145        *self == CNTPRESC::Div512
146    }
147    ///CLKCNT = LFECLKRTCC/1024
148    #[inline(always)]
149    pub fn is_div1024(&self) -> bool {
150        *self == CNTPRESC::Div1024
151    }
152    ///CLKCNT = LFECLKRTCC/2048
153    #[inline(always)]
154    pub fn is_div2048(&self) -> bool {
155        *self == CNTPRESC::Div2048
156    }
157    ///CLKCNT = LFECLKRTCC/4096
158    #[inline(always)]
159    pub fn is_div4096(&self) -> bool {
160        *self == CNTPRESC::Div4096
161    }
162    ///CLKCNT = LFECLKRTCC/8192
163    #[inline(always)]
164    pub fn is_div8192(&self) -> bool {
165        *self == CNTPRESC::Div8192
166    }
167    ///CLKCNT = LFECLKRTCC/16384
168    #[inline(always)]
169    pub fn is_div16384(&self) -> bool {
170        *self == CNTPRESC::Div16384
171    }
172    ///CLKCNT = LFECLKRTCC/32768
173    #[inline(always)]
174    pub fn is_div32768(&self) -> bool {
175        *self == CNTPRESC::Div32768
176    }
177}
178///Field `CNTPRESC` writer - Counter Prescaler Value
179pub type CntprescW<'a, REG> = crate::FieldWriter<'a, REG, 4, CNTPRESC, crate::Safe>;
180impl<'a, REG> CntprescW<'a, REG>
181where
182    REG: crate::Writable + crate::RegisterSpec,
183    REG::Ux: From<u8>,
184{
185    ///CLKCNT = LFECLKRTCC/1
186    #[inline(always)]
187    pub fn div1(self) -> &'a mut crate::W<REG> {
188        self.variant(CNTPRESC::Div1)
189    }
190    ///CLKCNT = LFECLKRTCC/2
191    #[inline(always)]
192    pub fn div2(self) -> &'a mut crate::W<REG> {
193        self.variant(CNTPRESC::Div2)
194    }
195    ///CLKCNT = LFECLKRTCC/4
196    #[inline(always)]
197    pub fn div4(self) -> &'a mut crate::W<REG> {
198        self.variant(CNTPRESC::Div4)
199    }
200    ///CLKCNT = LFECLKRTCC/8
201    #[inline(always)]
202    pub fn div8(self) -> &'a mut crate::W<REG> {
203        self.variant(CNTPRESC::Div8)
204    }
205    ///CLKCNT = LFECLKRTCC/16
206    #[inline(always)]
207    pub fn div16(self) -> &'a mut crate::W<REG> {
208        self.variant(CNTPRESC::Div16)
209    }
210    ///CLKCNT = LFECLKRTCC/32
211    #[inline(always)]
212    pub fn div32(self) -> &'a mut crate::W<REG> {
213        self.variant(CNTPRESC::Div32)
214    }
215    ///CLKCNT = LFECLKRTCC/64
216    #[inline(always)]
217    pub fn div64(self) -> &'a mut crate::W<REG> {
218        self.variant(CNTPRESC::Div64)
219    }
220    ///CLKCNT = LFECLKRTCC/128
221    #[inline(always)]
222    pub fn div128(self) -> &'a mut crate::W<REG> {
223        self.variant(CNTPRESC::Div128)
224    }
225    ///CLKCNT = LFECLKRTCC/256
226    #[inline(always)]
227    pub fn div256(self) -> &'a mut crate::W<REG> {
228        self.variant(CNTPRESC::Div256)
229    }
230    ///CLKCNT = LFECLKRTCC/512
231    #[inline(always)]
232    pub fn div512(self) -> &'a mut crate::W<REG> {
233        self.variant(CNTPRESC::Div512)
234    }
235    ///CLKCNT = LFECLKRTCC/1024
236    #[inline(always)]
237    pub fn div1024(self) -> &'a mut crate::W<REG> {
238        self.variant(CNTPRESC::Div1024)
239    }
240    ///CLKCNT = LFECLKRTCC/2048
241    #[inline(always)]
242    pub fn div2048(self) -> &'a mut crate::W<REG> {
243        self.variant(CNTPRESC::Div2048)
244    }
245    ///CLKCNT = LFECLKRTCC/4096
246    #[inline(always)]
247    pub fn div4096(self) -> &'a mut crate::W<REG> {
248        self.variant(CNTPRESC::Div4096)
249    }
250    ///CLKCNT = LFECLKRTCC/8192
251    #[inline(always)]
252    pub fn div8192(self) -> &'a mut crate::W<REG> {
253        self.variant(CNTPRESC::Div8192)
254    }
255    ///CLKCNT = LFECLKRTCC/16384
256    #[inline(always)]
257    pub fn div16384(self) -> &'a mut crate::W<REG> {
258        self.variant(CNTPRESC::Div16384)
259    }
260    ///CLKCNT = LFECLKRTCC/32768
261    #[inline(always)]
262    pub fn div32768(self) -> &'a mut crate::W<REG> {
263        self.variant(CNTPRESC::Div32768)
264    }
265}
266///Field `CNTTICK` reader - Counter Prescaler Mode
267pub type CnttickR = crate::BitReader;
268///Field `CNTTICK` writer - Counter Prescaler Mode
269pub type CnttickW<'a, REG> = crate::BitWriter<'a, REG>;
270///Field `OSCFDETEN` reader - Oscillator Failure Detection Enable
271pub type OscfdetenR = crate::BitReader;
272///Field `OSCFDETEN` writer - Oscillator Failure Detection Enable
273pub type OscfdetenW<'a, REG> = crate::BitWriter<'a, REG>;
274///Field `CNTMODE` reader - Main Counter Mode
275pub type CntmodeR = crate::BitReader;
276///Field `CNTMODE` writer - Main Counter Mode
277pub type CntmodeW<'a, REG> = crate::BitWriter<'a, REG>;
278///Field `LYEARCORRDIS` reader - Leap Year Correction Disabled
279pub type LyearcorrdisR = crate::BitReader;
280///Field `LYEARCORRDIS` writer - Leap Year Correction Disabled
281pub type LyearcorrdisW<'a, REG> = crate::BitWriter<'a, REG>;
282impl R {
283    ///Bit 0 - RTCC Enable
284    #[inline(always)]
285    pub fn enable(&self) -> EnableR {
286        EnableR::new((self.bits & 1) != 0)
287    }
288    ///Bit 2 - Debug Mode Run Enable
289    #[inline(always)]
290    pub fn debugrun(&self) -> DebugrunR {
291        DebugrunR::new(((self.bits >> 2) & 1) != 0)
292    }
293    ///Bit 4 - Pre-counter CCV0 Top Value Enable
294    #[inline(always)]
295    pub fn preccv0top(&self) -> Preccv0topR {
296        Preccv0topR::new(((self.bits >> 4) & 1) != 0)
297    }
298    ///Bit 5 - CCV1 Top Value Enable
299    #[inline(always)]
300    pub fn ccv1top(&self) -> Ccv1topR {
301        Ccv1topR::new(((self.bits >> 5) & 1) != 0)
302    }
303    ///Bits 8:11 - Counter Prescaler Value
304    #[inline(always)]
305    pub fn cntpresc(&self) -> CntprescR {
306        CntprescR::new(((self.bits >> 8) & 0x0f) as u8)
307    }
308    ///Bit 12 - Counter Prescaler Mode
309    #[inline(always)]
310    pub fn cnttick(&self) -> CnttickR {
311        CnttickR::new(((self.bits >> 12) & 1) != 0)
312    }
313    ///Bit 15 - Oscillator Failure Detection Enable
314    #[inline(always)]
315    pub fn oscfdeten(&self) -> OscfdetenR {
316        OscfdetenR::new(((self.bits >> 15) & 1) != 0)
317    }
318    ///Bit 16 - Main Counter Mode
319    #[inline(always)]
320    pub fn cntmode(&self) -> CntmodeR {
321        CntmodeR::new(((self.bits >> 16) & 1) != 0)
322    }
323    ///Bit 17 - Leap Year Correction Disabled
324    #[inline(always)]
325    pub fn lyearcorrdis(&self) -> LyearcorrdisR {
326        LyearcorrdisR::new(((self.bits >> 17) & 1) != 0)
327    }
328}
329impl core::fmt::Debug for R {
330    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
331        f.debug_struct("CTRL")
332            .field("enable", &self.enable())
333            .field("debugrun", &self.debugrun())
334            .field("preccv0top", &self.preccv0top())
335            .field("ccv1top", &self.ccv1top())
336            .field("cntpresc", &self.cntpresc())
337            .field("cnttick", &self.cnttick())
338            .field("oscfdeten", &self.oscfdeten())
339            .field("cntmode", &self.cntmode())
340            .field("lyearcorrdis", &self.lyearcorrdis())
341            .finish()
342    }
343}
344impl W {
345    ///Bit 0 - RTCC Enable
346    #[inline(always)]
347    pub fn enable(&mut self) -> EnableW<'_, CTRLrs> {
348        EnableW::new(self, 0)
349    }
350    ///Bit 2 - Debug Mode Run Enable
351    #[inline(always)]
352    pub fn debugrun(&mut self) -> DebugrunW<'_, CTRLrs> {
353        DebugrunW::new(self, 2)
354    }
355    ///Bit 4 - Pre-counter CCV0 Top Value Enable
356    #[inline(always)]
357    pub fn preccv0top(&mut self) -> Preccv0topW<'_, CTRLrs> {
358        Preccv0topW::new(self, 4)
359    }
360    ///Bit 5 - CCV1 Top Value Enable
361    #[inline(always)]
362    pub fn ccv1top(&mut self) -> Ccv1topW<'_, CTRLrs> {
363        Ccv1topW::new(self, 5)
364    }
365    ///Bits 8:11 - Counter Prescaler Value
366    #[inline(always)]
367    pub fn cntpresc(&mut self) -> CntprescW<'_, CTRLrs> {
368        CntprescW::new(self, 8)
369    }
370    ///Bit 12 - Counter Prescaler Mode
371    #[inline(always)]
372    pub fn cnttick(&mut self) -> CnttickW<'_, CTRLrs> {
373        CnttickW::new(self, 12)
374    }
375    ///Bit 15 - Oscillator Failure Detection Enable
376    #[inline(always)]
377    pub fn oscfdeten(&mut self) -> OscfdetenW<'_, CTRLrs> {
378        OscfdetenW::new(self, 15)
379    }
380    ///Bit 16 - Main Counter Mode
381    #[inline(always)]
382    pub fn cntmode(&mut self) -> CntmodeW<'_, CTRLrs> {
383        CntmodeW::new(self, 16)
384    }
385    ///Bit 17 - Leap Year Correction Disabled
386    #[inline(always)]
387    pub fn lyearcorrdis(&mut self) -> LyearcorrdisW<'_, CTRLrs> {
388        LyearcorrdisW::new(self, 17)
389    }
390}
391///Control Register
392///
393///You can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
394pub struct CTRLrs;
395impl crate::RegisterSpec for CTRLrs {
396    type Ux = u32;
397}
398///`read()` method returns [`ctrl::R`](R) reader structure
399impl crate::Readable for CTRLrs {}
400///`write(|w| ..)` method takes [`ctrl::W`](W) writer structure
401impl crate::Writable for CTRLrs {
402    type Safety = crate::Unsafe;
403}
404///`reset()` method sets CTRL to value 0
405impl crate::Resettable for CTRLrs {}
efm32pg1b_pac/rtcc/ctrl.rs

efm32pg1b_pac/rtcc/
ctrl.rs
