[−][src]Struct efm32pg1b_pac::generic::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Methods

`impl<U, REG> W<U, REG>`[src]

`pub unsafe fn bits(&mut self, bits: U) -> &mut Self`[src]

Writes raw bits to the register

`impl W<u32, Reg<u32, _CTRL>>`[src]

`pub fn addrfaulten(&mut self) -> ADDRFAULTEN_W`[src]

Bit 0 - Invalid Address Bus Fault Response Enable

`pub fn clkdisfaulten(&mut self) -> CLKDISFAULTEN_W`[src]

Bit 1 - Clock-disabled Bus Fault Response Enable

`pub fn pwrupondemand(&mut self) -> PWRUPONDEMAND_W`[src]

Bit 2 - Power Up on Demand During Wake Up

`pub fn ifcreadclear(&mut self) -> IFCREADCLEAR_W`[src]

Bit 3 - IFC Read Clears IF

`impl W<u32, Reg<u32, _READCTRL>>`[src]

`pub fn ifcdis(&mut self) -> IFCDIS_W`[src]

Bit 3 - Internal Flash Cache Disable

`pub fn aidis(&mut self) -> AIDIS_W`[src]

Bit 4 - Automatic Invalidate Disable

`pub fn iccdis(&mut self) -> ICCDIS_W`[src]

Bit 5 - Interrupt Context Cache Disable

`pub fn prefetch(&mut self) -> PREFETCH_W`[src]

Bit 8 - Prefetch Mode

`pub fn usehprot(&mut self) -> USEHPROT_W`[src]

Bit 9 - AHB_HPROT Mode

`pub fn mode(&mut self) -> MODE_W`[src]

Bits 24:25 - Read Mode

`pub fn scbtp(&mut self) -> SCBTP_W`[src]

Bit 28 - Suppress Conditional Branch Target Perfetch

`impl W<u32, Reg<u32, _WRITECTRL>>`[src]

`pub fn wren(&mut self) -> WREN_W`[src]

Bit 0 - Enable Write/Erase Controller

`pub fn irqeraseabort(&mut self) -> IRQERASEABORT_W`[src]

Bit 1 - Abort Page Erase on Interrupt

`impl W<u32, Reg<u32, _WRITECMD>>`[src]

`pub fn laddrim(&mut self) -> LADDRIM_W`[src]

Bit 0 - Load MSC_ADDRB Into ADDR

`pub fn erasepage(&mut self) -> ERASEPAGE_W`[src]

Bit 1 - Erase Page

`pub fn writeend(&mut self) -> WRITEEND_W`[src]

Bit 2 - End Write Mode

`pub fn writeonce(&mut self) -> WRITEONCE_W`[src]

Bit 3 - Word Write-Once Trigger

`pub fn writetrig(&mut self) -> WRITETRIG_W`[src]

Bit 4 - Word Write Sequence Trigger

`pub fn eraseabort(&mut self) -> ERASEABORT_W`[src]

Bit 5 - Abort Erase Sequence

`pub fn erasemain0(&mut self) -> ERASEMAIN0_W`[src]

Bit 8 - Mass Erase Region 0

`pub fn clearwdata(&mut self) -> CLEARWDATA_W`[src]

Bit 12 - Clear WDATA State

`impl W<u32, Reg<u32, _ADDRB>>`[src]

`pub fn addrb(&mut self) -> ADDRB_W`[src]

Bits 0:31 - Page Erase or Write Address Buffer

`impl W<u32, Reg<u32, _WDATA>>`[src]

`pub fn wdata(&mut self) -> WDATA_W`[src]

Bits 0:31 - Write Data

`impl W<u32, Reg<u32, _IFS>>`[src]

`pub fn erase(&mut self) -> ERASE_W`[src]

Bit 0 - Set ERASE Interrupt Flag

`pub fn write(&mut self) -> WRITE_W`[src]

Bit 1 - Set WRITE Interrupt Flag

`pub fn chof(&mut self) -> CHOF_W`[src]

Bit 2 - Set CHOF Interrupt Flag

`pub fn cmof(&mut self) -> CMOF_W`[src]

Bit 3 - Set CMOF Interrupt Flag

`pub fn pwrupf(&mut self) -> PWRUPF_W`[src]

Bit 4 - Set PWRUPF Interrupt Flag

`pub fn icacherr(&mut self) -> ICACHERR_W`[src]

Bit 5 - Set ICACHERR Interrupt Flag

`impl W<u32, Reg<u32, _IFC>>`[src]

`pub fn erase(&mut self) -> ERASE_W`[src]

Bit 0 - Clear ERASE Interrupt Flag

`pub fn write(&mut self) -> WRITE_W`[src]

Bit 1 - Clear WRITE Interrupt Flag

`pub fn chof(&mut self) -> CHOF_W`[src]

Bit 2 - Clear CHOF Interrupt Flag

`pub fn cmof(&mut self) -> CMOF_W`[src]

Bit 3 - Clear CMOF Interrupt Flag

`pub fn pwrupf(&mut self) -> PWRUPF_W`[src]

Bit 4 - Clear PWRUPF Interrupt Flag

`pub fn icacherr(&mut self) -> ICACHERR_W`[src]

Bit 5 - Clear ICACHERR Interrupt Flag

`impl W<u32, Reg<u32, _IEN>>`[src]

`pub fn erase(&mut self) -> ERASE_W`[src]

Bit 0 - ERASE Interrupt Enable

`pub fn write(&mut self) -> WRITE_W`[src]

Bit 1 - WRITE Interrupt Enable

`pub fn chof(&mut self) -> CHOF_W`[src]

Bit 2 - CHOF Interrupt Enable

`pub fn cmof(&mut self) -> CMOF_W`[src]

Bit 3 - CMOF Interrupt Enable

`pub fn pwrupf(&mut self) -> PWRUPF_W`[src]

Bit 4 - PWRUPF Interrupt Enable

`pub fn icacherr(&mut self) -> ICACHERR_W`[src]

Bit 5 - ICACHERR Interrupt Enable

`impl W<u32, Reg<u32, _LOCK>>`[src]

`pub fn lockkey(&mut self) -> LOCKKEY_W`[src]

Bits 0:15 - Configuration Lock

`impl W<u32, Reg<u32, _CACHECMD>>`[src]

`pub fn invcache(&mut self) -> INVCACHE_W`[src]

Bit 0 - Invalidate Instruction Cache

`pub fn startpc(&mut self) -> STARTPC_W`[src]

Bit 1 - Start Performance Counters

`pub fn stoppc(&mut self) -> STOPPC_W`[src]

Bit 2 - Stop Performance Counters

`impl W<u32, Reg<u32, _MASSLOCK>>`[src]

`pub fn lockkey(&mut self) -> LOCKKEY_W`[src]

Bits 0:15 - Mass Erase Lock

`impl W<u32, Reg<u32, _STARTUP>>`[src]

`pub fn stdly0(&mut self) -> STDLY0_W`[src]

Bits 0:9 - Startup Delay 0

`pub fn stdly1(&mut self) -> STDLY1_W`[src]

Bits 12:21 - Startup Delay 0

`pub fn astwait(&mut self) -> ASTWAIT_W`[src]

Bit 24 - Active Startup Wait

`pub fn stwsen(&mut self) -> STWSEN_W`[src]

Bit 25 - Startup Waitstates Enable

`pub fn stwsaen(&mut self) -> STWSAEN_W`[src]

Bit 26 - Startup Waitstates Always Enable

`pub fn stws(&mut self) -> STWS_W`[src]

Bits 28:30 - Startup Waitstates

`impl W<u32, Reg<u32, _CMD>>`[src]

`pub fn pwrup(&mut self) -> PWRUP_W`[src]

Bit 0 - Flash Power Up Command

`impl W<u32, Reg<u32, _CTRL>>`[src]

`pub fn em2block(&mut self) -> EM2BLOCK_W`[src]

Bit 1 - Energy Mode 2 Block

`impl W<u32, Reg<u32, _LOCK>>`[src]

`pub fn lockkey(&mut self) -> LOCKKEY_W`[src]

Bits 0:15 - Configuration Lock Key

`impl W<u32, Reg<u32, _RAM0CTRL>>`[src]

`pub fn rampowerdown(&mut self) -> RAMPOWERDOWN_W`[src]

Bits 0:3 - RAM0 Blockset Power-down

`impl W<u32, Reg<u32, _CMD>>`[src]

`pub fn em4unlatch(&mut self) -> EM4UNLATCH_W`[src]

Bit 0 - EM4 Unlatch

`impl W<u32, Reg<u32, _EM4CTRL>>`[src]

`pub fn em4state(&mut self) -> EM4STATE_W`[src]

Bit 0 - Energy Mode 4 State

`pub fn retainlfrco(&mut self) -> RETAINLFRCO_W`[src]

Bit 1 - LFRCO Retain During EM4

`pub fn retainlfxo(&mut self) -> RETAINLFXO_W`[src]

Bit 2 - LFXO Retain During EM4

`pub fn retainulfrco(&mut self) -> RETAINULFRCO_W`[src]

Bit 3 - ULFRCO Retain During EM4S

`pub fn em4ioretmode(&mut self) -> EM4IORETMODE_W`[src]

Bits 4:5 - EM4 IO Retention Disable

`pub fn em4entry(&mut self) -> EM4ENTRY_W`[src]

Bits 16:17 - Energy Mode 4 Entry

`impl W<u32, Reg<u32, _TEMPLIMITS>>`[src]

`pub fn templow(&mut self) -> TEMPLOW_W`[src]

Bits 0:7 - Temperature Low Limit

`pub fn temphigh(&mut self) -> TEMPHIGH_W`[src]

Bits 8:15 - Temperature High Limit

`pub fn em4wuen(&mut self) -> EM4WUEN_W`[src]

Bit 16 - Enable EM4 Wakeup Due to Low/high Temperature

`impl W<u32, Reg<u32, _IFS>>`[src]

`pub fn vmonavddfall(&mut self) -> VMONAVDDFALL_W`[src]

Bit 0 - Set VMONAVDDFALL Interrupt Flag

`pub fn vmonavddrise(&mut self) -> VMONAVDDRISE_W`[src]

Bit 1 - Set VMONAVDDRISE Interrupt Flag

`pub fn vmonaltavddfall(&mut self) -> VMONALTAVDDFALL_W`[src]

Bit 2 - Set VMONALTAVDDFALL Interrupt Flag

`pub fn vmonaltavddrise(&mut self) -> VMONALTAVDDRISE_W`[src]

Bit 3 - Set VMONALTAVDDRISE Interrupt Flag

`pub fn vmondvddfall(&mut self) -> VMONDVDDFALL_W`[src]

Bit 4 - Set VMONDVDDFALL Interrupt Flag

`pub fn vmondvddrise(&mut self) -> VMONDVDDRISE_W`[src]

Bit 5 - Set VMONDVDDRISE Interrupt Flag

`pub fn vmonio0fall(&mut self) -> VMONIO0FALL_W`[src]

Bit 6 - Set VMONIO0FALL Interrupt Flag

`pub fn vmonio0rise(&mut self) -> VMONIO0RISE_W`[src]

Bit 7 - Set VMONIO0RISE Interrupt Flag

`pub fn vmonfvddfall(&mut self) -> VMONFVDDFALL_W`[src]

Bit 14 - Set VMONFVDDFALL Interrupt Flag

`pub fn vmonfvddrise(&mut self) -> VMONFVDDRISE_W`[src]

Bit 15 - Set VMONFVDDRISE Interrupt Flag

`pub fn pfetovercurrentlimit(&mut self) -> PFETOVERCURRENTLIMIT_W`[src]

Bit 16 - Set PFETOVERCURRENTLIMIT Interrupt Flag

`pub fn nfetovercurrentlimit(&mut self) -> NFETOVERCURRENTLIMIT_W`[src]

Bit 17 - Set NFETOVERCURRENTLIMIT Interrupt Flag

`pub fn dcdclprunning(&mut self) -> DCDCLPRUNNING_W`[src]

Bit 18 - Set DCDCLPRUNNING Interrupt Flag

`pub fn dcdclnrunning(&mut self) -> DCDCLNRUNNING_W`[src]

Bit 19 - Set DCDCLNRUNNING Interrupt Flag

`pub fn dcdcinbypass(&mut self) -> DCDCINBYPASS_W`[src]

Bit 20 - Set DCDCINBYPASS Interrupt Flag

`pub fn em23wakeup(&mut self) -> EM23WAKEUP_W`[src]

Bit 24 - Set EM23WAKEUP Interrupt Flag

`pub fn temp(&mut self) -> TEMP_W`[src]

Bit 29 - Set TEMP Interrupt Flag

`pub fn templow(&mut self) -> TEMPLOW_W`[src]

Bit 30 - Set TEMPLOW Interrupt Flag

`pub fn temphigh(&mut self) -> TEMPHIGH_W`[src]

Bit 31 - Set TEMPHIGH Interrupt Flag

`impl W<u32, Reg<u32, _IFC>>`[src]

`pub fn vmonavddfall(&mut self) -> VMONAVDDFALL_W`[src]

Bit 0 - Clear VMONAVDDFALL Interrupt Flag

`pub fn vmonavddrise(&mut self) -> VMONAVDDRISE_W`[src]

Bit 1 - Clear VMONAVDDRISE Interrupt Flag

`pub fn vmonaltavddfall(&mut self) -> VMONALTAVDDFALL_W`[src]

Bit 2 - Clear VMONALTAVDDFALL Interrupt Flag

`pub fn vmonaltavddrise(&mut self) -> VMONALTAVDDRISE_W`[src]

Bit 3 - Clear VMONALTAVDDRISE Interrupt Flag

`pub fn vmondvddfall(&mut self) -> VMONDVDDFALL_W`[src]

Bit 4 - Clear VMONDVDDFALL Interrupt Flag

`pub fn vmondvddrise(&mut self) -> VMONDVDDRISE_W`[src]

Bit 5 - Clear VMONDVDDRISE Interrupt Flag

`pub fn vmonio0fall(&mut self) -> VMONIO0FALL_W`[src]

Bit 6 - Clear VMONIO0FALL Interrupt Flag

`pub fn vmonio0rise(&mut self) -> VMONIO0RISE_W`[src]

Bit 7 - Clear VMONIO0RISE Interrupt Flag

`pub fn vmonfvddfall(&mut self) -> VMONFVDDFALL_W`[src]

Bit 14 - Clear VMONFVDDFALL Interrupt Flag

`pub fn vmonfvddrise(&mut self) -> VMONFVDDRISE_W`[src]

Bit 15 - Clear VMONFVDDRISE Interrupt Flag

`pub fn pfetovercurrentlimit(&mut self) -> PFETOVERCURRENTLIMIT_W`[src]

Bit 16 - Clear PFETOVERCURRENTLIMIT Interrupt Flag

`pub fn nfetovercurrentlimit(&mut self) -> NFETOVERCURRENTLIMIT_W`[src]

Bit 17 - Clear NFETOVERCURRENTLIMIT Interrupt Flag

`pub fn dcdclprunning(&mut self) -> DCDCLPRUNNING_W`[src]

Bit 18 - Clear DCDCLPRUNNING Interrupt Flag

`pub fn dcdclnrunning(&mut self) -> DCDCLNRUNNING_W`[src]

Bit 19 - Clear DCDCLNRUNNING Interrupt Flag

`pub fn dcdcinbypass(&mut self) -> DCDCINBYPASS_W`[src]

Bit 20 - Clear DCDCINBYPASS Interrupt Flag

`pub fn em23wakeup(&mut self) -> EM23WAKEUP_W`[src]

Bit 24 - Clear EM23WAKEUP Interrupt Flag

`pub fn temp(&mut self) -> TEMP_W`[src]

Bit 29 - Clear TEMP Interrupt Flag

`pub fn templow(&mut self) -> TEMPLOW_W`[src]

Bit 30 - Clear TEMPLOW Interrupt Flag

`pub fn temphigh(&mut self) -> TEMPHIGH_W`[src]

Bit 31 - Clear TEMPHIGH Interrupt Flag

`impl W<u32, Reg<u32, _IEN>>`[src]

`pub fn vmonavddfall(&mut self) -> VMONAVDDFALL_W`[src]

Bit 0 - VMONAVDDFALL Interrupt Enable

`pub fn vmonavddrise(&mut self) -> VMONAVDDRISE_W`[src]

Bit 1 - VMONAVDDRISE Interrupt Enable

`pub fn vmonaltavddfall(&mut self) -> VMONALTAVDDFALL_W`[src]

Bit 2 - VMONALTAVDDFALL Interrupt Enable

`pub fn vmonaltavddrise(&mut self) -> VMONALTAVDDRISE_W`[src]

Bit 3 - VMONALTAVDDRISE Interrupt Enable

`pub fn vmondvddfall(&mut self) -> VMONDVDDFALL_W`[src]

Bit 4 - VMONDVDDFALL Interrupt Enable

`pub fn vmondvddrise(&mut self) -> VMONDVDDRISE_W`[src]

Bit 5 - VMONDVDDRISE Interrupt Enable

`pub fn vmonio0fall(&mut self) -> VMONIO0FALL_W`[src]

Bit 6 - VMONIO0FALL Interrupt Enable

`pub fn vmonio0rise(&mut self) -> VMONIO0RISE_W`[src]

Bit 7 - VMONIO0RISE Interrupt Enable

`pub fn vmonfvddfall(&mut self) -> VMONFVDDFALL_W`[src]

Bit 14 - VMONFVDDFALL Interrupt Enable

`pub fn vmonfvddrise(&mut self) -> VMONFVDDRISE_W`[src]

Bit 15 - VMONFVDDRISE Interrupt Enable

`pub fn pfetovercurrentlimit(&mut self) -> PFETOVERCURRENTLIMIT_W`[src]

Bit 16 - PFETOVERCURRENTLIMIT Interrupt Enable

`pub fn nfetovercurrentlimit(&mut self) -> NFETOVERCURRENTLIMIT_W`[src]

Bit 17 - NFETOVERCURRENTLIMIT Interrupt Enable

`pub fn dcdclprunning(&mut self) -> DCDCLPRUNNING_W`[src]

Bit 18 - DCDCLPRUNNING Interrupt Enable

`pub fn dcdclnrunning(&mut self) -> DCDCLNRUNNING_W`[src]

Bit 19 - DCDCLNRUNNING Interrupt Enable

`pub fn dcdcinbypass(&mut self) -> DCDCINBYPASS_W`[src]

Bit 20 - DCDCINBYPASS Interrupt Enable

`pub fn em23wakeup(&mut self) -> EM23WAKEUP_W`[src]

Bit 24 - EM23WAKEUP Interrupt Enable

`pub fn temp(&mut self) -> TEMP_W`[src]

Bit 29 - TEMP Interrupt Enable

`pub fn templow(&mut self) -> TEMPLOW_W`[src]

Bit 30 - TEMPLOW Interrupt Enable

`pub fn temphigh(&mut self) -> TEMPHIGH_W`[src]

Bit 31 - TEMPHIGH Interrupt Enable

`impl W<u32, Reg<u32, _PWRLOCK>>`[src]

`pub fn lockkey(&mut self) -> LOCKKEY_W`[src]

Bits 0:15 - Regulator and Supply Configuration Lock Key

`impl W<u32, Reg<u32, _PWRCFG>>`[src]

`pub fn pwrcfg(&mut self) -> PWRCFG_W`[src]

Bits 0:3 - Power Configuration

`impl W<u32, Reg<u32, _PWRCTRL>>`[src]

`pub fn anasw(&mut self) -> ANASW_W`[src]

Bit 5 - Analog Switch Selection

`impl W<u32, Reg<u32, _DCDCCTRL>>`[src]

`pub fn dcdcmode(&mut self) -> DCDCMODE_W`[src]

Bits 0:1 - Regulator Mode

`pub fn dcdcmodeem23(&mut self) -> DCDCMODEEM23_W`[src]

Bit 4 - DCDC Mode EM23

`pub fn dcdcmodeem4(&mut self) -> DCDCMODEEM4_W`[src]

Bit 5 - DCDC Mode EM4H

`impl W<u32, Reg<u32, _DCDCMISCCTRL>>`[src]

`pub fn lnforceccm(&mut self) -> LNFORCECCM_W`[src]

Bit 0 - Force DCDC Into CCM Mode in Low Noise Operation

`pub fn pfetcnt(&mut self) -> PFETCNT_W`[src]

Bits 8:11 - PFET Switch Number Selection

`pub fn nfetcnt(&mut self) -> NFETCNT_W`[src]

Bits 12:15 - NFET Switch Number Selection

`pub fn byplimsel(&mut self) -> BYPLIMSEL_W`[src]

Bits 16:19 - Current Limit in Bypass Mode

`pub fn lpclimilimsel(&mut self) -> LPCLIMILIMSEL_W`[src]

Bits 20:22 - Current Limit Level Selection for Current Limiter in LP Mode

`pub fn lnclimilimsel(&mut self) -> LNCLIMILIMSEL_W`[src]

Bits 24:26 - Current Limit Level Selection for Current Limiter in LN Mode

`pub fn lpcmpbias(&mut self) -> LPCMPBIAS_W`[src]

Bits 28:29 - LP Mode Comparator Bias Selection

`impl W<u32, Reg<u32, _DCDCZDETCTRL>>`[src]

`pub fn zdetilimsel(&mut self) -> ZDETILIMSEL_W`[src]

Bits 4:6 - Reverse Current Limit Level Selection for Zero Detector

`pub fn zdetblankdly(&mut self) -> ZDETBLANKDLY_W`[src]

Bits 8:9 - Reserved for internal use. Do not change.

`impl W<u32, Reg<u32, _DCDCCLIMCTRL>>`[src]

`pub fn climblankdly(&mut self) -> CLIMBLANKDLY_W`[src]

Bits 8:9 - Reserved for internal use. Do not change.

`pub fn byplimen(&mut self) -> BYPLIMEN_W`[src]

Bit 13 - Bypass Current Limit Enable

`impl W<u32, Reg<u32, _DCDCLNCOMPCTRL>>`[src]

`pub fn compenr1(&mut self) -> COMPENR1_W`[src]

Bits 0:2 - Low Noise Mode Compensator R1 Trim Value

`pub fn compenr2(&mut self) -> COMPENR2_W`[src]

Bits 4:8 - Low Noise Mode Compensator R2 Trim Value

`pub fn compenr3(&mut self) -> COMPENR3_W`[src]

Bits 12:15 - Low Noise Mode Compensator R3 Trim Value

`pub fn compenc1(&mut self) -> COMPENC1_W`[src]

Bits 20:21 - Low Noise Mode Compensator C1 Trim Value

`pub fn compenc2(&mut self) -> COMPENC2_W`[src]

Bits 24:26 - Low Noise Mode Compensator C2 Trim Value

`pub fn compenc3(&mut self) -> COMPENC3_W`[src]

Bits 28:31 - Low Noise Mode Compensator C3 Trim Value

`impl W<u32, Reg<u32, _DCDCLNVCTRL>>`[src]

`pub fn lnatt(&mut self) -> LNATT_W`[src]

Bit 1 - Low Noise Mode Feedback Attenuation

`pub fn lnvref(&mut self) -> LNVREF_W`[src]

Bits 8:14 - Low Noise Mode VREF Trim

`impl W<u32, Reg<u32, _DCDCTIMING>>`[src]

`pub fn lpinitwait(&mut self) -> LPINITWAIT_W`[src]

Bits 0:7 - Low Power Initialization Wait Time

`pub fn compenprchgen(&mut self) -> COMPENPRCHGEN_W`[src]

Bit 11 - LN Mode Precharge Enable

`pub fn lnwait(&mut self) -> LNWAIT_W`[src]

Bits 12:16 - Low Noise Controller Initialization Wait Time

`pub fn bypwait(&mut self) -> BYPWAIT_W`[src]

Bits 20:27 - Bypass Mode Transition From Low Power or Low Noise Modes Wait Wait

`pub fn dutyscale(&mut self) -> DUTYSCALE_W`[src]

Bits 29:30 - Select Bias Duty Cycle Clock

`impl W<u32, Reg<u32, _DCDCLPVCTRL>>`[src]

`pub fn lpatt(&mut self) -> LPATT_W`[src]

Bit 0 - Low Power Feedback Attenuation

`pub fn lpvref(&mut self) -> LPVREF_W`[src]

Bits 1:8 - LP Mode Reference Selection for EM23 and EM4H

`impl W<u32, Reg<u32, _DCDCLPCTRL>>`[src]

`pub fn lpcmphyssel(&mut self) -> LPCMPHYSSEL_W`[src]

Bits 12:15 - LP Mode Hysteresis Selection

`pub fn lpvrefdutyen(&mut self) -> LPVREFDUTYEN_W`[src]

Bit 24 - LP Mode Duty Cycling Enable

`pub fn lpblank(&mut self) -> LPBLANK_W`[src]

Bits 25:26 - Reserved for internal use. Do not change.

`impl W<u32, Reg<u32, _DCDCLNFREQCTRL>>`[src]

`pub fn rcoband(&mut self) -> RCOBAND_W`[src]

Bits 0:2 - LN Mode RCO Frequency Band Selection

`pub fn rcotrim(&mut self) -> RCOTRIM_W`[src]

Bits 24:28 - Reserved for internal use. Do not change.

`impl W<u32, Reg<u32, _VMONAVDDCTRL>>`[src]

`pub fn en(&mut self) -> EN_W`[src]

Bit 0 - Enable

`pub fn risewu(&mut self) -> RISEWU_W`[src]

Bit 2 - Rise Wakeup

`pub fn fallwu(&mut self) -> FALLWU_W`[src]

Bit 3 - Fall Wakeup

`pub fn fallthresfine(&mut self) -> FALLTHRESFINE_W`[src]

Bits 8:11 - Falling Threshold Fine Adjust

`pub fn fallthrescoarse(&mut self) -> FALLTHRESCOARSE_W`[src]

Bits 12:15 - Falling Threshold Coarse Adjust

`pub fn risethresfine(&mut self) -> RISETHRESFINE_W`[src]

Bits 16:19 - Rising Threshold Fine Adjust

`pub fn risethrescoarse(&mut self) -> RISETHRESCOARSE_W`[src]

Bits 20:23 - Rising Threshold Coarse Adjust

`impl W<u32, Reg<u32, _VMONALTAVDDCTRL>>`[src]

`pub fn en(&mut self) -> EN_W`[src]

Bit 0 - Enable

`pub fn risewu(&mut self) -> RISEWU_W`[src]

Bit 2 - Rise Wakeup

`pub fn fallwu(&mut self) -> FALLWU_W`[src]

Bit 3 - Fall Wakeup

`pub fn thresfine(&mut self) -> THRESFINE_W`[src]

Bits 8:11 - Threshold Fine Adjust

`pub fn threscoarse(&mut self) -> THRESCOARSE_W`[src]

Bits 12:15 - Threshold Coarse Adjust

`impl W<u32, Reg<u32, _VMONDVDDCTRL>>`[src]

`pub fn en(&mut self) -> EN_W`[src]

Bit 0 - Enable

`pub fn risewu(&mut self) -> RISEWU_W`[src]

Bit 2 - Rise Wakeup

`pub fn fallwu(&mut self) -> FALLWU_W`[src]

Bit 3 - Fall Wakeup

`pub fn thresfine(&mut self) -> THRESFINE_W`[src]

Bits 8:11 - Threshold Fine Adjust

`pub fn threscoarse(&mut self) -> THRESCOARSE_W`[src]

Bits 12:15 - Threshold Coarse Adjust

`impl W<u32, Reg<u32, _VMONIO0CTRL>>`[src]

`pub fn en(&mut self) -> EN_W`[src]

Bit 0 - Enable

`pub fn risewu(&mut self) -> RISEWU_W`[src]

Bit 2 - Rise Wakeup

`pub fn fallwu(&mut self) -> FALLWU_W`[src]

Bit 3 - Fall Wakeup

`pub fn retdis(&mut self) -> RETDIS_W`[src]

Bit 4 - EM4 IO0 Retention Disable

`pub fn thresfine(&mut self) -> THRESFINE_W`[src]

Bits 8:11 - Threshold Fine Adjust

`pub fn threscoarse(&mut self) -> THRESCOARSE_W`[src]

Bits 12:15 - Threshold Coarse Adjust

`impl W<u32, Reg<u32, _BIASCONF>>`[src]

`pub fn nadutyem01(&mut self) -> NADUTYEM01_W`[src]

Bit 2 - NA DUTY in EM01

`pub fn lpem01(&mut self) -> LPEM01_W`[src]

Bit 3 - LP in EM01

`pub fn gmcem23(&mut self) -> GMCEM23_W`[src]

Bit 4 - GMC in EM234

`pub fn uadutyem23(&mut self) -> UADUTYEM23_W`[src]

Bit 5 - UADUTY in EM234

`pub fn nadutyem23(&mut self) -> NADUTYEM23_W`[src]

Bit 6 - NA DUTY in EM234

`pub fn lpem23(&mut self) -> LPEM23_W`[src]

Bit 7 - LP in EM234

`impl W<u32, Reg<u32, _TESTLOCK>>`[src]

`pub fn lockkey(&mut self) -> LOCKKEY_W`[src]

Bits 0:15 - Configuration Lock Key

`impl W<u32, Reg<u32, _BIASTESTCTRL>>`[src]

`pub fn bias_rip_reset(&mut self) -> BIAS_RIP_RESET_W`[src]

Bit 3 - Reset Bias Ripple Counter

`impl W<u32, Reg<u32, _CTRL>>`[src]

`pub fn wdogrmode(&mut self) -> WDOGRMODE_W`[src]

Bits 0:2 - WDOG Reset Mode

`pub fn lockuprmode(&mut self) -> LOCKUPRMODE_W`[src]

Bits 4:6 - Core LOCKUP Reset Mode

`pub fn sysrmode(&mut self) -> SYSRMODE_W`[src]

Bits 8:10 - Core Sysreset Reset Mode

`pub fn pinrmode(&mut self) -> PINRMODE_W`[src]

Bits 12:14 - PIN Reset Mode

`pub fn resetstate(&mut self) -> RESETSTATE_W`[src]

Bits 24:25 - System Software Reset State

`impl W<u32, Reg<u32, _CMD>>`[src]

`pub fn rcclr(&mut self) -> RCCLR_W`[src]

Bit 0 - Reset Cause Clear

`impl W<u32, Reg<u32, _LOCK>>`[src]

`pub fn lockkey(&mut self) -> LOCKKEY_W`[src]

Bits 0:15 - Configuration Lock Key

`impl W<u32, Reg<u32, _CTRL>>`[src]

`pub fn clkoutsel0(&mut self) -> CLKOUTSEL0_W`[src]

Bits 0:3 - Clock Output Select 0

`pub fn clkoutsel1(&mut self) -> CLKOUTSEL1_W`[src]

Bits 5:8 - Clock Output Select 1

`pub fn wshfle(&mut self) -> WSHFLE_W`[src]

Bit 16 - Wait State for High-Frequency LE Interface

`pub fn hfperclken(&mut self) -> HFPERCLKEN_W`[src]

Bit 20 - HFPERCLK Enable

`impl W<u32, Reg<u32, _HFRCOCTRL>>`[src]

`pub fn tuning(&mut self) -> TUNING_W`[src]

Bits 0:6 - HFRCO Tuning Value

`pub fn finetuning(&mut self) -> FINETUNING_W`[src]

Bits 8:13 - HFRCO Fine Tuning Value

`pub fn freqrange(&mut self) -> FREQRANGE_W`[src]

Bits 16:20 - HFRCO Frequency Range

`pub fn cmpbias(&mut self) -> CMPBIAS_W`[src]

Bits 21:23 - HFRCO Comparator Bias Current

`pub fn ldohp(&mut self) -> LDOHP_W`[src]

Bit 24 - HFRCO LDO High Power Mode

`pub fn clkdiv(&mut self) -> CLKDIV_W`[src]

Bits 25:26 - Locally Divide HFRCO Clock Output

`pub fn finetuningen(&mut self) -> FINETUNINGEN_W`[src]

Bit 27 - Enable Reference for Fine Tuning

`pub fn vreftc(&mut self) -> VREFTC_W`[src]

Bits 28:31 - HFRCO Temperature Coefficient Trim on Comparator Reference

`impl W<u32, Reg<u32, _AUXHFRCOCTRL>>`[src]

`pub fn tuning(&mut self) -> TUNING_W`[src]

Bits 0:6 - AUXHFRCO Tuning Value

`pub fn finetuning(&mut self) -> FINETUNING_W`[src]

Bits 8:13 - AUXHFRCO Fine Tuning Value

`pub fn freqrange(&mut self) -> FREQRANGE_W`[src]

Bits 16:20 - AUXHFRCO Frequency Range

`pub fn cmpbias(&mut self) -> CMPBIAS_W`[src]

Bits 21:23 - AUXHFRCO Comparator Bias Current

`pub fn ldohp(&mut self) -> LDOHP_W`[src]

Bit 24 - AUXHFRCO LDO High Power Mode

`pub fn clkdiv(&mut self) -> CLKDIV_W`[src]

Bits 25:26 - Locally Divide AUXHFRCO Clock Output

`pub fn finetuningen(&mut self) -> FINETUNINGEN_W`[src]

Bit 27 - Enable Reference for Fine Tuning

`pub fn vreftc(&mut self) -> VREFTC_W`[src]

Bits 28:31 - AUXHFRCO Temperature Coefficient Trim on Comparator Reference

`impl W<u32, Reg<u32, _LFRCOCTRL>>`[src]

`pub fn tuning(&mut self) -> TUNING_W`[src]

Bits 0:8 - LFRCO Tuning Value

`pub fn envref(&mut self) -> ENVREF_W`[src]

Bit 16 - Enable Duty Cycling of Vref

`pub fn enchop(&mut self) -> ENCHOP_W`[src]

Bit 17 - Enable Comparator Chopping

`pub fn endem(&mut self) -> ENDEM_W`[src]

Bit 18 - Enable Dynamic Element Matching

`pub fn timeout(&mut self) -> TIMEOUT_W`[src]

Bits 24:25 - LFRCO Timeout

`pub fn gmccurtune(&mut self) -> GMCCURTUNE_W`[src]

Bits 28:31 - Tuning of Gmc Current

`impl W<u32, Reg<u32, _HFXOCTRL>>`[src]

`pub fn mode(&mut self) -> MODE_W`[src]

Bit 0 - HFXO Mode

`pub fn peakdetshuntoptmode(&mut self) -> PEAKDETSHUNTOPTMODE_W`[src]

Bits 4:5 - HFXO Automatic Peak Detection and Shunt Current Optimization Mode

`pub fn lowpower(&mut self) -> LOWPOWER_W`[src]

Bit 8 - Low Power Mode Control

`pub fn xti2gnd(&mut self) -> XTI2GND_W`[src]

Bit 9 - Clamp HFXTAL_N Pin to Ground When HFXO Oscillator is Off

`pub fn xto2gnd(&mut self) -> XTO2GND_W`[src]

Bit 10 - Clamp HFXTAL_P Pin to Ground When HFXO Oscillator is Off

`pub fn lftimeout(&mut self) -> LFTIMEOUT_W`[src]

Bits 24:26 - HFXO Low Frequency Timeout

`pub fn autostartem0em1(&mut self) -> AUTOSTARTEM0EM1_W`[src]

Bit 28 - Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3

`pub fn autostartselem0em1(&mut self) -> AUTOSTARTSELEM0EM1_W`[src]

Bit 29 - Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3

`impl W<u32, Reg<u32, _HFXOCTRL1>>`[src]

`pub fn peakdetthr(&mut self) -> PEAKDETTHR_W`[src]

Bits 0:2 - Sets the Peak Detector amplitude detection threshold levels

`pub fn reglvl(&mut self) -> REGLVL_W`[src]

Bits 4:6 - Reserved for internal use. Do not change.

`pub fn xtibiasen(&mut self) -> XTIBIASEN_W`[src]

Bit 9 - Reserved for internal use. Do not change.

`impl W<u32, Reg<u32, _HFXOSTARTUPCTRL>>`[src]

`pub fn ibtrimxocore(&mut self) -> IBTRIMXOCORE_W`[src]

Bits 0:6 - Sets the Startup Oscillator Core Bias Current

`pub fn ctune(&mut self) -> CTUNE_W`[src]

Bits 11:19 - Sets Oscillator Tuning Capacitance

`pub fn reserved0(&mut self) -> RESERVED0_W`[src]

Bits 21:27 - This Field is Reserved. It Should Be Set to 0x9

`pub fn reserved1(&mut self) -> RESERVED1_W`[src]

Bits 28:31 - Sets the Regulator Output Current Level (shunt Regulator)

`impl W<u32, Reg<u32, _HFXOSTEADYSTATECTRL>>`[src]

`pub fn ibtrimxocore(&mut self) -> IBTRIMXOCORE_W`[src]

Bits 0:6 - Sets the Steady State Oscillator Core Bias Current.

`pub fn regish(&mut self) -> REGISH_W`[src]

Bits 7:10 - Sets the Steady State Regulator Output Current Level (shunt Regulator)

`pub fn ctune(&mut self) -> CTUNE_W`[src]

Bits 11:19 - Sets Oscillator Tuning Capacitance

`pub fn regselilow(&mut self) -> REGSELILOW_W`[src]

Bits 24:25 - Controls Regulator Minimum Shunt Current Detection Relative to Nominal

`pub fn peakdeten(&mut self) -> PEAKDETEN_W`[src]

Bit 26 - Enables Oscillator Peak Detectors

`pub fn regishupper(&mut self) -> REGISHUPPER_W`[src]

Bits 28:31 - Set Regulator Output Current Level (shunt Regulator). Ish = 120uA + REGISHUPPER X 120uA

`impl W<u32, Reg<u32, _HFXOTIMEOUTCTRL>>`[src]

`pub fn startuptimeout(&mut self) -> STARTUPTIMEOUT_W`[src]

Bits 0:3 - Wait Duration in HFXO Startup Enable Wait State

`pub fn steadytimeout(&mut self) -> STEADYTIMEOUT_W`[src]

Bits 4:7 - Wait Duration in HFXO Startup Steady Wait State

`pub fn reserved2(&mut self) -> RESERVED2_W`[src]

Bits 8:11 - Wait Duration in HFXO Warm Startup Steady Wait State

`pub fn peakdettimeout(&mut self) -> PEAKDETTIMEOUT_W`[src]

Bits 12:15 - Wait Duration in HFXO Peak Detection Wait State

`pub fn shuntopttimeout(&mut self) -> SHUNTOPTTIMEOUT_W`[src]

Bits 16:19 - Wait Duration in HFXO Shunt Current Optimization Wait State

`impl W<u32, Reg<u32, _LFXOCTRL>>`[src]

`pub fn tuning(&mut self) -> TUNING_W`[src]

Bits 0:6 - LFXO Internal Capacitor Array Tuning Value

`pub fn mode(&mut self) -> MODE_W`[src]

Bits 8:9 - LFXO Mode

`pub fn gain(&mut self) -> GAIN_W`[src]

Bits 11:12 - LFXO Startup Gain

`pub fn highampl(&mut self) -> HIGHAMPL_W`[src]

Bit 14 - LFXO High XTAL Oscillation Amplitude Enable

`pub fn agc(&mut self) -> AGC_W`[src]

Bit 15 - LFXO AGC Enable

`pub fn cur(&mut self) -> CUR_W`[src]

Bits 16:17 - LFXO Current Trim

`pub fn bufcur(&mut self) -> BUFCUR_W`[src]

Bit 20 - LFXO Buffer Bias Current

`pub fn timeout(&mut self) -> TIMEOUT_W`[src]

Bits 24:26 - LFXO Timeout

`impl W<u32, Reg<u32, _ULFRCOCTRL>>`[src]

`pub fn tuning(&mut self) -> TUNING_W`[src]

Bits 0:5 - ULFRCO TUNING Value

`pub fn mode(&mut self) -> MODE_W`[src]

Bits 10:11 - ULFRCO Mode

`pub fn restrim(&mut self) -> RESTRIM_W`[src]

Bits 16:17 - ULFRCO Resistor Trim Value (for Resistor in Bias Circuit; NOT for USE as FREQUENCY CALIBRATION)

`impl W<u32, Reg<u32, _CALCTRL>>`[src]

`pub fn upsel(&mut self) -> UPSEL_W`[src]

Bits 0:2 - Calibration Up-counter Select

`pub fn downsel(&mut self) -> DOWNSEL_W`[src]

Bits 4:6 - Calibration Down-counter Select

`pub fn cont(&mut self) -> CONT_W`[src]

Bit 8 - Continuous Calibration

`pub fn prsupsel(&mut self) -> PRSUPSEL_W`[src]

Bits 16:19 - PRS Select for PRS Input When Selected in UPSEL

`pub fn prsdownsel(&mut self) -> PRSDOWNSEL_W`[src]

Bits 24:27 - PRS Select for PRS Input When Selected in DOWNSEL

`impl W<u32, Reg<u32, _CALCNT>>`[src]

`pub fn calcnt(&mut self) -> CALCNT_W`[src]

Bits 0:19 - Calibration Counter

`impl W<u32, Reg<u32, _OSCENCMD>>`[src]

`pub fn hfrcoen(&mut self) -> HFRCOEN_W`[src]

Bit 0 - HFRCO Enable

`pub fn hfrcodis(&mut self) -> HFRCODIS_W`[src]

Bit 1 - HFRCO Disable

`pub fn hfxoen(&mut self) -> HFXOEN_W`[src]

Bit 2 - HFXO Enable

`pub fn hfxodis(&mut self) -> HFXODIS_W`[src]

Bit 3 - HFXO Disable

`pub fn auxhfrcoen(&mut self) -> AUXHFRCOEN_W`[src]

Bit 4 - AUXHFRCO Enable

`pub fn auxhfrcodis(&mut self) -> AUXHFRCODIS_W`[src]

Bit 5 - AUXHFRCO Disable

`pub fn lfrcoen(&mut self) -> LFRCOEN_W`[src]

Bit 6 - LFRCO Enable

`pub fn lfrcodis(&mut self) -> LFRCODIS_W`[src]

Bit 7 - LFRCO Disable

`pub fn lfxoen(&mut self) -> LFXOEN_W`[src]

Bit 8 - LFXO Enable

`pub fn lfxodis(&mut self) -> LFXODIS_W`[src]

Bit 9 - LFXO Disable

`impl W<u32, Reg<u32, _CMD>>`[src]

`pub fn calstart(&mut self) -> CALSTART_W`[src]

Bit 0 - Calibration Start

`pub fn calstop(&mut self) -> CALSTOP_W`[src]

Bit 1 - Calibration Stop

`pub fn hfxopeakdetstart(&mut self) -> HFXOPEAKDETSTART_W`[src]

Bit 4 - HFXO Peak Detection Start

`pub fn hfxoshuntoptstart(&mut self) -> HFXOSHUNTOPTSTART_W`[src]

Bit 5 - HFXO Shunt Current Optimization Start

`impl W<u32, Reg<u32, _DBGCLKSEL>>`[src]

`pub fn dbg(&mut self) -> DBG_W`[src]

Bit 0 - Debug Trace Clock

`impl W<u32, Reg<u32, _HFCLKSEL>>`[src]

`pub fn hf(&mut self) -> HF_W`[src]

Bits 0:2 - HFCLK Select

`impl W<u32, Reg<u32, _LFACLKSEL>>`[src]

`pub fn lfa(&mut self) -> LFA_W`[src]

Bits 0:2 - Clock Select for LFA

`impl W<u32, Reg<u32, _LFBCLKSEL>>`[src]

`pub fn lfb(&mut self) -> LFB_W`[src]

Bits 0:2 - Clock Select for LFB

`impl W<u32, Reg<u32, _LFECLKSEL>>`[src]

`pub fn lfe(&mut self) -> LFE_W`[src]

Bits 0:2 - Clock Select for LFE

`impl W<u32, Reg<u32, _IFS>>`[src]

`pub fn hfrcordy(&mut self) -> HFRCORDY_W`[src]

Bit 0 - Set HFRCORDY Interrupt Flag

`pub fn hfxordy(&mut self) -> HFXORDY_W`[src]

Bit 1 - Set HFXORDY Interrupt Flag

`pub fn lfrcordy(&mut self) -> LFRCORDY_W`[src]

Bit 2 - Set LFRCORDY Interrupt Flag

`pub fn lfxordy(&mut self) -> LFXORDY_W`[src]

Bit 3 - Set LFXORDY Interrupt Flag

`pub fn auxhfrcordy(&mut self) -> AUXHFRCORDY_W`[src]

Bit 4 - Set AUXHFRCORDY Interrupt Flag

`pub fn calrdy(&mut self) -> CALRDY_W`[src]

Bit 5 - Set CALRDY Interrupt Flag

`pub fn calof(&mut self) -> CALOF_W`[src]

Bit 6 - Set CALOF Interrupt Flag

`pub fn hfxodiserr(&mut self) -> HFXODISERR_W`[src]

Bit 8 - Set HFXODISERR Interrupt Flag

`pub fn hfxoautosw(&mut self) -> HFXOAUTOSW_W`[src]

Bit 9 - Set HFXOAUTOSW Interrupt Flag

`pub fn hfxopeakdeterr(&mut self) -> HFXOPEAKDETERR_W`[src]

Bit 10 - Set HFXOPEAKDETERR Interrupt Flag

`pub fn hfxopeakdetrdy(&mut self) -> HFXOPEAKDETRDY_W`[src]

Bit 11 - Set HFXOPEAKDETRDY Interrupt Flag

`pub fn hfxoshuntoptrdy(&mut self) -> HFXOSHUNTOPTRDY_W`[src]

Bit 12 - Set HFXOSHUNTOPTRDY Interrupt Flag

`pub fn hfrcodis(&mut self) -> HFRCODIS_W`[src]

Bit 13 - Set HFRCODIS Interrupt Flag

`pub fn lftimeouterr(&mut self) -> LFTIMEOUTERR_W`[src]

Bit 14 - Set LFTIMEOUTERR Interrupt Flag

`pub fn cmuerr(&mut self) -> CMUERR_W`[src]

Bit 31 - Set CMUERR Interrupt Flag

`impl W<u32, Reg<u32, _IFC>>`[src]

`pub fn hfrcordy(&mut self) -> HFRCORDY_W`[src]

Bit 0 - Clear HFRCORDY Interrupt Flag

`pub fn hfxordy(&mut self) -> HFXORDY_W`[src]

Bit 1 - Clear HFXORDY Interrupt Flag

`pub fn lfrcordy(&mut self) -> LFRCORDY_W`[src]

Bit 2 - Clear LFRCORDY Interrupt Flag

`pub fn lfxordy(&mut self) -> LFXORDY_W`[src]

Bit 3 - Clear LFXORDY Interrupt Flag

`pub fn auxhfrcordy(&mut self) -> AUXHFRCORDY_W`[src]

Bit 4 - Clear AUXHFRCORDY Interrupt Flag

`pub fn calrdy(&mut self) -> CALRDY_W`[src]

Bit 5 - Clear CALRDY Interrupt Flag

`pub fn calof(&mut self) -> CALOF_W`[src]

Bit 6 - Clear CALOF Interrupt Flag

`pub fn hfxodiserr(&mut self) -> HFXODISERR_W`[src]

Bit 8 - Clear HFXODISERR Interrupt Flag

`pub fn hfxoautosw(&mut self) -> HFXOAUTOSW_W`[src]

Bit 9 - Clear HFXOAUTOSW Interrupt Flag

`pub fn hfxopeakdeterr(&mut self) -> HFXOPEAKDETERR_W`[src]

Bit 10 - Clear HFXOPEAKDETERR Interrupt Flag

`pub fn hfxopeakdetrdy(&mut self) -> HFXOPEAKDETRDY_W`[src]

Bit 11 - Clear HFXOPEAKDETRDY Interrupt Flag

`pub fn hfxoshuntoptrdy(&mut self) -> HFXOSHUNTOPTRDY_W`[src]

Bit 12 - Clear HFXOSHUNTOPTRDY Interrupt Flag

`pub fn hfrcodis(&mut self) -> HFRCODIS_W`[src]

Bit 13 - Clear HFRCODIS Interrupt Flag

`pub fn lftimeouterr(&mut self) -> LFTIMEOUTERR_W`[src]

Bit 14 - Clear LFTIMEOUTERR Interrupt Flag

`pub fn cmuerr(&mut self) -> CMUERR_W`[src]

Bit 31 - Clear CMUERR Interrupt Flag

`impl W<u32, Reg<u32, _IEN>>`[src]

`pub fn hfrcordy(&mut self) -> HFRCORDY_W`[src]

Bit 0 - HFRCORDY Interrupt Enable

`pub fn hfxordy(&mut self) -> HFXORDY_W`[src]

Bit 1 - HFXORDY Interrupt Enable

`pub fn lfrcordy(&mut self) -> LFRCORDY_W`[src]

Bit 2 - LFRCORDY Interrupt Enable

`pub fn lfxordy(&mut self) -> LFXORDY_W`[src]

Bit 3 - LFXORDY Interrupt Enable

`pub fn auxhfrcordy(&mut self) -> AUXHFRCORDY_W`[src]

Bit 4 - AUXHFRCORDY Interrupt Enable

`pub fn calrdy(&mut self) -> CALRDY_W`[src]

Bit 5 - CALRDY Interrupt Enable

`pub fn calof(&mut self) -> CALOF_W`[src]

Bit 6 - CALOF Interrupt Enable

`pub fn hfxodiserr(&mut self) -> HFXODISERR_W`[src]

Bit 8 - HFXODISERR Interrupt Enable

`pub fn hfxoautosw(&mut self) -> HFXOAUTOSW_W`[src]

Bit 9 - HFXOAUTOSW Interrupt Enable

`pub fn hfxopeakdeterr(&mut self) -> HFXOPEAKDETERR_W`[src]

Bit 10 - HFXOPEAKDETERR Interrupt Enable

`pub fn hfxopeakdetrdy(&mut self) -> HFXOPEAKDETRDY_W`[src]

Bit 11 - HFXOPEAKDETRDY Interrupt Enable

`pub fn hfxoshuntoptrdy(&mut self) -> HFXOSHUNTOPTRDY_W`[src]

Bit 12 - HFXOSHUNTOPTRDY Interrupt Enable

`pub fn hfrcodis(&mut self) -> HFRCODIS_W`[src]

Bit 13 - HFRCODIS Interrupt Enable

`pub fn lftimeouterr(&mut self) -> LFTIMEOUTERR_W`[src]

Bit 14 - LFTIMEOUTERR Interrupt Enable

`pub fn cmuerr(&mut self) -> CMUERR_W`[src]

Bit 31 - CMUERR Interrupt Enable

`impl W<u32, Reg<u32, _HFBUSCLKEN0>>`[src]

`pub fn le(&mut self) -> LE_W`[src]

Bit 0 - Low Energy Peripheral Interface Clock Enable

`pub fn crypto(&mut self) -> CRYPTO_W`[src]

Bit 1 - Advanced Encryption Standard Accelerator Clock Enable

`pub fn gpio(&mut self) -> GPIO_W`[src]

Bit 2 - General purpose Input/Output Clock Enable

`pub fn prs(&mut self) -> PRS_W`[src]

Bit 3 - Peripheral Reflex System Clock Enable

`pub fn ldma(&mut self) -> LDMA_W`[src]

Bit 4 - Linked Direct Memory Access Controller Clock Enable

`pub fn gpcrc(&mut self) -> GPCRC_W`[src]

Bit 5 - General Purpose CRC Clock Enable

`impl W<u32, Reg<u32, _HFPERCLKEN0>>`[src]

`pub fn timer0(&mut self) -> TIMER0_W`[src]

Bit 0 - Timer 0 Clock Enable

`pub fn timer1(&mut self) -> TIMER1_W`[src]

Bit 1 - Timer 1 Clock Enable

`pub fn usart0(&mut self) -> USART0_W`[src]

Bit 2 - Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable

`pub fn usart1(&mut self) -> USART1_W`[src]

Bit 3 - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable

`pub fn acmp0(&mut self) -> ACMP0_W`[src]

Bit 4 - Analog Comparator 0 Clock Enable

`pub fn acmp1(&mut self) -> ACMP1_W`[src]

Bit 5 - Analog Comparator 1 Clock Enable

`pub fn cryotimer(&mut self) -> CRYOTIMER_W`[src]

Bit 6 - CRYOTIMER Clock Enable

`pub fn i2c0(&mut self) -> I2C0_W`[src]

Bit 7 - I2C 0 Clock Enable

`pub fn adc0(&mut self) -> ADC0_W`[src]

Bit 8 - Analog to Digital Converter 0 Clock Enable

`pub fn idac0(&mut self) -> IDAC0_W`[src]

Bit 9 - Current Digital to Analog Converter 0 Clock Enable

`impl W<u32, Reg<u32, _LFACLKEN0>>`[src]

`pub fn letimer0(&mut self) -> LETIMER0_W`[src]

Bit 0 - Low Energy Timer 0 Clock Enable

`impl W<u32, Reg<u32, _LFBCLKEN0>>`[src]

`pub fn leuart0(&mut self) -> LEUART0_W`[src]

Bit 0 - Low Energy UART 0 Clock Enable

`impl W<u32, Reg<u32, _LFECLKEN0>>`[src]

`pub fn rtcc(&mut self) -> RTCC_W`[src]

Bit 0 - Real-Time Counter and Calendar Clock Enable

`impl W<u32, Reg<u32, _HFPRESC>>`[src]

`pub fn presc(&mut self) -> PRESC_W`[src]

Bits 8:12 - HFCLK Prescaler

`pub fn hfclklepresc(&mut self) -> HFCLKLEPRESC_W`[src]

Bit 24 - HFCLKLE Prescaler

`impl W<u32, Reg<u32, _HFCOREPRESC>>`[src]

`pub fn presc(&mut self) -> PRESC_W`[src]

Bits 8:16 - HFCORECLK Prescaler

`impl W<u32, Reg<u32, _HFPERPRESC>>`[src]

`pub fn presc(&mut self) -> PRESC_W`[src]

Bits 8:16 - HFPERCLK Prescaler

`impl W<u32, Reg<u32, _HFEXPPRESC>>`[src]

`pub fn presc(&mut self) -> PRESC_W`[src]

Bits 8:12 - HFEXPCLK Prescaler

`impl W<u32, Reg<u32, _LFAPRESC0>>`[src]

`pub fn letimer0(&mut self) -> LETIMER0_W`[src]

Bits 0:3 - Low Energy Timer 0 Prescaler

`impl W<u32, Reg<u32, _LFBPRESC0>>`[src]

`pub fn leuart0(&mut self) -> LEUART0_W`[src]

Bits 0:1 - Low Energy UART 0 Prescaler

`impl W<u32, Reg<u32, _FREEZE>>`[src]

`pub fn regfreeze(&mut self) -> REGFREEZE_W`[src]

Bit 0 - Register Update Freeze

`impl W<u32, Reg<u32, _PCNTCTRL>>`[src]

`pub fn pcnt0clken(&mut self) -> PCNT0CLKEN_W`[src]

Bit 0 - PCNT0 Clock Enable

`pub fn pcnt0clksel(&mut self) -> PCNT0CLKSEL_W`[src]

Bit 1 - PCNT0 Clock Select

`impl W<u32, Reg<u32, _ADCCTRL>>`[src]

`pub fn adc0clksel(&mut self) -> ADC0CLKSEL_W`[src]

Bits 4:5 - ADC0 Clock Select

`pub fn adc0clkinv(&mut self) -> ADC0CLKINV_W`[src]

Bit 8 - Invert Clock Selected By ADC0CLKSEL

`impl W<u32, Reg<u32, _ROUTEPEN>>`[src]

`pub fn clkout0pen(&mut self) -> CLKOUT0PEN_W`[src]

Bit 0 - CLKOUT0 Pin Enable

`pub fn clkout1pen(&mut self) -> CLKOUT1PEN_W`[src]

Bit 1 - CLKOUT1 Pin Enable

`impl W<u32, Reg<u32, _ROUTELOC0>>`[src]

`pub fn clkout0loc(&mut self) -> CLKOUT0LOC_W`[src]

Bits 0:5 - I/O Location

`pub fn clkout1loc(&mut self) -> CLKOUT1LOC_W`[src]

Bits 8:13 - I/O Location

`impl W<u32, Reg<u32, _LOCK>>`[src]

`pub fn lockkey(&mut self) -> LOCKKEY_W`[src]

Bits 0:15 - Configuration Lock Key

`impl W<u32, Reg<u32, _CTRL>>`[src]

`pub fn aes(&mut self) -> AES_W`[src]

Bit 0 - AES Mode

`pub fn keybufdis(&mut self) -> KEYBUFDIS_W`[src]

Bit 1 - Key Buffer Disable

`pub fn sha(&mut self) -> SHA_W`[src]

Bit 2 - SHA Mode

`pub fn nobusystall(&mut self) -> NOBUSYSTALL_W`[src]

Bit 10 - No Stalling of Bus When Busy

`pub fn incwidth(&mut self) -> INCWIDTH_W`[src]

Bits 14:15 - Increment Width

`pub fn dma0mode(&mut self) -> DMA0MODE_W`[src]

Bits 16:17 - DMA0 Read Mode

`pub fn dma0rsel(&mut self) -> DMA0RSEL_W`[src]

Bits 20:21 - DMA0 Read Register Select

`pub fn dma1mode(&mut self) -> DMA1MODE_W`[src]

Bits 24:25 - DMA1 Read Mode

`pub fn dma1rsel(&mut self) -> DMA1RSEL_W`[src]

Bits 28:29 - DATA0 DMA Unaligned Read Register Select

`pub fn combdma0wereq(&mut self) -> COMBDMA0WEREQ_W`[src]

Bit 31 - Combined Data0 Write DMA Request

`impl W<u32, Reg<u32, _WAC>>`[src]

`pub fn modulus(&mut self) -> MODULUS_W`[src]

Bits 0:3 - Modular Operation Modulus

`pub fn modop(&mut self) -> MODOP_W`[src]

Bit 4 - Modular Operation Field Type

`pub fn mulwidth(&mut self) -> MULWIDTH_W`[src]

Bits 8:9 - Multiply Width

`pub fn resultwidth(&mut self) -> RESULTWIDTH_W`[src]

Bits 10:11 - Result Width

`impl W<u32, Reg<u32, _CMD>>`[src]

`pub fn instr(&mut self) -> INSTR_W`[src]

Bits 0:7 - Execute Instruction

`pub fn seqstart(&mut self) -> SEQSTART_W`[src]

Bit 9 - Encryption/Decryption SEQUENCE Start

`pub fn seqstop(&mut self) -> SEQSTOP_W`[src]

Bit 10 - Sequence Stop

`pub fn seqstep(&mut self) -> SEQSTEP_W`[src]

Bit 11 - Sequence Step

`impl W<u32, Reg<u32, _KEY>>`[src]

`pub fn key(&mut self) -> KEY_W`[src]

Bits 0:31 - Key Access

`impl W<u32, Reg<u32, _KEYBUF>>`[src]

`pub fn keybuf(&mut self) -> KEYBUF_W`[src]

Bits 0:31 - Key Buffer Access

`impl W<u32, Reg<u32, _SEQCTRL>>`[src]

`pub fn lengtha(&mut self) -> LENGTHA_W`[src]

Bits 0:13 - Buffer Length a in Bytes

`pub fn blocksize(&mut self) -> BLOCKSIZE_W`[src]

Bits 20:21 - Size of Data Blocks

`pub fn dma0skip(&mut self) -> DMA0SKIP_W`[src]

Bits 24:25 - DMA0 Skip

`pub fn dma1skip(&mut self) -> DMA1SKIP_W`[src]

Bits 26:27 - DMA1 Skip

`pub fn dma0presa(&mut self) -> DMA0PRESA_W`[src]

Bit 28 - DMA0 Preserve a

`pub fn dma1presa(&mut self) -> DMA1PRESA_W`[src]

Bit 29 - DMA1 Preserve a

`pub fn halt(&mut self) -> HALT_W`[src]

Bit 31 - Halt Sequence

`impl W<u32, Reg<u32, _SEQCTRLB>>`[src]

`pub fn lengthb(&mut self) -> LENGTHB_W`[src]

Bits 0:13 - Buffer Length B in Bytes

`pub fn dma0presb(&mut self) -> DMA0PRESB_W`[src]

Bit 28 - DMA0 Preserve B

`pub fn dma1presb(&mut self) -> DMA1PRESB_W`[src]

Bit 29 - DMA1 Preserve B

`impl W<u32, Reg<u32, _IFS>>`[src]

`pub fn instrdone(&mut self) -> INSTRDONE_W`[src]

Bit 0 - Set INSTRDONE Interrupt Flag

`pub fn seqdone(&mut self) -> SEQDONE_W`[src]

Bit 1 - Set SEQDONE Interrupt Flag

`impl W<u32, Reg<u32, _IFC>>`[src]

`pub fn instrdone(&mut self) -> INSTRDONE_W`[src]

Bit 0 - Clear INSTRDONE Interrupt Flag

`pub fn seqdone(&mut self) -> SEQDONE_W`[src]

Bit 1 - Clear SEQDONE Interrupt Flag

`impl W<u32, Reg<u32, _IEN>>`[src]

`pub fn instrdone(&mut self) -> INSTRDONE_W`[src]

Bit 0 - INSTRDONE Interrupt Enable

`pub fn seqdone(&mut self) -> SEQDONE_W`[src]

Bit 1 - SEQDONE Interrupt Enable

`impl W<u32, Reg<u32, _SEQ0>>`[src]

`pub fn instr0(&mut self) -> INSTR0_W`[src]

Bits 0:7 - Sequence Instruction 0

`pub fn instr1(&mut self) -> INSTR1_W`[src]

Bits 8:15 - Sequence Instruction 1

`pub fn instr2(&mut self) -> INSTR2_W`[src]

Bits 16:23 - Sequence Instruction 2

`pub fn instr3(&mut self) -> INSTR3_W`[src]

Bits 24:31 - Sequence Instruction 3

`impl W<u32, Reg<u32, _SEQ1>>`[src]

`pub fn instr4(&mut self) -> INSTR4_W`[src]

Bits 0:7 - Sequence Instruction 4

`pub fn instr5(&mut self) -> INSTR5_W`[src]

Bits 8:15 - Sequence Instruction 5

`pub fn instr6(&mut self) -> INSTR6_W`[src]

Bits 16:23 - Sequence Instruction 6

`pub fn instr7(&mut self) -> INSTR7_W`[src]

Bits 24:31 - Sequence Instruction 7

`impl W<u32, Reg<u32, _SEQ2>>`[src]

`pub fn instr8(&mut self) -> INSTR8_W`[src]

Bits 0:7 - Sequence Instruction 8

`pub fn instr9(&mut self) -> INSTR9_W`[src]

Bits 8:15 - Sequence Instruction 9

`pub fn instr10(&mut self) -> INSTR10_W`[src]

Bits 16:23 - Sequence Instruction 10

`pub fn instr11(&mut self) -> INSTR11_W`[src]

Bits 24:31 - Sequence Instruction 11

`impl W<u32, Reg<u32, _SEQ3>>`[src]

`pub fn instr12(&mut self) -> INSTR12_W`[src]

Bits 0:7 - Sequence Instruction 12

`pub fn instr13(&mut self) -> INSTR13_W`[src]

Bits 8:15 - Sequence Instruction 13

`pub fn instr14(&mut self) -> INSTR14_W`[src]

Bits 16:23 - Sequence Instruction 14

`pub fn instr15(&mut self) -> INSTR15_W`[src]

Bits 24:31 - Sequence Instruction 15

`impl W<u32, Reg<u32, _SEQ4>>`[src]

`pub fn instr16(&mut self) -> INSTR16_W`[src]

Bits 0:7 - Sequence Instruction 16

`pub fn instr17(&mut self) -> INSTR17_W`[src]

Bits 8:15 - Sequence Instruction 17

`pub fn instr18(&mut self) -> INSTR18_W`[src]

Bits 16:23 - Sequence Instruction 18

`pub fn instr19(&mut self) -> INSTR19_W`[src]

Bits 24:31 - Sequence Instruction 19

`impl W<u32, Reg<u32, _DATA0>>`[src]

`pub fn data0(&mut self) -> DATA0_W`[src]

Bits 0:31 - Data 0 Access

`impl W<u32, Reg<u32, _DATA1>>`[src]

`pub fn data1(&mut self) -> DATA1_W`[src]

Bits 0:31 - Data 1 Access

`impl W<u32, Reg<u32, _DATA2>>`[src]

`pub fn data2(&mut self) -> DATA2_W`[src]

Bits 0:31 - Data 2 Access

`impl W<u32, Reg<u32, _DATA3>>`[src]

`pub fn data3(&mut self) -> DATA3_W`[src]

Bits 0:31 - Data 3 Access

`impl W<u32, Reg<u32, _DATA0XOR>>`[src]

`pub fn data0xor(&mut self) -> DATA0XOR_W`[src]

Bits 0:31 - XOR Data 0 Access

`impl W<u32, Reg<u32, _DATA0BYTE>>`[src]

`pub fn data0byte(&mut self) -> DATA0BYTE_W`[src]

Bits 0:7 - Data 0 Byte Access

`impl W<u32, Reg<u32, _DATA1BYTE>>`[src]

`pub fn data1byte(&mut self) -> DATA1BYTE_W`[src]

Bits 0:7 - Data 1 Byte Access

`impl W<u32, Reg<u32, _DATA0XORBYTE>>`[src]

`pub fn data0xorbyte(&mut self) -> DATA0XORBYTE_W`[src]

Bits 0:7 - Data 0 XOR Byte Access

`impl W<u32, Reg<u32, _DATA0BYTE12>>`[src]

`pub fn data0byte12(&mut self) -> DATA0BYTE12_W`[src]

Bits 0:7 - Data 0 Byte 12 Access

`impl W<u32, Reg<u32, _DATA0BYTE13>>`[src]

`pub fn data0byte13(&mut self) -> DATA0BYTE13_W`[src]

Bits 0:7 - Data 0 Byte 13 Access

`impl W<u32, Reg<u32, _DATA0BYTE14>>`[src]

`pub fn data0byte14(&mut self) -> DATA0BYTE14_W`[src]

Bits 0:7 - Data 0 Byte 14 Access

`impl W<u32, Reg<u32, _DATA0BYTE15>>`[src]

`pub fn data0byte15(&mut self) -> DATA0BYTE15_W`[src]

Bits 0:7 - Data 0 Byte 15 Access

`impl W<u32, Reg<u32, _DDATA0>>`[src]

`pub fn ddata0(&mut self) -> DDATA0_W`[src]

Bits 0:31 - Double Data 0 Access

`impl W<u32, Reg<u32, _DDATA1>>`[src]

`pub fn ddata1(&mut self) -> DDATA1_W`[src]

Bits 0:31 - Double Data 0 Access

`impl W<u32, Reg<u32, _DDATA2>>`[src]

`pub fn ddata2(&mut self) -> DDATA2_W`[src]

Bits 0:31 - Double Data 0 Access

`impl W<u32, Reg<u32, _DDATA3>>`[src]

`pub fn ddata3(&mut self) -> DDATA3_W`[src]

Bits 0:31 - Double Data 0 Access

`impl W<u32, Reg<u32, _DDATA4>>`[src]

`pub fn ddata4(&mut self) -> DDATA4_W`[src]

Bits 0:31 - Double Data 0 Access

`impl W<u32, Reg<u32, _DDATA0BIG>>`[src]

`pub fn ddata0big(&mut self) -> DDATA0BIG_W`[src]

Bits 0:31 - Double Data 0 Big Endian Access

`impl W<u32, Reg<u32, _DDATA0BYTE>>`[src]

`pub fn ddata0byte(&mut self) -> DDATA0BYTE_W`[src]

Bits 0:7 - Ddata 0 Byte Access

`impl W<u32, Reg<u32, _DDATA1BYTE>>`[src]

`pub fn ddata1byte(&mut self) -> DDATA1BYTE_W`[src]

Bits 0:7 - Ddata 1 Byte Access

`impl W<u32, Reg<u32, _DDATA0BYTE32>>`[src]

`pub fn ddata0byte32(&mut self) -> DDATA0BYTE32_W`[src]

Bits 0:3 - Ddata 0 Byte 32 Access

`impl W<u32, Reg<u32, _QDATA0>>`[src]

`pub fn qdata0(&mut self) -> QDATA0_W`[src]

Bits 0:31 - Quad Data 0 Access

`impl W<u32, Reg<u32, _QDATA1>>`[src]

`pub fn qdata1(&mut self) -> QDATA1_W`[src]

Bits 0:31 - Quad Data 1 Access

`impl W<u32, Reg<u32, _QDATA1BIG>>`[src]

`pub fn qdata1big(&mut self) -> QDATA1BIG_W`[src]

Bits 0:31 - Quad Data 1 Big Endian Access

`impl W<u32, Reg<u32, _QDATA0BYTE>>`[src]

`pub fn qdata0byte(&mut self) -> QDATA0BYTE_W`[src]

Bits 0:7 - Qdata 0 Byte Access

`impl W<u32, Reg<u32, _QDATA1BYTE>>`[src]

`pub fn qdata1byte(&mut self) -> QDATA1BYTE_W`[src]

Bits 0:7 - Qdata 1 Byte Access

`impl W<u32, Reg<u32, _PA_CTRL>>`[src]

`pub fn drivestrength(&mut self) -> DRIVESTRENGTH_W`[src]

Bit 0 - Drive Strength for Port

`pub fn slewrate(&mut self) -> SLEWRATE_W`[src]

Bits 4:6 - Slewrate Limit for Port

`pub fn dindis(&mut self) -> DINDIS_W`[src]

Bit 12 - Data in Disable

`pub fn drivestrengthalt(&mut self) -> DRIVESTRENGTHALT_W`[src]

Bit 16 - Alternate Drive Strength for Port

`pub fn slewratealt(&mut self) -> SLEWRATEALT_W`[src]

Bits 20:22 - Alternate Slewrate Limit for Port

`pub fn dindisalt(&mut self) -> DINDISALT_W`[src]

Bit 28 - Alternate Data in Disable

`impl W<u32, Reg<u32, _PA_MODEL>>`[src]

`pub fn mode0(&mut self) -> MODE0_W`[src]

Bits 0:3 - Pin 0 Mode

`pub fn mode1(&mut self) -> MODE1_W`[src]

Bits 4:7 - Pin 1 Mode

`pub fn mode2(&mut self) -> MODE2_W`[src]

Bits 8:11 - Pin 2 Mode

`pub fn mode3(&mut self) -> MODE3_W`[src]

Bits 12:15 - Pin 3 Mode

`pub fn mode4(&mut self) -> MODE4_W`[src]

Bits 16:19 - Pin 4 Mode

`pub fn mode5(&mut self) -> MODE5_W`[src]

Bits 20:23 - Pin 5 Mode

`pub fn mode6(&mut self) -> MODE6_W`[src]

Bits 24:27 - Pin 6 Mode

`pub fn mode7(&mut self) -> MODE7_W`[src]

Bits 28:31 - Pin 7 Mode

`impl W<u32, Reg<u32, _PA_MODEH>>`[src]

`pub fn mode8(&mut self) -> MODE8_W`[src]

Bits 0:3 - Pin 8 Mode

`pub fn mode9(&mut self) -> MODE9_W`[src]

Bits 4:7 - Pin 9 Mode

`pub fn mode10(&mut self) -> MODE10_W`[src]

Bits 8:11 - Pin 10 Mode

`pub fn mode11(&mut self) -> MODE11_W`[src]

Bits 12:15 - Pin 11 Mode

`pub fn mode12(&mut self) -> MODE12_W`[src]

Bits 16:19 - Pin 12 Mode

`pub fn mode13(&mut self) -> MODE13_W`[src]

Bits 20:23 - Pin 13 Mode

`pub fn mode14(&mut self) -> MODE14_W`[src]

Bits 24:27 - Pin 14 Mode

`pub fn mode15(&mut self) -> MODE15_W`[src]

Bits 28:31 - Pin 15 Mode

`impl W<u32, Reg<u32, _PA_DOUT>>`[src]

`pub fn dout(&mut self) -> DOUT_W`[src]

Bits 0:15 - Data Out

`impl W<u32, Reg<u32, _PA_DOUTTGL>>`[src]

`pub fn douttgl(&mut self) -> DOUTTGL_W`[src]

Bits 0:15 - Data Out Toggle

`impl W<u32, Reg<u32, _PA_PINLOCKN>>`[src]

`pub fn pinlockn(&mut self) -> PINLOCKN_W`[src]

Bits 0:15 - Unlocked Pins

`impl W<u32, Reg<u32, _PA_OVTDIS>>`[src]

`pub fn ovtdis(&mut self) -> OVTDIS_W`[src]

Bits 0:15 - Disable Over Voltage Capability

`impl W<u32, Reg<u32, _PB_CTRL>>`[src]

`pub fn drivestrength(&mut self) -> DRIVESTRENGTH_W`[src]

Bit 0 - Drive Strength for Port

`pub fn slewrate(&mut self) -> SLEWRATE_W`[src]

Bits 4:6 - Slewrate Limit for Port

`pub fn dindis(&mut self) -> DINDIS_W`[src]

Bit 12 - Data in Disable

`pub fn drivestrengthalt(&mut self) -> DRIVESTRENGTHALT_W`[src]

Bit 16 - Alternate Drive Strength for Port

`pub fn slewratealt(&mut self) -> SLEWRATEALT_W`[src]

Bits 20:22 - Alternate Slewrate Limit for Port

`pub fn dindisalt(&mut self) -> DINDISALT_W`[src]

Bit 28 - Alternate Data in Disable

`impl W<u32, Reg<u32, _PB_MODEL>>`[src]

`pub fn mode0(&mut self) -> MODE0_W`[src]

Bits 0:3 - Pin 0 Mode

`pub fn mode1(&mut self) -> MODE1_W`[src]

Bits 4:7 - Pin 1 Mode

`pub fn mode2(&mut self) -> MODE2_W`[src]

Bits 8:11 - Pin 2 Mode

`pub fn mode3(&mut self) -> MODE3_W`[src]

Bits 12:15 - Pin 3 Mode

`pub fn mode4(&mut self) -> MODE4_W`[src]

Bits 16:19 - Pin 4 Mode

`pub fn mode5(&mut self) -> MODE5_W`[src]

Bits 20:23 - Pin 5 Mode

`pub fn mode6(&mut self) -> MODE6_W`[src]

Bits 24:27 - Pin 6 Mode

`pub fn mode7(&mut self) -> MODE7_W`[src]

Bits 28:31 - Pin 7 Mode

`impl W<u32, Reg<u32, _PB_MODEH>>`[src]

`pub fn mode8(&mut self) -> MODE8_W`[src]

Bits 0:3 - Pin 8 Mode

`pub fn mode9(&mut self) -> MODE9_W`[src]

Bits 4:7 - Pin 9 Mode

`pub fn mode10(&mut self) -> MODE10_W`[src]

Bits 8:11 - Pin 10 Mode

`pub fn mode11(&mut self) -> MODE11_W`[src]

Bits 12:15 - Pin 11 Mode

`pub fn mode12(&mut self) -> MODE12_W`[src]

Bits 16:19 - Pin 12 Mode

`pub fn mode13(&mut self) -> MODE13_W`[src]

Bits 20:23 - Pin 13 Mode

`pub fn mode14(&mut self) -> MODE14_W`[src]

Bits 24:27 - Pin 14 Mode

`pub fn mode15(&mut self) -> MODE15_W`[src]

Bits 28:31 - Pin 15 Mode

`impl W<u32, Reg<u32, _PB_DOUT>>`[src]

`pub fn dout(&mut self) -> DOUT_W`[src]

Bits 0:15 - Data Out

`impl W<u32, Reg<u32, _PB_DOUTTGL>>`[src]

`pub fn douttgl(&mut self) -> DOUTTGL_W`[src]

Bits 0:15 - Data Out Toggle

`impl W<u32, Reg<u32, _PB_PINLOCKN>>`[src]

`pub fn pinlockn(&mut self) -> PINLOCKN_W`[src]

Bits 0:15 - Unlocked Pins

`impl W<u32, Reg<u32, _PB_OVTDIS>>`[src]

`pub fn ovtdis(&mut self) -> OVTDIS_W`[src]

Bits 0:15 - Disable Over Voltage Capability

`impl W<u32, Reg<u32, _PC_CTRL>>`[src]

`pub fn drivestrength(&mut self) -> DRIVESTRENGTH_W`[src]

Bit 0 - Drive Strength for Port

`pub fn slewrate(&mut self) -> SLEWRATE_W`[src]

Bits 4:6 - Slewrate Limit for Port

`pub fn dindis(&mut self) -> DINDIS_W`[src]

Bit 12 - Data in Disable

`pub fn drivestrengthalt(&mut self) -> DRIVESTRENGTHALT_W`[src]

Bit 16 - Alternate Drive Strength for Port

`pub fn slewratealt(&mut self) -> SLEWRATEALT_W`[src]

Bits 20:22 - Alternate Slewrate Limit for Port

`pub fn dindisalt(&mut self) -> DINDISALT_W`[src]

Bit 28 - Alternate Data in Disable

`impl W<u32, Reg<u32, _PC_MODEL>>`[src]

`pub fn mode0(&mut self) -> MODE0_W`[src]

Bits 0:3 - Pin 0 Mode

`pub fn mode1(&mut self) -> MODE1_W`[src]

Bits 4:7 - Pin 1 Mode

`pub fn mode2(&mut self) -> MODE2_W`[src]

Bits 8:11 - Pin 2 Mode

`pub fn mode3(&mut self) -> MODE3_W`[src]

Bits 12:15 - Pin 3 Mode

`pub fn mode4(&mut self) -> MODE4_W`[src]

Bits 16:19 - Pin 4 Mode

`pub fn mode5(&mut self) -> MODE5_W`[src]

Bits 20:23 - Pin 5 Mode

`pub fn mode6(&mut self) -> MODE6_W`[src]

Bits 24:27 - Pin 6 Mode

`pub fn mode7(&mut self) -> MODE7_W`[src]

Bits 28:31 - Pin 7 Mode

`impl W<u32, Reg<u32, _PC_MODEH>>`[src]

`pub fn mode8(&mut self) -> MODE8_W`[src]

Bits 0:3 - Pin 8 Mode

`pub fn mode9(&mut self) -> MODE9_W`[src]

Bits 4:7 - Pin 9 Mode

`pub fn mode10(&mut self) -> MODE10_W`[src]

Bits 8:11 - Pin 10 Mode

`pub fn mode11(&mut self) -> MODE11_W`[src]

Bits 12:15 - Pin 11 Mode

`pub fn mode12(&mut self) -> MODE12_W`[src]

Bits 16:19 - Pin 12 Mode

`pub fn mode13(&mut self) -> MODE13_W`[src]

Bits 20:23 - Pin 13 Mode

`pub fn mode14(&mut self) -> MODE14_W`[src]

Bits 24:27 - Pin 14 Mode

`pub fn mode15(&mut self) -> MODE15_W`[src]

Bits 28:31 - Pin 15 Mode

`impl W<u32, Reg<u32, _PC_DOUT>>`[src]

`pub fn dout(&mut self) -> DOUT_W`[src]

Bits 0:15 - Data Out

`impl W<u32, Reg<u32, _PC_DOUTTGL>>`[src]

`pub fn douttgl(&mut self) -> DOUTTGL_W`[src]

Bits 0:15 - Data Out Toggle

`impl W<u32, Reg<u32, _PC_PINLOCKN>>`[src]

`pub fn pinlockn(&mut self) -> PINLOCKN_W`[src]

Bits 0:15 - Unlocked Pins

`impl W<u32, Reg<u32, _PC_OVTDIS>>`[src]

`pub fn ovtdis(&mut self) -> OVTDIS_W`[src]

Bits 0:15 - Disable Over Voltage Capability

`impl W<u32, Reg<u32, _PD_CTRL>>`[src]

`pub fn drivestrength(&mut self) -> DRIVESTRENGTH_W`[src]

Bit 0 - Drive Strength for Port

`pub fn slewrate(&mut self) -> SLEWRATE_W`[src]

Bits 4:6 - Slewrate Limit for Port

`pub fn dindis(&mut self) -> DINDIS_W`[src]

Bit 12 - Data in Disable

`pub fn drivestrengthalt(&mut self) -> DRIVESTRENGTHALT_W`[src]

Bit 16 - Alternate Drive Strength for Port

`pub fn slewratealt(&mut self) -> SLEWRATEALT_W`[src]

Bits 20:22 - Alternate Slewrate Limit for Port

`pub fn dindisalt(&mut self) -> DINDISALT_W`[src]

Bit 28 - Alternate Data in Disable

`impl W<u32, Reg<u32, _PD_MODEL>>`[src]

`pub fn mode0(&mut self) -> MODE0_W`[src]

Bits 0:3 - Pin 0 Mode

`pub fn mode1(&mut self) -> MODE1_W`[src]

Bits 4:7 - Pin 1 Mode

`pub fn mode2(&mut self) -> MODE2_W`[src]

Bits 8:11 - Pin 2 Mode

`pub fn mode3(&mut self) -> MODE3_W`[src]

Bits 12:15 - Pin 3 Mode

`pub fn mode4(&mut self) -> MODE4_W`[src]

Bits 16:19 - Pin 4 Mode

`pub fn mode5(&mut self) -> MODE5_W`[src]

Bits 20:23 - Pin 5 Mode

`pub fn mode6(&mut self) -> MODE6_W`[src]

Bits 24:27 - Pin 6 Mode

`pub fn mode7(&mut self) -> MODE7_W`[src]

Bits 28:31 - Pin 7 Mode

`impl W<u32, Reg<u32, _PD_MODEH>>`[src]

`pub fn mode8(&mut self) -> MODE8_W`[src]

Bits 0:3 - Pin 8 Mode

`pub fn mode9(&mut self) -> MODE9_W`[src]

Bits 4:7 - Pin 9 Mode

`pub fn mode10(&mut self) -> MODE10_W`[src]

Bits 8:11 - Pin 10 Mode

`pub fn mode11(&mut self) -> MODE11_W`[src]

Bits 12:15 - Pin 11 Mode

`pub fn mode12(&mut self) -> MODE12_W`[src]

Bits 16:19 - Pin 12 Mode

`pub fn mode13(&mut self) -> MODE13_W`[src]

Bits 20:23 - Pin 13 Mode

`pub fn mode14(&mut self) -> MODE14_W`[src]

Bits 24:27 - Pin 14 Mode

`pub fn mode15(&mut self) -> MODE15_W`[src]

Bits 28:31 - Pin 15 Mode

`impl W<u32, Reg<u32, _PD_DOUT>>`[src]

`pub fn dout(&mut self) -> DOUT_W`[src]

Bits 0:15 - Data Out

`impl W<u32, Reg<u32, _PD_DOUTTGL>>`[src]

`pub fn douttgl(&mut self) -> DOUTTGL_W`[src]

Bits 0:15 - Data Out Toggle

`impl W<u32, Reg<u32, _PD_PINLOCKN>>`[src]

`pub fn pinlockn(&mut self) -> PINLOCKN_W`[src]

Bits 0:15 - Unlocked Pins

`impl W<u32, Reg<u32, _PD_OVTDIS>>`[src]

`pub fn ovtdis(&mut self) -> OVTDIS_W`[src]

Bits 0:15 - Disable Over Voltage Capability

`impl W<u32, Reg<u32, _PE_CTRL>>`[src]

`pub fn drivestrength(&mut self) -> DRIVESTRENGTH_W`[src]

Bit 0 - Drive Strength for Port

`pub fn slewrate(&mut self) -> SLEWRATE_W`[src]

Bits 4:6 - Slewrate Limit for Port

`pub fn dindis(&mut self) -> DINDIS_W`[src]

Bit 12 - Data in Disable

`pub fn drivestrengthalt(&mut self) -> DRIVESTRENGTHALT_W`[src]

Bit 16 - Alternate Drive Strength for Port

`pub fn slewratealt(&mut self) -> SLEWRATEALT_W`[src]

Bits 20:22 - Alternate Slewrate Limit for Port

`pub fn dindisalt(&mut self) -> DINDISALT_W`[src]

Bit 28 - Alternate Data in Disable

`impl W<u32, Reg<u32, _PE_MODEL>>`[src]

`pub fn mode0(&mut self) -> MODE0_W`[src]

Bits 0:3 - Pin 0 Mode

`pub fn mode1(&mut self) -> MODE1_W`[src]

Bits 4:7 - Pin 1 Mode

`pub fn mode2(&mut self) -> MODE2_W`[src]

Bits 8:11 - Pin 2 Mode

`pub fn mode3(&mut self) -> MODE3_W`[src]

Bits 12:15 - Pin 3 Mode

`pub fn mode4(&mut self) -> MODE4_W`[src]

Bits 16:19 - Pin 4 Mode

`pub fn mode5(&mut self) -> MODE5_W`[src]

Bits 20:23 - Pin 5 Mode

`pub fn mode6(&mut self) -> MODE6_W`[src]

Bits 24:27 - Pin 6 Mode

`pub fn mode7(&mut self) -> MODE7_W`[src]

Bits 28:31 - Pin 7 Mode

`impl W<u32, Reg<u32, _PE_MODEH>>`[src]

`pub fn mode8(&mut self) -> MODE8_W`[src]

Bits 0:3 - Pin 8 Mode

`pub fn mode9(&mut self) -> MODE9_W`[src]

Bits 4:7 - Pin 9 Mode

`pub fn mode10(&mut self) -> MODE10_W`[src]

Bits 8:11 - Pin 10 Mode

`pub fn mode11(&mut self) -> MODE11_W`[src]

Bits 12:15 - Pin 11 Mode

`pub fn mode12(&mut self) -> MODE12_W`[src]

Bits 16:19 - Pin 12 Mode

`pub fn mode13(&mut self) -> MODE13_W`[src]

Bits 20:23 - Pin 13 Mode

`pub fn mode14(&mut self) -> MODE14_W`[src]

Bits 24:27 - Pin 14 Mode

`pub fn mode15(&mut self) -> MODE15_W`[src]

Bits 28:31 - Pin 15 Mode

`impl W<u32, Reg<u32, _PE_DOUT>>`[src]

`pub fn dout(&mut self) -> DOUT_W`[src]

Bits 0:15 - Data Out

`impl W<u32, Reg<u32, _PE_DOUTTGL>>`[src]

`pub fn douttgl(&mut self) -> DOUTTGL_W`[src]

Bits 0:15 - Data Out Toggle

`impl W<u32, Reg<u32, _PE_PINLOCKN>>`[src]

`pub fn pinlockn(&mut self) -> PINLOCKN_W`[src]

Bits 0:15 - Unlocked Pins

`impl W<u32, Reg<u32, _PE_OVTDIS>>`[src]

`pub fn ovtdis(&mut self) -> OVTDIS_W`[src]

Bits 0:15 - Disable Over Voltage Capability

`impl W<u32, Reg<u32, _PF_CTRL>>`[src]

`pub fn drivestrength(&mut self) -> DRIVESTRENGTH_W`[src]

Bit 0 - Drive Strength for Port

`pub fn slewrate(&mut self) -> SLEWRATE_W`[src]

Bits 4:6 - Slewrate Limit for Port

`pub fn dindis(&mut self) -> DINDIS_W`[src]

Bit 12 - Data in Disable

`pub fn drivestrengthalt(&mut self) -> DRIVESTRENGTHALT_W`[src]

Bit 16 - Alternate Drive Strength for Port

`pub fn slewratealt(&mut self) -> SLEWRATEALT_W`[src]

Bits 20:22 - Alternate Slewrate Limit for Port

`pub fn dindisalt(&mut self) -> DINDISALT_W`[src]

Bit 28 - Alternate Data in Disable

`impl W<u32, Reg<u32, _PF_MODEL>>`[src]

`pub fn mode0(&mut self) -> MODE0_W`[src]

Bits 0:3 - Pin 0 Mode

`pub fn mode1(&mut self) -> MODE1_W`[src]

Bits 4:7 - Pin 1 Mode

`pub fn mode2(&mut self) -> MODE2_W`[src]

Bits 8:11 - Pin 2 Mode

`pub fn mode3(&mut self) -> MODE3_W`[src]

Bits 12:15 - Pin 3 Mode

`pub fn mode4(&mut self) -> MODE4_W`[src]

Bits 16:19 - Pin 4 Mode

`pub fn mode5(&mut self) -> MODE5_W`[src]

Bits 20:23 - Pin 5 Mode

`pub fn mode6(&mut self) -> MODE6_W`[src]

Bits 24:27 - Pin 6 Mode

`pub fn mode7(&mut self) -> MODE7_W`[src]

Bits 28:31 - Pin 7 Mode

`impl W<u32, Reg<u32, _PF_MODEH>>`[src]

`pub fn mode8(&mut self) -> MODE8_W`[src]

Bits 0:3 - Pin 8 Mode

`pub fn mode9(&mut self) -> MODE9_W`[src]

Bits 4:7 - Pin 9 Mode

`pub fn mode10(&mut self) -> MODE10_W`[src]

Bits 8:11 - Pin 10 Mode

`pub fn mode11(&mut self) -> MODE11_W`[src]

Bits 12:15 - Pin 11 Mode

`pub fn mode12(&mut self) -> MODE12_W`[src]

Bits 16:19 - Pin 12 Mode

`pub fn mode13(&mut self) -> MODE13_W`[src]

Bits 20:23 - Pin 13 Mode

`pub fn mode14(&mut self) -> MODE14_W`[src]

Bits 24:27 - Pin 14 Mode

`pub fn mode15(&mut self) -> MODE15_W`[src]

Bits 28:31 - Pin 15 Mode

`impl W<u32, Reg<u32, _PF_DOUT>>`[src]

`pub fn dout(&mut self) -> DOUT_W`[src]

Bits 0:15 - Data Out

`impl W<u32, Reg<u32, _PF_DOUTTGL>>`[src]

`pub fn douttgl(&mut self) -> DOUTTGL_W`[src]

Bits 0:15 - Data Out Toggle

`impl W<u32, Reg<u32, _PF_PINLOCKN>>`[src]

`pub fn pinlockn(&mut self) -> PINLOCKN_W`[src]

Bits 0:15 - Unlocked Pins

`impl W<u32, Reg<u32, _PF_OVTDIS>>`[src]

`pub fn ovtdis(&mut self) -> OVTDIS_W`[src]

Bits 0:15 - Disable Over Voltage Capability

`impl W<u32, Reg<u32, _EXTIPSELL>>`[src]

`pub fn extipsel0(&mut self) -> EXTIPSEL0_W`[src]

Bits 0:3 - External Interrupt 0 Port Select

`pub fn extipsel1(&mut self) -> EXTIPSEL1_W`[src]

Bits 4:7 - External Interrupt 1 Port Select

`pub fn extipsel2(&mut self) -> EXTIPSEL2_W`[src]

Bits 8:11 - External Interrupt 2 Port Select

`pub fn extipsel3(&mut self) -> EXTIPSEL3_W`[src]

Bits 12:15 - External Interrupt 3 Port Select

`pub fn extipsel4(&mut self) -> EXTIPSEL4_W`[src]

Bits 16:19 - External Interrupt 4 Port Select

`pub fn extipsel5(&mut self) -> EXTIPSEL5_W`[src]

Bits 20:23 - External Interrupt 5 Port Select

`pub fn extipsel6(&mut self) -> EXTIPSEL6_W`[src]

Bits 24:27 - External Interrupt 6 Port Select

`pub fn extipsel7(&mut self) -> EXTIPSEL7_W`[src]

Bits 28:31 - External Interrupt 7 Port Select

`impl W<u32, Reg<u32, _EXTIPSELH>>`[src]

`pub fn extipsel8(&mut self) -> EXTIPSEL8_W`[src]

Bits 0:3 - External Interrupt 8 Port Select

`pub fn extipsel9(&mut self) -> EXTIPSEL9_W`[src]

Bits 4:7 - External Interrupt 9 Port Select

`pub fn extipsel10(&mut self) -> EXTIPSEL10_W`[src]

Bits 8:11 - External Interrupt 10 Port Select

`pub fn extipsel11(&mut self) -> EXTIPSEL11_W`[src]

Bits 12:15 - External Interrupt 11 Port Select

`pub fn extipsel12(&mut self) -> EXTIPSEL12_W`[src]

Bits 16:19 - External Interrupt 12 Port Select

`pub fn extipsel13(&mut self) -> EXTIPSEL13_W`[src]

Bits 20:23 - External Interrupt 13 Port Select

`pub fn extipsel14(&mut self) -> EXTIPSEL14_W`[src]

Bits 24:27 - External Interrupt 14 Port Select

`pub fn extipsel15(&mut self) -> EXTIPSEL15_W`[src]

Bits 28:31 - External Interrupt 15 Port Select

`impl W<u32, Reg<u32, _EXTIPINSELL>>`[src]

`pub fn extipinsel0(&mut self) -> EXTIPINSEL0_W`[src]

Bits 0:1 - External Interrupt 0 Pin Select

`pub fn extipinsel1(&mut self) -> EXTIPINSEL1_W`[src]

Bits 4:5 - External Interrupt 1 Pin Select

`pub fn extipinsel2(&mut self) -> EXTIPINSEL2_W`[src]

Bits 8:9 - External Interrupt 2 Pin Select

`pub fn extipinsel3(&mut self) -> EXTIPINSEL3_W`[src]

Bits 12:13 - External Interrupt 3 Pin Select

`pub fn extipinsel4(&mut self) -> EXTIPINSEL4_W`[src]

Bits 16:17 - External Interrupt 4 Pin Select

`pub fn extipinsel5(&mut self) -> EXTIPINSEL5_W`[src]

Bits 20:21 - External Interrupt 5 Pin Select

`pub fn extipinsel6(&mut self) -> EXTIPINSEL6_W`[src]

Bits 24:25 - External Interrupt 6 Pin Select

`pub fn extipinsel7(&mut self) -> EXTIPINSEL7_W`[src]

Bits 28:29 - External Interrupt 7 Pin Select

`impl W<u32, Reg<u32, _EXTIPINSELH>>`[src]

`pub fn extipinsel8(&mut self) -> EXTIPINSEL8_W`[src]

Bits 0:1 - External Interrupt 8 Pin Select

`pub fn extipinsel9(&mut self) -> EXTIPINSEL9_W`[src]

Bits 4:5 - External Interrupt 9 Pin Select

`pub fn extipinsel10(&mut self) -> EXTIPINSEL10_W`[src]

Bits 8:9 - External Interrupt 10 Pin Select

`pub fn extipinsel11(&mut self) -> EXTIPINSEL11_W`[src]

Bits 12:13 - External Interrupt 11 Pin Select

`pub fn extipinsel12(&mut self) -> EXTIPINSEL12_W`[src]

Bits 16:17 - External Interrupt 12 Pin Select

`pub fn extipinsel13(&mut self) -> EXTIPINSEL13_W`[src]

Bits 20:21 - External Interrupt 13 Pin Select

`pub fn extipinsel14(&mut self) -> EXTIPINSEL14_W`[src]

Bits 24:25 - External Interrupt 14 Pin Select

`pub fn extipinsel15(&mut self) -> EXTIPINSEL15_W`[src]

Bits 28:29 - External Interrupt 15 Pin Select

`impl W<u32, Reg<u32, _EXTIRISE>>`[src]

`pub fn extirise(&mut self) -> EXTIRISE_W`[src]

Bits 0:15 - External Interrupt N Rising Edge Trigger Enable

`impl W<u32, Reg<u32, _EXTIFALL>>`[src]

`pub fn extifall(&mut self) -> EXTIFALL_W`[src]

Bits 0:15 - External Interrupt N Falling Edge Trigger Enable

`impl W<u32, Reg<u32, _EXTILEVEL>>`[src]

`pub fn em4wu0(&mut self) -> EM4WU0_W`[src]

Bit 16 - EM4 Wake Up Level for EM4WU0 Pin

`pub fn em4wu1(&mut self) -> EM4WU1_W`[src]

Bit 17 - EM4 Wake Up Level for EM4WU1 Pin

`pub fn em4wu4(&mut self) -> EM4WU4_W`[src]

Bit 20 - EM4 Wake Up Level for EM4WU4 Pin

`pub fn em4wu8(&mut self) -> EM4WU8_W`[src]

Bit 24 - EM4 Wake Up Level for EM4WU8 Pin

`pub fn em4wu9(&mut self) -> EM4WU9_W`[src]

Bit 25 - EM4 Wake Up Level for EM4WU9 Pin

`pub fn em4wu12(&mut self) -> EM4WU12_W`[src]

Bit 28 - EM4 Wake Up Level for EM4WU12 Pin

`impl W<u32, Reg<u32, _IFS>>`[src]

`pub fn ext(&mut self) -> EXT_W`[src]

Bits 0:15 - Set EXT Interrupt Flag

`pub fn em4wu(&mut self) -> EM4WU_W`[src]

Bits 16:31 - Set EM4WU Interrupt Flag

`impl W<u32, Reg<u32, _IFC>>`[src]

`pub fn ext(&mut self) -> EXT_W`[src]

Bits 0:15 - Clear EXT Interrupt Flag

`pub fn em4wu(&mut self) -> EM4WU_W`[src]

Bits 16:31 - Clear EM4WU Interrupt Flag

`impl W<u32, Reg<u32, _IEN>>`[src]

`pub fn ext(&mut self) -> EXT_W`[src]

Bits 0:15 - EXT Interrupt Enable

`pub fn em4wu(&mut self) -> EM4WU_W`[src]

Bits 16:31 - EM4WU Interrupt Enable

`impl W<u32, Reg<u32, _EM4WUEN>>`[src]

`pub fn em4wuen(&mut self) -> EM4WUEN_W`[src]

Bits 16:31 - EM4 Wake Up Enable

`impl W<u32, Reg<u32, _ROUTEPEN>>`[src]

`pub fn swclktckpen(&mut self) -> SWCLKTCKPEN_W`[src]

Bit 0 - Serial Wire Clock and JTAG Test Clock Pin Enable

`pub fn swdiotmspen(&mut self) -> SWDIOTMSPEN_W`[src]

Bit 1 - Serial Wire Data and JTAG Test Mode Select Pin Enable

`pub fn tdopen(&mut self) -> TDOPEN_W`[src]

Bit 2 - JTAG Test Debug Output Pin Enable

`pub fn tdipen(&mut self) -> TDIPEN_W`[src]

Bit 3 - JTAG Test Debug Input Pin Enable

`pub fn swvpen(&mut self) -> SWVPEN_W`[src]

Bit 4 - Serial Wire Viewer Output Pin Enable

`impl W<u32, Reg<u32, _ROUTELOC0>>`[src]

`pub fn swvloc(&mut self) -> SWVLOC_W`[src]

Bits 0:5 - I/O Location

`impl W<u32, Reg<u32, _INSENSE>>`[src]

`pub fn int(&mut self) -> INT_W`[src]

Bit 0 - Interrupt Sense Enable

`pub fn em4wu(&mut self) -> EM4WU_W`[src]

Bit 1 - EM4WU Interrupt Sense Enable

`impl W<u32, Reg<u32, _LOCK>>`[src]

`pub fn lockkey(&mut self) -> LOCKKEY_W`[src]

Bits 0:15 - Configuration Lock Key

`impl W<u32, Reg<u32, _SWPULSE>>`[src]

`pub fn ch0pulse(&mut self) -> CH0PULSE_W`[src]

Bit 0 - Channel 0 Pulse Generation

`pub fn ch1pulse(&mut self) -> CH1PULSE_W`[src]

Bit 1 - Channel 1 Pulse Generation

`pub fn ch2pulse(&mut self) -> CH2PULSE_W`[src]

Bit 2 - Channel 2 Pulse Generation

`pub fn ch3pulse(&mut self) -> CH3PULSE_W`[src]

Bit 3 - Channel 3 Pulse Generation

`pub fn ch4pulse(&mut self) -> CH4PULSE_W`[src]

Bit 4 - Channel 4 Pulse Generation

`pub fn ch5pulse(&mut self) -> CH5PULSE_W`[src]

Bit 5 - Channel 5 Pulse Generation

`pub fn ch6pulse(&mut self) -> CH6PULSE_W`[src]

Bit 6 - Channel 6 Pulse Generation

`pub fn ch7pulse(&mut self) -> CH7PULSE_W`[src]

Bit 7 - Channel 7 Pulse Generation

`pub fn ch8pulse(&mut self) -> CH8PULSE_W`[src]

Bit 8 - Channel 8 Pulse Generation

`pub fn ch9pulse(&mut self) -> CH9PULSE_W`[src]

Bit 9 - Channel 9 Pulse Generation

`pub fn ch10pulse(&mut self) -> CH10PULSE_W`[src]

Bit 10 - Channel 10 Pulse Generation

`pub fn ch11pulse(&mut self) -> CH11PULSE_W`[src]

Bit 11 - Channel 11 Pulse Generation

`impl W<u32, Reg<u32, _SWLEVEL>>`[src]

`pub fn ch0level(&mut self) -> CH0LEVEL_W`[src]

Bit 0 - Channel 0 Software Level

`pub fn ch1level(&mut self) -> CH1LEVEL_W`[src]

Bit 1 - Channel 1 Software Level

`pub fn ch2level(&mut self) -> CH2LEVEL_W`[src]

Bit 2 - Channel 2 Software Level

`pub fn ch3level(&mut self) -> CH3LEVEL_W`[src]

Bit 3 - Channel 3 Software Level

`pub fn ch4level(&mut self) -> CH4LEVEL_W`[src]

Bit 4 - Channel 4 Software Level

`pub fn ch5level(&mut self) -> CH5LEVEL_W`[src]

Bit 5 - Channel 5 Software Level

`pub fn ch6level(&mut self) -> CH6LEVEL_W`[src]

Bit 6 - Channel 6 Software Level

`pub fn ch7level(&mut self) -> CH7LEVEL_W`[src]

Bit 7 - Channel 7 Software Level

`pub fn ch8level(&mut self) -> CH8LEVEL_W`[src]

Bit 8 - Channel 8 Software Level

`pub fn ch9level(&mut self) -> CH9LEVEL_W`[src]

Bit 9 - Channel 9 Software Level

`pub fn ch10level(&mut self) -> CH10LEVEL_W`[src]

Bit 10 - Channel 10 Software Level

`pub fn ch11level(&mut self) -> CH11LEVEL_W`[src]

Bit 11 - Channel 11 Software Level

`impl W<u32, Reg<u32, _ROUTEPEN>>`[src]

`pub fn ch0pen(&mut self) -> CH0PEN_W`[src]

Bit 0 - CH0 Pin Enable

`pub fn ch1pen(&mut self) -> CH1PEN_W`[src]

Bit 1 - CH1 Pin Enable

`pub fn ch2pen(&mut self) -> CH2PEN_W`[src]

Bit 2 - CH2 Pin Enable

`pub fn ch3pen(&mut self) -> CH3PEN_W`[src]

Bit 3 - CH3 Pin Enable

`pub fn ch4pen(&mut self) -> CH4PEN_W`[src]

Bit 4 - CH4 Pin Enable

`pub fn ch5pen(&mut self) -> CH5PEN_W`[src]

Bit 5 - CH5 Pin Enable

`pub fn ch6pen(&mut self) -> CH6PEN_W`[src]

Bit 6 - CH6 Pin Enable

`pub fn ch7pen(&mut self) -> CH7PEN_W`[src]

Bit 7 - CH7 Pin Enable

`pub fn ch8pen(&mut self) -> CH8PEN_W`[src]

Bit 8 - CH8 Pin Enable

`pub fn ch9pen(&mut self) -> CH9PEN_W`[src]

Bit 9 - CH9 Pin Enable

`pub fn ch10pen(&mut self) -> CH10PEN_W`[src]

Bit 10 - CH10 Pin Enable

`pub fn ch11pen(&mut self) -> CH11PEN_W`[src]

Bit 11 - CH11 Pin Enable

`impl W<u32, Reg<u32, _ROUTELOC0>>`[src]

`pub fn ch0loc(&mut self) -> CH0LOC_W`[src]

Bits 0:5 - I/O Location

`pub fn ch1loc(&mut self) -> CH1LOC_W`[src]

Bits 8:13 - I/O Location

`pub fn ch2loc(&mut self) -> CH2LOC_W`[src]

Bits 16:21 - I/O Location

`pub fn ch3loc(&mut self) -> CH3LOC_W`[src]

Bits 24:29 - I/O Location

`impl W<u32, Reg<u32, _ROUTELOC1>>`[src]

`pub fn ch4loc(&mut self) -> CH4LOC_W`[src]

Bits 0:5 - I/O Location

`pub fn ch5loc(&mut self) -> CH5LOC_W`[src]

Bits 8:13 - I/O Location

`pub fn ch6loc(&mut self) -> CH6LOC_W`[src]

Bits 16:21 - I/O Location

`pub fn ch7loc(&mut self) -> CH7LOC_W`[src]

Bits 24:29 - I/O Location

`impl W<u32, Reg<u32, _ROUTELOC2>>`[src]

`pub fn ch8loc(&mut self) -> CH8LOC_W`[src]

Bits 0:5 - I/O Location

`pub fn ch9loc(&mut self) -> CH9LOC_W`[src]

Bits 8:13 - I/O Location

`pub fn ch10loc(&mut self) -> CH10LOC_W`[src]

Bits 16:21 - I/O Location

`pub fn ch11loc(&mut self) -> CH11LOC_W`[src]

Bits 24:29 - I/O Location

`impl W<u32, Reg<u32, _CTRL>>`[src]

`pub fn sevonprs(&mut self) -> SEVONPRS_W`[src]

Bit 0 - Set Event on PRS

`pub fn sevonprssel(&mut self) -> SEVONPRSSEL_W`[src]

Bits 1:4 - SEVONPRS PRS Channel Select

`impl W<u32, Reg<u32, _DMAREQ0>>`[src]

`pub fn prssel(&mut self) -> PRSSEL_W`[src]

Bits 6:9 - DMA Request 0 PRS Channel Select

`impl W<u32, Reg<u32, _DMAREQ1>>`[src]

`pub fn prssel(&mut self) -> PRSSEL_W`[src]

Bits 6:9 - DMA Request 1 PRS Channel Select

`impl W<u32, Reg<u32, _CH0_CTRL>>`[src]

`pub fn sigsel(&mut self) -> SIGSEL_W`[src]

Bits 0:2 - Signal Select

`pub fn sourcesel(&mut self) -> SOURCESEL_W`[src]

Bits 8:14 - Source Select

`pub fn edsel(&mut self) -> EDSEL_W`[src]

Bits 20:21 - Edge Detect Select

`pub fn stretch(&mut self) -> STRETCH_W`[src]

Bit 25 - Stretch Channel Output

`pub fn inv(&mut self) -> INV_W`[src]

Bit 26 - Invert Channel

`pub fn orprev(&mut self) -> ORPREV_W`[src]

Bit 27 - Or Previous

`pub fn andnext(&mut self) -> ANDNEXT_W`[src]

Bit 28 - And Next

`pub fn asyncrefl(&mut self) -> ASYNCREFL_W`[src]

Bit 30 - Asynchronous Reflex

`impl W<u32, Reg<u32, _CH1_CTRL>>`[src]

`pub fn sigsel(&mut self) -> SIGSEL_W`[src]

Bits 0:2 - Signal Select

`pub fn sourcesel(&mut self) -> SOURCESEL_W`[src]

Bits 8:14 - Source Select

`pub fn edsel(&mut self) -> EDSEL_W`[src]

Bits 20:21 - Edge Detect Select

`pub fn stretch(&mut self) -> STRETCH_W`[src]

Bit 25 - Stretch Channel Output

`pub fn inv(&mut self) -> INV_W`[src]

Bit 26 - Invert Channel

`pub fn orprev(&mut self) -> ORPREV_W`[src]

Bit 27 - Or Previous

`pub fn andnext(&mut self) -> ANDNEXT_W`[src]

Bit 28 - And Next

`pub fn asyncrefl(&mut self) -> ASYNCREFL_W`[src]

Bit 30 - Asynchronous Reflex

`impl W<u32, Reg<u32, _CH2_CTRL>>`[src]

`pub fn sigsel(&mut self) -> SIGSEL_W`[src]

Bits 0:2 - Signal Select

`pub fn sourcesel(&mut self) -> SOURCESEL_W`[src]

Bits 8:14 - Source Select

`pub fn edsel(&mut self) -> EDSEL_W`[src]

Bits 20:21 - Edge Detect Select

`pub fn stretch(&mut self) -> STRETCH_W`[src]

Bit 25 - Stretch Channel Output

`pub fn inv(&mut self) -> INV_W`[src]

Bit 26 - Invert Channel

`pub fn orprev(&mut self) -> ORPREV_W`[src]

Bit 27 - Or Previous

`pub fn andnext(&mut self) -> ANDNEXT_W`[src]

Bit 28 - And Next

`pub fn asyncrefl(&mut self) -> ASYNCREFL_W`[src]

Bit 30 - Asynchronous Reflex

`impl W<u32, Reg<u32, _CH3_CTRL>>`[src]

`pub fn sigsel(&mut self) -> SIGSEL_W`[src]

Bits 0:2 - Signal Select

`pub fn sourcesel(&mut self) -> SOURCESEL_W`[src]

Bits 8:14 - Source Select

`pub fn edsel(&mut self) -> EDSEL_W`[src]

Bits 20:21 - Edge Detect Select

`pub fn stretch(&mut self) -> STRETCH_W`[src]

Bit 25 - Stretch Channel Output

`pub fn inv(&mut self) -> INV_W`[src]

Bit 26 - Invert Channel

`pub fn orprev(&mut self) -> ORPREV_W`[src]

Bit 27 - Or Previous

`pub fn andnext(&mut self) -> ANDNEXT_W`[src]

Bit 28 - And Next

`pub fn asyncrefl(&mut self) -> ASYNCREFL_W`[src]

Bit 30 - Asynchronous Reflex

`impl W<u32, Reg<u32, _CH4_CTRL>>`[src]

`pub fn sigsel(&mut self) -> SIGSEL_W`[src]

Bits 0:2 - Signal Select

`pub fn sourcesel(&mut self) -> SOURCESEL_W`[src]

Bits 8:14 - Source Select

`pub fn edsel(&mut self) -> EDSEL_W`[src]

Bits 20:21 - Edge Detect Select

`pub fn stretch(&mut self) -> STRETCH_W`[src]

Bit 25 - Stretch Channel Output

`pub fn inv(&mut self) -> INV_W`[src]

Bit 26 - Invert Channel

`pub fn orprev(&mut self) -> ORPREV_W`[src]

Bit 27 - Or Previous

`pub fn andnext(&mut self) -> ANDNEXT_W`[src]

Bit 28 - And Next

`pub fn asyncrefl(&mut self) -> ASYNCREFL_W`[src]

Bit 30 - Asynchronous Reflex

`impl W<u32, Reg<u32, _CH5_CTRL>>`[src]

`pub fn sigsel(&mut self) -> SIGSEL_W`[src]

Bits 0:2 - Signal Select

`pub fn sourcesel(&mut self) -> SOURCESEL_W`[src]

Bits 8:14 - Source Select

`pub fn edsel(&mut self) -> EDSEL_W`[src]

Bits 20:21 - Edge Detect Select

`pub fn stretch(&mut self) -> STRETCH_W`[src]

Bit 25 - Stretch Channel Output

`pub fn inv(&mut self) -> INV_W`[src]

Bit 26 - Invert Channel

`pub fn orprev(&mut self) -> ORPREV_W`[src]

Bit 27 - Or Previous

`pub fn andnext(&mut self) -> ANDNEXT_W`[src]

Bit 28 - And Next

`pub fn asyncrefl(&mut self) -> ASYNCREFL_W`[src]

Bit 30 - Asynchronous Reflex

`impl W<u32, Reg<u32, _CH6_CTRL>>`[src]

`pub fn sigsel(&mut self) -> SIGSEL_W`[src]

Bits 0:2 - Signal Select

`pub fn sourcesel(&mut self) -> SOURCESEL_W`[src]

Bits 8:14 - Source Select

`pub fn edsel(&mut self) -> EDSEL_W`[src]

Bits 20:21 - Edge Detect Select

`pub fn stretch(&mut self) -> STRETCH_W`[src]

Bit 25 - Stretch Channel Output

`pub fn inv(&mut self) -> INV_W`[src]

Bit 26 - Invert Channel

`pub fn orprev(&mut self) -> ORPREV_W`[src]

Bit 27 - Or Previous

`pub fn andnext(&mut self) -> ANDNEXT_W`[src]

Bit 28 - And Next

`pub fn asyncrefl(&mut self) -> ASYNCREFL_W`[src]

Bit 30 - Asynchronous Reflex

`impl W<u32, Reg<u32, _CH7_CTRL>>`[src]

`pub fn sigsel(&mut self) -> SIGSEL_W`[src]

Bits 0:2 - Signal Select

`pub fn sourcesel(&mut self) -> SOURCESEL_W`[src]

Bits 8:14 - Source Select

`pub fn edsel(&mut self) -> EDSEL_W`[src]

Bits 20:21 - Edge Detect Select

`pub fn stretch(&mut self) -> STRETCH_W`[src]

Bit 25 - Stretch Channel Output

`pub fn inv(&mut self) -> INV_W`[src]

Bit 26 - Invert Channel

`pub fn orprev(&mut self) -> ORPREV_W`[src]

Bit 27 - Or Previous

`pub fn andnext(&mut self) -> ANDNEXT_W`[src]

Bit 28 - And Next

`pub fn asyncrefl(&mut self) -> ASYNCREFL_W`[src]

Bit 30 - Asynchronous Reflex

`impl W<u32, Reg<u32, _CH8_CTRL>>`[src]

`pub fn sigsel(&mut self) -> SIGSEL_W`[src]

Bits 0:2 - Signal Select

`pub fn sourcesel(&mut self) -> SOURCESEL_W`[src]

Bits 8:14 - Source Select

`pub fn edsel(&mut self) -> EDSEL_W`[src]

Bits 20:21 - Edge Detect Select

`pub fn stretch(&mut self) -> STRETCH_W`[src]

Bit 25 - Stretch Channel Output

`pub fn inv(&mut self) -> INV_W`[src]

Bit 26 - Invert Channel

`pub fn orprev(&mut self) -> ORPREV_W`[src]

Bit 27 - Or Previous

`pub fn andnext(&mut self) -> ANDNEXT_W`[src]

Bit 28 - And Next

`pub fn asyncrefl(&mut self) -> ASYNCREFL_W`[src]

Bit 30 - Asynchronous Reflex

`impl W<u32, Reg<u32, _CH9_CTRL>>`[src]

`pub fn sigsel(&mut self) -> SIGSEL_W`[src]

Bits 0:2 - Signal Select

`pub fn sourcesel(&mut self) -> SOURCESEL_W`[src]

Bits 8:14 - Source Select

`pub fn edsel(&mut self) -> EDSEL_W`[src]

Bits 20:21 - Edge Detect Select

`pub fn stretch(&mut self) -> STRETCH_W`[src]

Bit 25 - Stretch Channel Output

`pub fn inv(&mut self) -> INV_W`[src]

Bit 26 - Invert Channel

`pub fn orprev(&mut self) -> ORPREV_W`[src]

Bit 27 - Or Previous

`pub fn andnext(&mut self) -> ANDNEXT_W`[src]

Bit 28 - And Next

`pub fn asyncrefl(&mut self) -> ASYNCREFL_W`[src]

Bit 30 - Asynchronous Reflex

`impl W<u32, Reg<u32, _CH10_CTRL>>`[src]

`pub fn sigsel(&mut self) -> SIGSEL_W`[src]

Bits 0:2 - Signal Select

`pub fn sourcesel(&mut self) -> SOURCESEL_W`[src]

Bits 8:14 - Source Select

`pub fn edsel(&mut self) -> EDSEL_W`[src]

Bits 20:21 - Edge Detect Select

`pub fn stretch(&mut self) -> STRETCH_W`[src]

Bit 25 - Stretch Channel Output

`pub fn inv(&mut self) -> INV_W`[src]

Bit 26 - Invert Channel

`pub fn orprev(&mut self) -> ORPREV_W`[src]

Bit 27 - Or Previous

`pub fn andnext(&mut self) -> ANDNEXT_W`[src]

Bit 28 - And Next

`pub fn asyncrefl(&mut self) -> ASYNCREFL_W`[src]

Bit 30 - Asynchronous Reflex

`impl W<u32, Reg<u32, _CH11_CTRL>>`[src]

`pub fn sigsel(&mut self) -> SIGSEL_W`[src]

Bits 0:2 - Signal Select

`pub fn sourcesel(&mut self) -> SOURCESEL_W`[src]

Bits 8:14 - Source Select

`pub fn edsel(&mut self) -> EDSEL_W`[src]

Bits 20:21 - Edge Detect Select

`pub fn stretch(&mut self) -> STRETCH_W`[src]

Bit 25 - Stretch Channel Output

`pub fn inv(&mut self) -> INV_W`[src]

Bit 26 - Invert Channel

`pub fn orprev(&mut self) -> ORPREV_W`[src]

Bit 27 - Or Previous

`pub fn andnext(&mut self) -> ANDNEXT_W`[src]

Bit 28 - And Next

`pub fn asyncrefl(&mut self) -> ASYNCREFL_W`[src]

Bit 30 - Asynchronous Reflex

`impl W<u32, Reg<u32, _CTRL>>`[src]

`pub fn syncprsseten(&mut self) -> SYNCPRSSETEN_W`[src]

Bits 0:7 - Synchronization PRS Set Enable

`pub fn syncprsclren(&mut self) -> SYNCPRSCLREN_W`[src]

Bits 8:15 - Synchronization PRS Clear Enable

`pub fn numfixed(&mut self) -> NUMFIXED_W`[src]

Bits 24:26 - Number of Fixed Priority Channels

`impl W<u32, Reg<u32, _SYNC>>`[src]

`pub fn synctrig(&mut self) -> SYNCTRIG_W`[src]

Bits 0:7 - Synchronization Trigger

`impl W<u32, Reg<u32, _CHEN>>`[src]

`pub fn chen(&mut self) -> CHEN_W`[src]

Bits 0:7 - Channel Enables

`impl W<u32, Reg<u32, _CHDONE>>`[src]

`pub fn chdone(&mut self) -> CHDONE_W`[src]

Bits 0:7 - DMA Channel Linking or Done

`impl W<u32, Reg<u32, _DBGHALT>>`[src]

`pub fn dbghalt(&mut self) -> DBGHALT_W`[src]

Bits 0:7 - DMA Debug Halt

`impl W<u32, Reg<u32, _SWREQ>>`[src]

`pub fn swreq(&mut self) -> SWREQ_W`[src]

Bits 0:7 - Software Transfer Requests

`impl W<u32, Reg<u32, _REQDIS>>`[src]

`pub fn reqdis(&mut self) -> REQDIS_W`[src]

Bits 0:7 - DMA Request Disables

`impl W<u32, Reg<u32, _LINKLOAD>>`[src]

`pub fn linkload(&mut self) -> LINKLOAD_W`[src]

Bits 0:7 - DMA Link Loads

`impl W<u32, Reg<u32, _REQCLEAR>>`[src]

`pub fn reqclear(&mut self) -> REQCLEAR_W`[src]

Bits 0:7 - DMA Request Clear

`impl W<u32, Reg<u32, _IFS>>`[src]

`pub fn done(&mut self) -> DONE_W`[src]

Bits 0:7 - Set DONE Interrupt Flag

`pub fn error(&mut self) -> ERROR_W`[src]

Bit 31 - Set ERROR Interrupt Flag

`impl W<u32, Reg<u32, _IFC>>`[src]

`pub fn done(&mut self) -> DONE_W`[src]

Bits 0:7 - Clear DONE Interrupt Flag

`pub fn error(&mut self) -> ERROR_W`[src]

Bit 31 - Clear ERROR Interrupt Flag

`impl W<u32, Reg<u32, _IEN>>`[src]

`pub fn done(&mut self) -> DONE_W`[src]

Bits 0:7 - DONE Interrupt Enable

`pub fn error(&mut self) -> ERROR_W`[src]

Bit 31 - ERROR Interrupt Enable

`impl W<u32, Reg<u32, _CH0_REQSEL>>`[src]

`pub fn sigsel(&mut self) -> SIGSEL_W`[src]

Bits 0:3 - Signal Select

`pub fn sourcesel(&mut self) -> SOURCESEL_W`[src]

Bits 16:21 - Source Select

`impl W<u32, Reg<u32, _CH0_CFG>>`[src]

`pub fn arbslots(&mut self) -> ARBSLOTS_W`[src]

Bits 16:17 - Arbitration Slot Number Select

`pub fn srcincsign(&mut self) -> SRCINCSIGN_W`[src]

Bit 20 - Source Address Increment Sign

`pub fn dstincsign(&mut self) -> DSTINCSIGN_W`[src]

Bit 21 - Destination Address Increment Sign

`impl W<u32, Reg<u32, _CH0_LOOP>>`[src]

`pub fn loopcnt(&mut self) -> LOOPCNT_W`[src]

Bits 0:7 - Linked Structure Sequence Loop Counter

`impl W<u32, Reg<u32, _CH0_CTRL>>`[src]

`pub fn structreq(&mut self) -> STRUCTREQ_W`[src]

Bit 3 - Structure DMA Transfer Request

`pub fn xfercnt(&mut self) -> XFERCNT_W`[src]

Bits 4:14 - DMA Unit Data Transfer Count

`pub fn byteswap(&mut self) -> BYTESWAP_W`[src]

Bit 15 - Endian Byte Swap

`pub fn blocksize(&mut self) -> BLOCKSIZE_W`[src]

Bits 16:19 - Block Transfer Size

`pub fn doneifsen(&mut self) -> DONEIFSEN_W`[src]

Bit 20 - DMA Operation Done Interrupt Flag Set Enable

`pub fn reqmode(&mut self) -> REQMODE_W`[src]

Bit 21 - DMA Request Transfer Mode Select

`pub fn decloopcnt(&mut self) -> DECLOOPCNT_W`[src]

Bit 22 - Decrement Loop Count

`pub fn ignoresreq(&mut self) -> IGNORESREQ_W`[src]

Bit 23 - Ignore Sreq

`pub fn srcinc(&mut self) -> SRCINC_W`[src]

Bits 24:25 - Source Address Increment Size

`pub fn size(&mut self) -> SIZE_W`[src]

Bits 26:27 - Unit Data Transfer Size

`pub fn dstinc(&mut self) -> DSTINC_W`[src]

Bits 28:29 - Destination Address Increment Size

`impl W<u32, Reg<u32, _CH0_SRC>>`[src]

`pub fn srcaddr(&mut self) -> SRCADDR_W`[src]

Bits 0:31 - Source Data Address

`impl W<u32, Reg<u32, _CH0_DST>>`[src]

`pub fn dstaddr(&mut self) -> DSTADDR_W`[src]

Bits 0:31 - Destination Data Address

`impl W<u32, Reg<u32, _CH0_LINK>>`[src]

`pub fn link(&mut self) -> LINK_W`[src]

Bit 1 - Link Next Structure

`pub fn linkaddr(&mut self) -> LINKADDR_W`[src]

Bits 2:31 - Link Structure Address

`impl W<u32, Reg<u32, _CH1_REQSEL>>`[src]

`pub fn sigsel(&mut self) -> SIGSEL_W`[src]

Bits 0:3 - Signal Select

`pub fn sourcesel(&mut self) -> SOURCESEL_W`[src]

Bits 16:21 - Source Select

`impl W<u32, Reg<u32, _CH1_CFG>>`[src]

`pub fn arbslots(&mut self) -> ARBSLOTS_W`[src]

Bits 16:17 - Arbitration Slot Number Select

`pub fn srcincsign(&mut self) -> SRCINCSIGN_W`[src]

Bit 20 - Source Address Increment Sign

`pub fn dstincsign(&mut self) -> DSTINCSIGN_W`[src]

Bit 21 - Destination Address Increment Sign

`impl W<u32, Reg<u32, _CH1_LOOP>>`[src]

`pub fn loopcnt(&mut self) -> LOOPCNT_W`[src]

Bits 0:7 - Linked Structure Sequence Loop Counter

`impl W<u32, Reg<u32, _CH1_CTRL>>`[src]

`pub fn structreq(&mut self) -> STRUCTREQ_W`[src]

Bit 3 - Structure DMA Transfer Request

`pub fn xfercnt(&mut self) -> XFERCNT_W`[src]

Bits 4:14 - DMA Unit Data Transfer Count

`pub fn byteswap(&mut self) -> BYTESWAP_W`[src]

Bit 15 - Endian Byte Swap

`pub fn blocksize(&mut self) -> BLOCKSIZE_W`[src]

Bits 16:19 - Block Transfer Size

`pub fn doneifsen(&mut self) -> DONEIFSEN_W`[src]

Bit 20 - DMA Operation Done Interrupt Flag Set Enable

`pub fn reqmode(&mut self) -> REQMODE_W`[src]

Bit 21 - DMA Request Transfer Mode Select

`pub fn decloopcnt(&mut self) -> DECLOOPCNT_W`[src]

Bit 22 - Decrement Loop Count

`pub fn ignoresreq(&mut self) -> IGNORESREQ_W`[src]

Bit 23 - Ignore Sreq

`pub fn srcinc(&mut self) -> SRCINC_W`[src]

Bits 24:25 - Source Address Increment Size

`pub fn size(&mut self) -> SIZE_W`[src]

Bits 26:27 - Unit Data Transfer Size

`pub fn dstinc(&mut self) -> DSTINC_W`[src]

Bits 28:29 - Destination Address Increment Size

`impl W<u32, Reg<u32, _CH1_SRC>>`[src]

`pub fn srcaddr(&mut self) -> SRCADDR_W`[src]

Bits 0:31 - Source Data Address

`impl W<u32, Reg<u32, _CH1_DST>>`[src]

`pub fn dstaddr(&mut self) -> DSTADDR_W`[src]

Bits 0:31 - Destination Data Address

`impl W<u32, Reg<u32, _CH1_LINK>>`[src]

`pub fn link(&mut self) -> LINK_W`[src]

Bit 1 - Link Next Structure

`pub fn linkaddr(&mut self) -> LINKADDR_W`[src]

Bits 2:31 - Link Structure Address

`impl W<u32, Reg<u32, _CH2_REQSEL>>`[src]

`pub fn sigsel(&mut self) -> SIGSEL_W`[src]

Bits 0:3 - Signal Select

`pub fn sourcesel(&mut self) -> SOURCESEL_W`[src]

Bits 16:21 - Source Select

`impl W<u32, Reg<u32, _CH2_CFG>>`[src]

`pub fn arbslots(&mut self) -> ARBSLOTS_W`[src]

Bits 16:17 - Arbitration Slot Number Select

`pub fn srcincsign(&mut self) -> SRCINCSIGN_W`[src]

Bit 20 - Source Address Increment Sign

`pub fn dstincsign(&mut self) -> DSTINCSIGN_W`[src]

Bit 21 - Destination Address Increment Sign

`impl W<u32, Reg<u32, _CH2_LOOP>>`[src]

`pub fn loopcnt(&mut self) -> LOOPCNT_W`[src]

Bits 0:7 - Linked Structure Sequence Loop Counter

`impl W<u32, Reg<u32, _CH2_CTRL>>`[src]

`pub fn structreq(&mut self) -> STRUCTREQ_W`[src]

Bit 3 - Structure DMA Transfer Request

`pub fn xfercnt(&mut self) -> XFERCNT_W`[src]

Bits 4:14 - DMA Unit Data Transfer Count

`pub fn byteswap(&mut self) -> BYTESWAP_W`[src]

Bit 15 - Endian Byte Swap

`pub fn blocksize(&mut self) -> BLOCKSIZE_W`[src]

Bits 16:19 - Block Transfer Size

`pub fn doneifsen(&mut self) -> DONEIFSEN_W`[src]

Bit 20 - DMA Operation Done Interrupt Flag Set Enable

`pub fn reqmode(&mut self) -> REQMODE_W`[src]

Bit 21 - DMA Request Transfer Mode Select

`pub fn decloopcnt(&mut self) -> DECLOOPCNT_W`[src]

Bit 22 - Decrement Loop Count

`pub fn ignoresreq(&mut self) -> IGNORESREQ_W`[src]

Bit 23 - Ignore Sreq

`pub fn srcinc(&mut self) -> SRCINC_W`[src]

Bits 24:25 - Source Address Increment Size

`pub fn size(&mut self) -> SIZE_W`[src]

Bits 26:27 - Unit Data Transfer Size

`pub fn dstinc(&mut self) -> DSTINC_W`[src]

Bits 28:29 - Destination Address Increment Size

`impl W<u32, Reg<u32, _CH2_SRC>>`[src]

`pub fn srcaddr(&mut self) -> SRCADDR_W`[src]

Bits 0:31 - Source Data Address

`impl W<u32, Reg<u32, _CH2_DST>>`[src]

`pub fn dstaddr(&mut self) -> DSTADDR_W`[src]

Bits 0:31 - Destination Data Address

`impl W<u32, Reg<u32, _CH2_LINK>>`[src]

`pub fn link(&mut self) -> LINK_W`[src]

Bit 1 - Link Next Structure

`pub fn linkaddr(&mut self) -> LINKADDR_W`[src]

Bits 2:31 - Link Structure Address

`impl W<u32, Reg<u32, _CH3_REQSEL>>`[src]

`pub fn sigsel(&mut self) -> SIGSEL_W`[src]

Bits 0:3 - Signal Select

`pub fn sourcesel(&mut self) -> SOURCESEL_W`[src]

Bits 16:21 - Source Select

`impl W<u32, Reg<u32, _CH3_CFG>>`[src]

`pub fn arbslots(&mut self) -> ARBSLOTS_W`[src]

Bits 16:17 - Arbitration Slot Number Select

`pub fn srcincsign(&mut self) -> SRCINCSIGN_W`[src]

Bit 20 - Source Address Increment Sign

`pub fn dstincsign(&mut self) -> DSTINCSIGN_W`[src]

Bit 21 - Destination Address Increment Sign

`impl W<u32, Reg<u32, _CH3_LOOP>>`[src]

`pub fn loopcnt(&mut self) -> LOOPCNT_W`[src]

Bits 0:7 - Linked Structure Sequence Loop Counter

`impl W<u32, Reg<u32, _CH3_CTRL>>`[src]

`pub fn structreq(&mut self) -> STRUCTREQ_W`[src]

Bit 3 - Structure DMA Transfer Request

`pub fn xfercnt(&mut self) -> XFERCNT_W`[src]

Bits 4:14 - DMA Unit Data Transfer Count

`pub fn byteswap(&mut self) -> BYTESWAP_W`[src]

Bit 15 - Endian Byte Swap

`pub fn blocksize(&mut self) -> BLOCKSIZE_W`[src]

Bits 16:19 - Block Transfer Size

`pub fn doneifsen(&mut self) -> DONEIFSEN_W`[src]

Bit 20 - DMA Operation Done Interrupt Flag Set Enable

`pub fn reqmode(&mut self) -> REQMODE_W`[src]

Bit 21 - DMA Request Transfer Mode Select

`pub fn decloopcnt(&mut self) -> DECLOOPCNT_W`[src]

Bit 22 - Decrement Loop Count

`pub fn ignoresreq(&mut self) -> IGNORESREQ_W`[src]

Bit 23 - Ignore Sreq

`pub fn srcinc(&mut self) -> SRCINC_W`[src]

Bits 24:25 - Source Address Increment Size

`pub fn size(&mut self) -> SIZE_W`[src]

Bits 26:27 - Unit Data Transfer Size

`pub fn dstinc(&mut self) -> DSTINC_W`[src]

Bits 28:29 - Destination Address Increment Size

`impl W<u32, Reg<u32, _CH3_SRC>>`[src]

`pub fn srcaddr(&mut self) -> SRCADDR_W`[src]

Bits 0:31 - Source Data Address

`impl W<u32, Reg<u32, _CH3_DST>>`[src]

`pub fn dstaddr(&mut self) -> DSTADDR_W`[src]

Bits 0:31 - Destination Data Address

`impl W<u32, Reg<u32, _CH3_LINK>>`[src]

`pub fn link(&mut self) -> LINK_W`[src]

Bit 1 - Link Next Structure

`pub fn linkaddr(&mut self) -> LINKADDR_W`[src]

Bits 2:31 - Link Structure Address

`impl W<u32, Reg<u32, _CH4_REQSEL>>`[src]

`pub fn sigsel(&mut self) -> SIGSEL_W`[src]

Bits 0:3 - Signal Select

`pub fn sourcesel(&mut self) -> SOURCESEL_W`[src]

Bits 16:21 - Source Select

`impl W<u32, Reg<u32, _CH4_CFG>>`[src]

`pub fn arbslots(&mut self) -> ARBSLOTS_W`[src]

Bits 16:17 - Arbitration Slot Number Select

`pub fn srcincsign(&mut self) -> SRCINCSIGN_W`[src]

Bit 20 - Source Address Increment Sign

`pub fn dstincsign(&mut self) -> DSTINCSIGN_W`[src]

Bit 21 - Destination Address Increment Sign

`impl W<u32, Reg<u32, _CH4_LOOP>>`[src]

`pub fn loopcnt(&mut self) -> LOOPCNT_W`[src]

Bits 0:7 - Linked Structure Sequence Loop Counter

`impl W<u32, Reg<u32, _CH4_CTRL>>`[src]

`pub fn structreq(&mut self) -> STRUCTREQ_W`[src]

Bit 3 - Structure DMA Transfer Request

`pub fn xfercnt(&mut self) -> XFERCNT_W`[src]

Bits 4:14 - DMA Unit Data Transfer Count

`pub fn byteswap(&mut self) -> BYTESWAP_W`[src]

Bit 15 - Endian Byte Swap

`pub fn blocksize(&mut self) -> BLOCKSIZE_W`[src]

Bits 16:19 - Block Transfer Size

`pub fn doneifsen(&mut self) -> DONEIFSEN_W`[src]

Bit 20 - DMA Operation Done Interrupt Flag Set Enable

`pub fn reqmode(&mut self) -> REQMODE_W`[src]

Bit 21 - DMA Request Transfer Mode Select

`pub fn decloopcnt(&mut self) -> DECLOOPCNT_W`[src]

Bit 22 - Decrement Loop Count

`pub fn ignoresreq(&mut self) -> IGNORESREQ_W`[src]

Bit 23 - Ignore Sreq

`pub fn srcinc(&mut self) -> SRCINC_W`[src]

Bits 24:25 - Source Address Increment Size

`pub fn size(&mut self) -> SIZE_W`[src]

Bits 26:27 - Unit Data Transfer Size

`pub fn dstinc(&mut self) -> DSTINC_W`[src]

Bits 28:29 - Destination Address Increment Size

`impl W<u32, Reg<u32, _CH4_SRC>>`[src]

`pub fn srcaddr(&mut self) -> SRCADDR_W`[src]

Bits 0:31 - Source Data Address

`impl W<u32, Reg<u32, _CH4_DST>>`[src]

`pub fn dstaddr(&mut self) -> DSTADDR_W`[src]

Bits 0:31 - Destination Data Address

`impl W<u32, Reg<u32, _CH4_LINK>>`[src]

`pub fn link(&mut self) -> LINK_W`[src]

Bit 1 - Link Next Structure

`pub fn linkaddr(&mut self) -> LINKADDR_W`[src]

Bits 2:31 - Link Structure Address

`impl W<u32, Reg<u32, _CH5_REQSEL>>`[src]

`pub fn sigsel(&mut self) -> SIGSEL_W`[src]

Bits 0:3 - Signal Select

`pub fn sourcesel(&mut self) -> SOURCESEL_W`[src]

Bits 16:21 - Source Select

`impl W<u32, Reg<u32, _CH5_CFG>>`[src]

`pub fn arbslots(&mut self) -> ARBSLOTS_W`[src]

Bits 16:17 - Arbitration Slot Number Select

`pub fn srcincsign(&mut self) -> SRCINCSIGN_W`[src]

Bit 20 - Source Address Increment Sign

`pub fn dstincsign(&mut self) -> DSTINCSIGN_W`[src]

Bit 21 - Destination Address Increment Sign

`impl W<u32, Reg<u32, _CH5_LOOP>>`[src]

`pub fn loopcnt(&mut self) -> LOOPCNT_W`[src]

Bits 0:7 - Linked Structure Sequence Loop Counter

`impl W<u32, Reg<u32, _CH5_CTRL>>`[src]

`pub fn structreq(&mut self) -> STRUCTREQ_W`[src]

Bit 3 - Structure DMA Transfer Request

`pub fn xfercnt(&mut self) -> XFERCNT_W`[src]

Bits 4:14 - DMA Unit Data Transfer Count

`pub fn byteswap(&mut self) -> BYTESWAP_W`[src]

Bit 15 - Endian Byte Swap

`pub fn blocksize(&mut self) -> BLOCKSIZE_W`[src]

Bits 16:19 - Block Transfer Size

`pub fn doneifsen(&mut self) -> DONEIFSEN_W`[src]

Bit 20 - DMA Operation Done Interrupt Flag Set Enable

`pub fn reqmode(&mut self) -> REQMODE_W`[src]

Bit 21 - DMA Request Transfer Mode Select

`pub fn decloopcnt(&mut self) -> DECLOOPCNT_W`[src]

Bit 22 - Decrement Loop Count

`pub fn ignoresreq(&mut self) -> IGNORESREQ_W`[src]

Bit 23 - Ignore Sreq

`pub fn srcinc(&mut self) -> SRCINC_W`[src]

Bits 24:25 - Source Address Increment Size

`pub fn size(&mut self) -> SIZE_W`[src]

Bits 26:27 - Unit Data Transfer Size

`pub fn dstinc(&mut self) -> DSTINC_W`[src]

Bits 28:29 - Destination Address Increment Size

`impl W<u32, Reg<u32, _CH5_SRC>>`[src]

`pub fn srcaddr(&mut self) -> SRCADDR_W`[src]

Bits 0:31 - Source Data Address

`impl W<u32, Reg<u32, _CH5_DST>>`[src]

`pub fn dstaddr(&mut self) -> DSTADDR_W`[src]

Bits 0:31 - Destination Data Address

`impl W<u32, Reg<u32, _CH5_LINK>>`[src]

`pub fn link(&mut self) -> LINK_W`[src]

Bit 1 - Link Next Structure

`pub fn linkaddr(&mut self) -> LINKADDR_W`[src]

Bits 2:31 - Link Structure Address

`impl W<u32, Reg<u32, _CH6_REQSEL>>`[src]

`pub fn sigsel(&mut self) -> SIGSEL_W`[src]

Bits 0:3 - Signal Select

`pub fn sourcesel(&mut self) -> SOURCESEL_W`[src]

Bits 16:21 - Source Select

`impl W<u32, Reg<u32, _CH6_CFG>>`[src]

`pub fn arbslots(&mut self) -> ARBSLOTS_W`[src]

Bits 16:17 - Arbitration Slot Number Select

`pub fn srcincsign(&mut self) -> SRCINCSIGN_W`[src]

Bit 20 - Source Address Increment Sign

`pub fn dstincsign(&mut self) -> DSTINCSIGN_W`[src]

Bit 21 - Destination Address Increment Sign

`impl W<u32, Reg<u32, _CH6_LOOP>>`[src]

`pub fn loopcnt(&mut self) -> LOOPCNT_W`[src]

Bits 0:7 - Linked Structure Sequence Loop Counter

`impl W<u32, Reg<u32, _CH6_CTRL>>`[src]

`pub fn structreq(&mut self) -> STRUCTREQ_W`[src]

Bit 3 - Structure DMA Transfer Request

`pub fn xfercnt(&mut self) -> XFERCNT_W`[src]

Bits 4:14 - DMA Unit Data Transfer Count

`pub fn byteswap(&mut self) -> BYTESWAP_W`[src]

Bit 15 - Endian Byte Swap

`pub fn blocksize(&mut self) -> BLOCKSIZE_W`[src]

Bits 16:19 - Block Transfer Size

`pub fn doneifsen(&mut self) -> DONEIFSEN_W`[src]

Bit 20 - DMA Operation Done Interrupt Flag Set Enable

`pub fn reqmode(&mut self) -> REQMODE_W`[src]

Bit 21 - DMA Request Transfer Mode Select

`pub fn decloopcnt(&mut self) -> DECLOOPCNT_W`[src]

Bit 22 - Decrement Loop Count

`pub fn ignoresreq(&mut self) -> IGNORESREQ_W`[src]

Bit 23 - Ignore Sreq

`pub fn srcinc(&mut self) -> SRCINC_W`[src]

Bits 24:25 - Source Address Increment Size

`pub fn size(&mut self) -> SIZE_W`[src]

Bits 26:27 - Unit Data Transfer Size

`pub fn dstinc(&mut self) -> DSTINC_W`[src]

Bits 28:29 - Destination Address Increment Size

`impl W<u32, Reg<u32, _CH6_SRC>>`[src]

`pub fn srcaddr(&mut self) -> SRCADDR_W`[src]

Bits 0:31 - Source Data Address

`impl W<u32, Reg<u32, _CH6_DST>>`[src]

`pub fn dstaddr(&mut self) -> DSTADDR_W`[src]

Bits 0:31 - Destination Data Address

`impl W<u32, Reg<u32, _CH6_LINK>>`[src]

`pub fn link(&mut self) -> LINK_W`[src]

Bit 1 - Link Next Structure

`pub fn linkaddr(&mut self) -> LINKADDR_W`[src]

Bits 2:31 - Link Structure Address

`impl W<u32, Reg<u32, _CH7_REQSEL>>`[src]

`pub fn sigsel(&mut self) -> SIGSEL_W`[src]

Bits 0:3 - Signal Select

`pub fn sourcesel(&mut self) -> SOURCESEL_W`[src]

Bits 16:21 - Source Select

`impl W<u32, Reg<u32, _CH7_CFG>>`[src]

`pub fn arbslots(&mut self) -> ARBSLOTS_W`[src]

Bits 16:17 - Arbitration Slot Number Select

`pub fn srcincsign(&mut self) -> SRCINCSIGN_W`[src]

Bit 20 - Source Address Increment Sign

`pub fn dstincsign(&mut self) -> DSTINCSIGN_W`[src]

Bit 21 - Destination Address Increment Sign

`impl W<u32, Reg<u32, _CH7_LOOP>>`[src]

`pub fn loopcnt(&mut self) -> LOOPCNT_W`[src]

Bits 0:7 - Linked Structure Sequence Loop Counter

`impl W<u32, Reg<u32, _CH7_CTRL>>`[src]

`pub fn structreq(&mut self) -> STRUCTREQ_W`[src]

Bit 3 - Structure DMA Transfer Request

`pub fn xfercnt(&mut self) -> XFERCNT_W`[src]

Bits 4:14 - DMA Unit Data Transfer Count

`pub fn byteswap(&mut self) -> BYTESWAP_W`[src]

Bit 15 - Endian Byte Swap

`pub fn blocksize(&mut self) -> BLOCKSIZE_W`[src]

Bits 16:19 - Block Transfer Size

`pub fn doneifsen(&mut self) -> DONEIFSEN_W`[src]

Bit 20 - DMA Operation Done Interrupt Flag Set Enable

`pub fn reqmode(&mut self) -> REQMODE_W`[src]

Bit 21 - DMA Request Transfer Mode Select

`pub fn decloopcnt(&mut self) -> DECLOOPCNT_W`[src]

Bit 22 - Decrement Loop Count

`pub fn ignoresreq(&mut self) -> IGNORESREQ_W`[src]

Bit 23 - Ignore Sreq

`pub fn srcinc(&mut self) -> SRCINC_W`[src]

Bits 24:25 - Source Address Increment Size

`pub fn size(&mut self) -> SIZE_W`[src]

Bits 26:27 - Unit Data Transfer Size

`pub fn dstinc(&mut self) -> DSTINC_W`[src]

Bits 28:29 - Destination Address Increment Size

`impl W<u32, Reg<u32, _CH7_SRC>>`[src]

`pub fn srcaddr(&mut self) -> SRCADDR_W`[src]

Bits 0:31 - Source Data Address

`impl W<u32, Reg<u32, _CH7_DST>>`[src]

`pub fn dstaddr(&mut self) -> DSTADDR_W`[src]

Bits 0:31 - Destination Data Address

`impl W<u32, Reg<u32, _CH7_LINK>>`[src]

`pub fn link(&mut self) -> LINK_W`[src]

Bit 1 - Link Next Structure

`pub fn linkaddr(&mut self) -> LINKADDR_W`[src]

Bits 2:31 - Link Structure Address

`impl W<u32, Reg<u32, _IFS>>`[src]

`pub fn fpioc(&mut self) -> FPIOC_W`[src]

Bit 0 - Set FPIOC Interrupt Flag

`pub fn fpdzc(&mut self) -> FPDZC_W`[src]

Bit 1 - Set FPDZC Interrupt Flag

`pub fn fpufc(&mut self) -> FPUFC_W`[src]

Bit 2 - Set FPUFC Interrupt Flag

`pub fn fpofc(&mut self) -> FPOFC_W`[src]

Bit 3 - Set FPOFC Interrupt Flag

`pub fn fpidc(&mut self) -> FPIDC_W`[src]

Bit 4 - Set FPIDC Interrupt Flag

`pub fn fpixc(&mut self) -> FPIXC_W`[src]

Bit 5 - Set FPIXC Interrupt Flag

`impl W<u32, Reg<u32, _IFC>>`[src]

`pub fn fpioc(&mut self) -> FPIOC_W`[src]

Bit 0 - Clear FPIOC Interrupt Flag

`pub fn fpdzc(&mut self) -> FPDZC_W`[src]

Bit 1 - Clear FPDZC Interrupt Flag

`pub fn fpufc(&mut self) -> FPUFC_W`[src]

Bit 2 - Clear FPUFC Interrupt Flag

`pub fn fpofc(&mut self) -> FPOFC_W`[src]

Bit 3 - Clear FPOFC Interrupt Flag

`pub fn fpidc(&mut self) -> FPIDC_W`[src]

Bit 4 - Clear FPIDC Interrupt Flag

`pub fn fpixc(&mut self) -> FPIXC_W`[src]

Bit 5 - Clear FPIXC Interrupt Flag

`impl W<u32, Reg<u32, _IEN>>`[src]

`pub fn fpioc(&mut self) -> FPIOC_W`[src]

Bit 0 - FPIOC Interrupt Enable

`pub fn fpdzc(&mut self) -> FPDZC_W`[src]

Bit 1 - FPDZC Interrupt Enable

`pub fn fpufc(&mut self) -> FPUFC_W`[src]

Bit 2 - FPUFC Interrupt Enable

`pub fn fpofc(&mut self) -> FPOFC_W`[src]

Bit 3 - FPOFC Interrupt Enable

`pub fn fpidc(&mut self) -> FPIDC_W`[src]

Bit 4 - FPIDC Interrupt Enable

`pub fn fpixc(&mut self) -> FPIXC_W`[src]

Bit 5 - FPIXC Interrupt Enable

`impl W<u32, Reg<u32, _CTRL>>`[src]

`pub fn en(&mut self) -> EN_W`[src]

Bit 0 - CRC Functionality Enable

`pub fn polysel(&mut self) -> POLYSEL_W`[src]

Bit 4 - Polynomial Select

`pub fn bytemode(&mut self) -> BYTEMODE_W`[src]

Bit 8 - Byte Mode Enable

`pub fn bitreverse(&mut self) -> BITREVERSE_W`[src]

Bit 9 - Byte-level Bit Reverse Enable

`pub fn bytereverse(&mut self) -> BYTEREVERSE_W`[src]

Bit 10 - Byte Reverse Mode

`pub fn autoinit(&mut self) -> AUTOINIT_W`[src]

Bit 13 - Auto Init Enable

`impl W<u32, Reg<u32, _CMD>>`[src]

`pub fn init(&mut self) -> INIT_W`[src]

Bit 0 - Initialization Enable

`impl W<u32, Reg<u32, _INIT>>`[src]

`pub fn init(&mut self) -> INIT_W`[src]

Bits 0:31 - CRC Initialization Value

`impl W<u32, Reg<u32, _POLY>>`[src]

`pub fn poly(&mut self) -> POLY_W`[src]

Bits 0:15 - CRC Polynomial Value

`impl W<u32, Reg<u32, _INPUTDATA>>`[src]

`pub fn inputdata(&mut self) -> INPUTDATA_W`[src]

Bits 0:31 - Input Data for 32-bit

`impl W<u32, Reg<u32, _INPUTDATAHWORD>>`[src]

`pub fn inputdatahword(&mut self) -> INPUTDATAHWORD_W`[src]

Bits 0:15 - Input Data for 16-bit

`impl W<u32, Reg<u32, _INPUTDATABYTE>>`[src]

`pub fn inputdatabyte(&mut self) -> INPUTDATABYTE_W`[src]

Bits 0:7 - Input Data for 8-bit

`impl W<u32, Reg<u32, _CTRL>>`[src]

`pub fn mode(&mut self) -> MODE_W`[src]

Bits 0:1 - Timer Mode

`pub fn sync(&mut self) -> SYNC_W`[src]

Bit 3 - Timer Start/Stop/Reload Synchronization

`pub fn osmen(&mut self) -> OSMEN_W`[src]

Bit 4 - One-shot Mode Enable

`pub fn qdm(&mut self) -> QDM_W`[src]

Bit 5 - Quadrature Decoder Mode Selection

`pub fn debugrun(&mut self) -> DEBUGRUN_W`[src]

Bit 6 - Debug Mode Run Enable

`pub fn dmaclract(&mut self) -> DMACLRACT_W`[src]

Bit 7 - DMA Request Clear on Active

`pub fn risea(&mut self) -> RISEA_W`[src]

Bits 8:9 - Timer Rising Input Edge Action

`pub fn falla(&mut self) -> FALLA_W`[src]

Bits 10:11 - Timer Falling Input Edge Action

`pub fn x2cnt(&mut self) -> X2CNT_W`[src]

Bit 13 - 2x Count Mode

`pub fn clksel(&mut self) -> CLKSEL_W`[src]

Bits 16:17 - Clock Source Select

`pub fn presc(&mut self) -> PRESC_W`[src]

Bits 24:27 - Prescaler Setting

`pub fn ati(&mut self) -> ATI_W`[src]

Bit 28 - Always Track Inputs

`pub fn rsscoist(&mut self) -> RSSCOIST_W`[src]

Bit 29 - Reload-Start Sets Compare Output Initial State

`impl W<u32, Reg<u32, _CMD>>`[src]

`pub fn start(&mut self) -> START_W`[src]

Bit 0 - Start Timer

`pub fn stop(&mut self) -> STOP_W`[src]

Bit 1 - Stop Timer

`impl W<u32, Reg<u32, _IFS>>`[src]

`pub fn of(&mut self) -> OF_W`[src]

Bit 0 - Set OF Interrupt Flag

`pub fn uf(&mut self) -> UF_W`[src]

Bit 1 - Set UF Interrupt Flag

`pub fn dirchg(&mut self) -> DIRCHG_W`[src]

Bit 2 - Set DIRCHG Interrupt Flag

`pub fn cc0(&mut self) -> CC0_W`[src]

Bit 4 - Set CC0 Interrupt Flag

`pub fn cc1(&mut self) -> CC1_W`[src]

Bit 5 - Set CC1 Interrupt Flag

`pub fn cc2(&mut self) -> CC2_W`[src]

Bit 6 - Set CC2 Interrupt Flag

`pub fn cc3(&mut self) -> CC3_W`[src]

Bit 7 - Set CC3 Interrupt Flag

`pub fn icbof0(&mut self) -> ICBOF0_W`[src]

Bit 8 - Set ICBOF0 Interrupt Flag

`pub fn icbof1(&mut self) -> ICBOF1_W`[src]

Bit 9 - Set ICBOF1 Interrupt Flag

`pub fn icbof2(&mut self) -> ICBOF2_W`[src]

Bit 10 - Set ICBOF2 Interrupt Flag

`pub fn icbof3(&mut self) -> ICBOF3_W`[src]

Bit 11 - Set ICBOF3 Interrupt Flag

`impl W<u32, Reg<u32, _IFC>>`[src]

`pub fn of(&mut self) -> OF_W`[src]

Bit 0 - Clear OF Interrupt Flag

`pub fn uf(&mut self) -> UF_W`[src]

Bit 1 - Clear UF Interrupt Flag

`pub fn dirchg(&mut self) -> DIRCHG_W`[src]

Bit 2 - Clear DIRCHG Interrupt Flag

`pub fn cc0(&mut self) -> CC0_W`[src]

Bit 4 - Clear CC0 Interrupt Flag

`pub fn cc1(&mut self) -> CC1_W`[src]

Bit 5 - Clear CC1 Interrupt Flag

`pub fn cc2(&mut self) -> CC2_W`[src]

Bit 6 - Clear CC2 Interrupt Flag

`pub fn cc3(&mut self) -> CC3_W`[src]

Bit 7 - Clear CC3 Interrupt Flag

`pub fn icbof0(&mut self) -> ICBOF0_W`[src]

Bit 8 - Clear ICBOF0 Interrupt Flag

`pub fn icbof1(&mut self) -> ICBOF1_W`[src]

Bit 9 - Clear ICBOF1 Interrupt Flag

`pub fn icbof2(&mut self) -> ICBOF2_W`[src]

Bit 10 - Clear ICBOF2 Interrupt Flag

`pub fn icbof3(&mut self) -> ICBOF3_W`[src]

Bit 11 - Clear ICBOF3 Interrupt Flag

`impl W<u32, Reg<u32, _IEN>>`[src]

`pub fn of(&mut self) -> OF_W`[src]

Bit 0 - OF Interrupt Enable

`pub fn uf(&mut self) -> UF_W`[src]

Bit 1 - UF Interrupt Enable

`pub fn dirchg(&mut self) -> DIRCHG_W`[src]

Bit 2 - DIRCHG Interrupt Enable

`pub fn cc0(&mut self) -> CC0_W`[src]

Bit 4 - CC0 Interrupt Enable

`pub fn cc1(&mut self) -> CC1_W`[src]

Bit 5 - CC1 Interrupt Enable

`pub fn cc2(&mut self) -> CC2_W`[src]

Bit 6 - CC2 Interrupt Enable

`pub fn cc3(&mut self) -> CC3_W`[src]

Bit 7 - CC3 Interrupt Enable

`pub fn icbof0(&mut self) -> ICBOF0_W`[src]

Bit 8 - ICBOF0 Interrupt Enable

`pub fn icbof1(&mut self) -> ICBOF1_W`[src]

Bit 9 - ICBOF1 Interrupt Enable

`pub fn icbof2(&mut self) -> ICBOF2_W`[src]

Bit 10 - ICBOF2 Interrupt Enable

`pub fn icbof3(&mut self) -> ICBOF3_W`[src]

Bit 11 - ICBOF3 Interrupt Enable

`impl W<u32, Reg<u32, _TOP>>`[src]

`pub fn top(&mut self) -> TOP_W`[src]

Bits 0:15 - Counter Top Value

`impl W<u32, Reg<u32, _TOPB>>`[src]

`pub fn topb(&mut self) -> TOPB_W`[src]

Bits 0:15 - Counter Top Value Buffer

`impl W<u32, Reg<u32, _CNT>>`[src]

`pub fn cnt(&mut self) -> CNT_W`[src]

Bits 0:15 - Counter Value

`impl W<u32, Reg<u32, _LOCK>>`[src]

`pub fn timerlockkey(&mut self) -> TIMERLOCKKEY_W`[src]

Bits 0:15 - Timer Lock Key

`impl W<u32, Reg<u32, _ROUTEPEN>>`[src]

`pub fn cc0pen(&mut self) -> CC0PEN_W`[src]

Bit 0 - CC Channel 0 Pin Enable

`pub fn cc1pen(&mut self) -> CC1PEN_W`[src]

Bit 1 - CC Channel 1 Pin Enable

`pub fn cc2pen(&mut self) -> CC2PEN_W`[src]

Bit 2 - CC Channel 2 Pin Enable

`pub fn cc3pen(&mut self) -> CC3PEN_W`[src]

Bit 3 - CC Channel 3 Pin Enable

`pub fn cdti0pen(&mut self) -> CDTI0PEN_W`[src]

Bit 8 - CC Channel 0 Complementary Dead-Time Insertion Pin Enable

`pub fn cdti1pen(&mut self) -> CDTI1PEN_W`[src]

Bit 9 - CC Channel 1 Complementary Dead-Time Insertion Pin Enable

`pub fn cdti2pen(&mut self) -> CDTI2PEN_W`[src]

Bit 10 - CC Channel 2 Complementary Dead-Time Insertion Pin Enable

`impl W<u32, Reg<u32, _ROUTELOC0>>`[src]

`pub fn cc0loc(&mut self) -> CC0LOC_W`[src]

Bits 0:5 - I/O Location

`pub fn cc1loc(&mut self) -> CC1LOC_W`[src]

Bits 8:13 - I/O Location

`pub fn cc2loc(&mut self) -> CC2LOC_W`[src]

Bits 16:21 - I/O Location

`pub fn cc3loc(&mut self) -> CC3LOC_W`[src]

Bits 24:29 - I/O Location

`impl W<u32, Reg<u32, _ROUTELOC2>>`[src]

`pub fn cdti0loc(&mut self) -> CDTI0LOC_W`[src]

Bits 0:5 - I/O Location

`pub fn cdti1loc(&mut self) -> CDTI1LOC_W`[src]

Bits 8:13 - I/O Location

`pub fn cdti2loc(&mut self) -> CDTI2LOC_W`[src]

Bits 16:21 - I/O Location

`impl W<u32, Reg<u32, _CC0_CTRL>>`[src]

`pub fn mode(&mut self) -> MODE_W`[src]

Bits 0:1 - CC Channel Mode

`pub fn outinv(&mut self) -> OUTINV_W`[src]

Bit 2 - Output Invert

`pub fn coist(&mut self) -> COIST_W`[src]

Bit 4 - Compare Output Initial State

`pub fn cmoa(&mut self) -> CMOA_W`[src]

Bits 8:9 - Compare Match Output Action

`pub fn cofoa(&mut self) -> COFOA_W`[src]

Bits 10:11 - Counter Overflow Output Action

`pub fn cufoa(&mut self) -> CUFOA_W`[src]

Bits 12:13 - Counter Underflow Output Action

`pub fn prssel(&mut self) -> PRSSEL_W`[src]

Bits 16:19 - Compare/Capture Channel PRS Input Channel Selection

`pub fn icedge(&mut self) -> ICEDGE_W`[src]

Bits 24:25 - Input Capture Edge Select

`pub fn icevctrl(&mut self) -> ICEVCTRL_W`[src]

Bits 26:27 - Input Capture Event Control

`pub fn prsconf(&mut self) -> PRSCONF_W`[src]

Bit 28 - PRS Configuration

`pub fn insel(&mut self) -> INSEL_W`[src]

Bit 29 - Input Selection

`pub fn filt(&mut self) -> FILT_W`[src]

Bit 30 - Digital Filter

`impl W<u32, Reg<u32, _CC0_CCV>>`[src]

`pub fn ccv(&mut self) -> CCV_W`[src]

Bits 0:15 - CC Channel Value

`impl W<u32, Reg<u32, _CC0_CCVB>>`[src]

`pub fn ccvb(&mut self) -> CCVB_W`[src]

Bits 0:15 - CC Channel Value Buffer

`impl W<u32, Reg<u32, _CC1_CTRL>>`[src]

`pub fn mode(&mut self) -> MODE_W`[src]

Bits 0:1 - CC Channel Mode

`pub fn outinv(&mut self) -> OUTINV_W`[src]

Bit 2 - Output Invert

`pub fn coist(&mut self) -> COIST_W`[src]

Bit 4 - Compare Output Initial State

`pub fn cmoa(&mut self) -> CMOA_W`[src]

Bits 8:9 - Compare Match Output Action

`pub fn cofoa(&mut self) -> COFOA_W`[src]

Bits 10:11 - Counter Overflow Output Action

`pub fn cufoa(&mut self) -> CUFOA_W`[src]

Bits 12:13 - Counter Underflow Output Action

`pub fn prssel(&mut self) -> PRSSEL_W`[src]

Bits 16:19 - Compare/Capture Channel PRS Input Channel Selection

`pub fn icedge(&mut self) -> ICEDGE_W`[src]

Bits 24:25 - Input Capture Edge Select

`pub fn icevctrl(&mut self) -> ICEVCTRL_W`[src]

Bits 26:27 - Input Capture Event Control

`pub fn prsconf(&mut self) -> PRSCONF_W`[src]

Bit 28 - PRS Configuration

`pub fn insel(&mut self) -> INSEL_W`[src]

Bit 29 - Input Selection

`pub fn filt(&mut self) -> FILT_W`[src]

Bit 30 - Digital Filter

`impl W<u32, Reg<u32, _CC1_CCV>>`[src]

`pub fn ccv(&mut self) -> CCV_W`[src]

Bits 0:15 - CC Channel Value

`impl W<u32, Reg<u32, _CC1_CCVB>>`[src]

`pub fn ccvb(&mut self) -> CCVB_W`[src]

Bits 0:15 - CC Channel Value Buffer

`impl W<u32, Reg<u32, _CC2_CTRL>>`[src]

`pub fn mode(&mut self) -> MODE_W`[src]

Bits 0:1 - CC Channel Mode

`pub fn outinv(&mut self) -> OUTINV_W`[src]

Bit 2 - Output Invert

`pub fn coist(&mut self) -> COIST_W`[src]

Bit 4 - Compare Output Initial State

`pub fn cmoa(&mut self) -> CMOA_W`[src]

Bits 8:9 - Compare Match Output Action

`pub fn cofoa(&mut self) -> COFOA_W`[src]

Bits 10:11 - Counter Overflow Output Action

`pub fn cufoa(&mut self) -> CUFOA_W`[src]

Bits 12:13 - Counter Underflow Output Action

`pub fn prssel(&mut self) -> PRSSEL_W`[src]

Bits 16:19 - Compare/Capture Channel PRS Input Channel Selection

`pub fn icedge(&mut self) -> ICEDGE_W`[src]

Bits 24:25 - Input Capture Edge Select

`pub fn icevctrl(&mut self) -> ICEVCTRL_W`[src]

Bits 26:27 - Input Capture Event Control

`pub fn prsconf(&mut self) -> PRSCONF_W`[src]

Bit 28 - PRS Configuration

`pub fn insel(&mut self) -> INSEL_W`[src]

Bit 29 - Input Selection

`pub fn filt(&mut self) -> FILT_W`[src]

Bit 30 - Digital Filter

`impl W<u32, Reg<u32, _CC2_CCV>>`[src]

`pub fn ccv(&mut self) -> CCV_W`[src]

Bits 0:15 - CC Channel Value

`impl W<u32, Reg<u32, _CC2_CCVB>>`[src]

`pub fn ccvb(&mut self) -> CCVB_W`[src]

Bits 0:15 - CC Channel Value Buffer

`impl W<u32, Reg<u32, _CC3_CTRL>>`[src]

`pub fn mode(&mut self) -> MODE_W`[src]

Bits 0:1 - CC Channel Mode

`pub fn outinv(&mut self) -> OUTINV_W`[src]

Bit 2 - Output Invert

`pub fn coist(&mut self) -> COIST_W`[src]

Bit 4 - Compare Output Initial State

`pub fn cmoa(&mut self) -> CMOA_W`[src]

Bits 8:9 - Compare Match Output Action

`pub fn cofoa(&mut self) -> COFOA_W`[src]

Bits 10:11 - Counter Overflow Output Action

`pub fn cufoa(&mut self) -> CUFOA_W`[src]

Bits 12:13 - Counter Underflow Output Action

`pub fn prssel(&mut self) -> PRSSEL_W`[src]

Bits 16:19 - Compare/Capture Channel PRS Input Channel Selection

`pub fn icedge(&mut self) -> ICEDGE_W`[src]

Bits 24:25 - Input Capture Edge Select

`pub fn icevctrl(&mut self) -> ICEVCTRL_W`[src]

Bits 26:27 - Input Capture Event Control

`pub fn prsconf(&mut self) -> PRSCONF_W`[src]

Bit 28 - PRS Configuration

`pub fn insel(&mut self) -> INSEL_W`[src]

Bit 29 - Input Selection

`pub fn filt(&mut self) -> FILT_W`[src]

Bit 30 - Digital Filter

`impl W<u32, Reg<u32, _CC3_CCV>>`[src]

`pub fn ccv(&mut self) -> CCV_W`[src]

Bits 0:15 - CC Channel Value

`impl W<u32, Reg<u32, _CC3_CCVB>>`[src]

`pub fn ccvb(&mut self) -> CCVB_W`[src]

Bits 0:15 - CC Channel Value Buffer

`impl W<u32, Reg<u32, _DTCTRL>>`[src]

`pub fn dten(&mut self) -> DTEN_W`[src]

Bit 0 - DTI Enable

`pub fn dtdas(&mut self) -> DTDAS_W`[src]

Bit 1 - DTI Automatic Start-up Functionality

`pub fn dtipol(&mut self) -> DTIPOL_W`[src]

Bit 2 - DTI Inactive Polarity

`pub fn dtcinv(&mut self) -> DTCINV_W`[src]

Bit 3 - DTI Complementary Output Invert

`pub fn dtprssel(&mut self) -> DTPRSSEL_W`[src]

Bits 4:7 - DTI PRS Source Channel Select

`pub fn dtar(&mut self) -> DTAR_W`[src]

Bit 9 - DTI Always Run

`pub fn dtfats(&mut self) -> DTFATS_W`[src]

Bit 10 - DTI Fault Action on Timer Stop

`pub fn dtprsen(&mut self) -> DTPRSEN_W`[src]

Bit 24 - DTI PRS Source Enable

`impl W<u32, Reg<u32, _DTTIME>>`[src]

`pub fn dtpresc(&mut self) -> DTPRESC_W`[src]

Bits 0:3 - DTI Prescaler Setting

`pub fn dtriset(&mut self) -> DTRISET_W`[src]

Bits 8:13 - DTI Rise-time

`pub fn dtfallt(&mut self) -> DTFALLT_W`[src]

Bits 16:21 - DTI Fall-time

`impl W<u32, Reg<u32, _DTFC>>`[src]

`pub fn dtprs0fsel(&mut self) -> DTPRS0FSEL_W`[src]

Bits 0:3 - DTI PRS Fault Source 0 Select

`pub fn dtprs1fsel(&mut self) -> DTPRS1FSEL_W`[src]

Bits 8:11 - DTI PRS Fault Source 1 Select

`pub fn dtfa(&mut self) -> DTFA_W`[src]

Bits 16:17 - DTI Fault Action

`pub fn dtprs0fen(&mut self) -> DTPRS0FEN_W`[src]

Bit 24 - DTI PRS 0 Fault Enable

`pub fn dtprs1fen(&mut self) -> DTPRS1FEN_W`[src]

Bit 25 - DTI PRS 1 Fault Enable

`pub fn dtdbgfen(&mut self) -> DTDBGFEN_W`[src]

Bit 26 - DTI Debugger Fault Enable

`pub fn dtlockupfen(&mut self) -> DTLOCKUPFEN_W`[src]

Bit 27 - DTI Lockup Fault Enable

`impl W<u32, Reg<u32, _DTOGEN>>`[src]

`pub fn dtogcc0en(&mut self) -> DTOGCC0EN_W`[src]

Bit 0 - DTI CC0 Output Generation Enable

`pub fn dtogcc1en(&mut self) -> DTOGCC1EN_W`[src]

Bit 1 - DTI CC1 Output Generation Enable

`pub fn dtogcc2en(&mut self) -> DTOGCC2EN_W`[src]

Bit 2 - DTI CC2 Output Generation Enable

`pub fn dtogcdti0en(&mut self) -> DTOGCDTI0EN_W`[src]

Bit 3 - DTI CDTI0 Output Generation Enable

`pub fn dtogcdti1en(&mut self) -> DTOGCDTI1EN_W`[src]

Bit 4 - DTI CDTI1 Output Generation Enable

`pub fn dtogcdti2en(&mut self) -> DTOGCDTI2EN_W`[src]

Bit 5 - DTI CDTI2 Output Generation Enable

`impl W<u32, Reg<u32, _DTFAULTC>>`[src]

`pub fn dtprs0fc(&mut self) -> DTPRS0FC_W`[src]

Bit 0 - DTI PRS0 Fault Clear

`pub fn dtprs1fc(&mut self) -> DTPRS1FC_W`[src]

Bit 1 - DTI PRS1 Fault Clear

`pub fn dtdbgfc(&mut self) -> DTDBGFC_W`[src]

Bit 2 - DTI Debugger Fault Clear

`pub fn tlockupfc(&mut self) -> TLOCKUPFC_W`[src]

Bit 3 - DTI Lockup Fault Clear

`impl W<u32, Reg<u32, _DTLOCK>>`[src]

`pub fn lockkey(&mut self) -> LOCKKEY_W`[src]

Bits 0:15 - DTI Lock Key

`impl W<u32, Reg<u32, _CTRL>>`[src]

`pub fn mode(&mut self) -> MODE_W`[src]

Bits 0:1 - Timer Mode

`pub fn sync(&mut self) -> SYNC_W`[src]

Bit 3 - Timer Start/Stop/Reload Synchronization

`pub fn osmen(&mut self) -> OSMEN_W`[src]

Bit 4 - One-shot Mode Enable

`pub fn qdm(&mut self) -> QDM_W`[src]

Bit 5 - Quadrature Decoder Mode Selection

`pub fn debugrun(&mut self) -> DEBUGRUN_W`[src]

Bit 6 - Debug Mode Run Enable

`pub fn dmaclract(&mut self) -> DMACLRACT_W`[src]

Bit 7 - DMA Request Clear on Active

`pub fn risea(&mut self) -> RISEA_W`[src]

Bits 8:9 - Timer Rising Input Edge Action

`pub fn falla(&mut self) -> FALLA_W`[src]

Bits 10:11 - Timer Falling Input Edge Action

`pub fn x2cnt(&mut self) -> X2CNT_W`[src]

Bit 13 - 2x Count Mode

`pub fn clksel(&mut self) -> CLKSEL_W`[src]

Bits 16:17 - Clock Source Select

`pub fn presc(&mut self) -> PRESC_W`[src]

Bits 24:27 - Prescaler Setting

`pub fn ati(&mut self) -> ATI_W`[src]

Bit 28 - Always Track Inputs

`pub fn rsscoist(&mut self) -> RSSCOIST_W`[src]

Bit 29 - Reload-Start Sets Compare Output Initial State

`impl W<u32, Reg<u32, _CMD>>`[src]

`pub fn start(&mut self) -> START_W`[src]

Bit 0 - Start Timer

`pub fn stop(&mut self) -> STOP_W`[src]

Bit 1 - Stop Timer

`impl W<u32, Reg<u32, _IFS>>`[src]

`pub fn of(&mut self) -> OF_W`[src]

Bit 0 - Set OF Interrupt Flag

`pub fn uf(&mut self) -> UF_W`[src]

Bit 1 - Set UF Interrupt Flag

`pub fn dirchg(&mut self) -> DIRCHG_W`[src]

Bit 2 - Set DIRCHG Interrupt Flag

`pub fn cc0(&mut self) -> CC0_W`[src]

Bit 4 - Set CC0 Interrupt Flag

`pub fn cc1(&mut self) -> CC1_W`[src]

Bit 5 - Set CC1 Interrupt Flag

`pub fn cc2(&mut self) -> CC2_W`[src]

Bit 6 - Set CC2 Interrupt Flag

`pub fn cc3(&mut self) -> CC3_W`[src]

Bit 7 - Set CC3 Interrupt Flag

`pub fn icbof0(&mut self) -> ICBOF0_W`[src]

Bit 8 - Set ICBOF0 Interrupt Flag

`pub fn icbof1(&mut self) -> ICBOF1_W`[src]

Bit 9 - Set ICBOF1 Interrupt Flag

`pub fn icbof2(&mut self) -> ICBOF2_W`[src]

Bit 10 - Set ICBOF2 Interrupt Flag

`pub fn icbof3(&mut self) -> ICBOF3_W`[src]

Bit 11 - Set ICBOF3 Interrupt Flag

`impl W<u32, Reg<u32, _IFC>>`[src]

`pub fn of(&mut self) -> OF_W`[src]

Bit 0 - Clear OF Interrupt Flag

`pub fn uf(&mut self) -> UF_W`[src]

Bit 1 - Clear UF Interrupt Flag

`pub fn dirchg(&mut self) -> DIRCHG_W`[src]

Bit 2 - Clear DIRCHG Interrupt Flag

`pub fn cc0(&mut self) -> CC0_W`[src]

Bit 4 - Clear CC0 Interrupt Flag

`pub fn cc1(&mut self) -> CC1_W`[src]

Bit 5 - Clear CC1 Interrupt Flag

`pub fn cc2(&mut self) -> CC2_W`[src]

Bit 6 - Clear CC2 Interrupt Flag

`pub fn cc3(&mut self) -> CC3_W`[src]

Bit 7 - Clear CC3 Interrupt Flag

`pub fn icbof0(&mut self) -> ICBOF0_W`[src]

Bit 8 - Clear ICBOF0 Interrupt Flag

`pub fn icbof1(&mut self) -> ICBOF1_W`[src]

Bit 9 - Clear ICBOF1 Interrupt Flag

`pub fn icbof2(&mut self) -> ICBOF2_W`[src]

Bit 10 - Clear ICBOF2 Interrupt Flag

`pub fn icbof3(&mut self) -> ICBOF3_W`[src]

Bit 11 - Clear ICBOF3 Interrupt Flag

`impl W<u32, Reg<u32, _IEN>>`[src]

`pub fn of(&mut self) -> OF_W`[src]

Bit 0 - OF Interrupt Enable

`pub fn uf(&mut self) -> UF_W`[src]

Bit 1 - UF Interrupt Enable

`pub fn dirchg(&mut self) -> DIRCHG_W`[src]

Bit 2 - DIRCHG Interrupt Enable

`pub fn cc0(&mut self) -> CC0_W`[src]

Bit 4 - CC0 Interrupt Enable

`pub fn cc1(&mut self) -> CC1_W`[src]

Bit 5 - CC1 Interrupt Enable

`pub fn cc2(&mut self) -> CC2_W`[src]

Bit 6 - CC2 Interrupt Enable

`pub fn cc3(&mut self) -> CC3_W`[src]

Bit 7 - CC3 Interrupt Enable

`pub fn icbof0(&mut self) -> ICBOF0_W`[src]

Bit 8 - ICBOF0 Interrupt Enable

`pub fn icbof1(&mut self) -> ICBOF1_W`[src]

Bit 9 - ICBOF1 Interrupt Enable

`pub fn icbof2(&mut self) -> ICBOF2_W`[src]

Bit 10 - ICBOF2 Interrupt Enable

`pub fn icbof3(&mut self) -> ICBOF3_W`[src]

Bit 11 - ICBOF3 Interrupt Enable

`impl W<u32, Reg<u32, _TOP>>`[src]

`pub fn top(&mut self) -> TOP_W`[src]

Bits 0:15 - Counter Top Value

`impl W<u32, Reg<u32, _TOPB>>`[src]

`pub fn topb(&mut self) -> TOPB_W`[src]

Bits 0:15 - Counter Top Value Buffer

`impl W<u32, Reg<u32, _CNT>>`[src]

`pub fn cnt(&mut self) -> CNT_W`[src]

Bits 0:15 - Counter Value

`impl W<u32, Reg<u32, _LOCK>>`[src]

`pub fn timerlockkey(&mut self) -> TIMERLOCKKEY_W`[src]

Bits 0:15 - Timer Lock Key

`impl W<u32, Reg<u32, _ROUTEPEN>>`[src]

`pub fn cc0pen(&mut self) -> CC0PEN_W`[src]

Bit 0 - CC Channel 0 Pin Enable

`pub fn cc1pen(&mut self) -> CC1PEN_W`[src]

Bit 1 - CC Channel 1 Pin Enable

`pub fn cc2pen(&mut self) -> CC2PEN_W`[src]

Bit 2 - CC Channel 2 Pin Enable

`pub fn cc3pen(&mut self) -> CC3PEN_W`[src]

Bit 3 - CC Channel 3 Pin Enable

`pub fn cdti0pen(&mut self) -> CDTI0PEN_W`[src]

Bit 8 - CC Channel 0 Complementary Dead-Time Insertion Pin Enable

`pub fn cdti1pen(&mut self) -> CDTI1PEN_W`[src]

Bit 9 - CC Channel 1 Complementary Dead-Time Insertion Pin Enable

`pub fn cdti2pen(&mut self) -> CDTI2PEN_W`[src]

Bit 10 - CC Channel 2 Complementary Dead-Time Insertion Pin Enable

`impl W<u32, Reg<u32, _ROUTELOC0>>`[src]

`pub fn cc0loc(&mut self) -> CC0LOC_W`[src]

Bits 0:5 - I/O Location

`pub fn cc1loc(&mut self) -> CC1LOC_W`[src]

Bits 8:13 - I/O Location

`pub fn cc2loc(&mut self) -> CC2LOC_W`[src]

Bits 16:21 - I/O Location

`pub fn cc3loc(&mut self) -> CC3LOC_W`[src]

Bits 24:29 - I/O Location

`impl W<u32, Reg<u32, _ROUTELOC2>>`[src]

`pub fn cdti0loc(&mut self) -> CDTI0LOC_W`[src]

Bits 0:5 - I/O Location

`pub fn cdti1loc(&mut self) -> CDTI1LOC_W`[src]

Bits 8:13 - I/O Location

`pub fn cdti2loc(&mut self) -> CDTI2LOC_W`[src]

Bits 16:21 - I/O Location

`impl W<u32, Reg<u32, _CC0_CTRL>>`[src]

`pub fn mode(&mut self) -> MODE_W`[src]

Bits 0:1 - CC Channel Mode

`pub fn outinv(&mut self) -> OUTINV_W`[src]

Bit 2 - Output Invert

`pub fn coist(&mut self) -> COIST_W`[src]

Bit 4 - Compare Output Initial State

`pub fn cmoa(&mut self) -> CMOA_W`[src]

Bits 8:9 - Compare Match Output Action

`pub fn cofoa(&mut self) -> COFOA_W`[src]

Bits 10:11 - Counter Overflow Output Action

`pub fn cufoa(&mut self) -> CUFOA_W`[src]

Bits 12:13 - Counter Underflow Output Action

`pub fn prssel(&mut self) -> PRSSEL_W`[src]

Bits 16:19 - Compare/Capture Channel PRS Input Channel Selection

`pub fn icedge(&mut self) -> ICEDGE_W`[src]

Bits 24:25 - Input Capture Edge Select

`pub fn icevctrl(&mut self) -> ICEVCTRL_W`[src]

Bits 26:27 - Input Capture Event Control

`pub fn prsconf(&mut self) -> PRSCONF_W`[src]

Bit 28 - PRS Configuration

`pub fn insel(&mut self) -> INSEL_W`[src]

Bit 29 - Input Selection

`pub fn filt(&mut self) -> FILT_W`[src]

Bit 30 - Digital Filter

`impl W<u32, Reg<u32, _CC0_CCV>>`[src]

`pub fn ccv(&mut self) -> CCV_W`[src]

Bits 0:15 - CC Channel Value

`impl W<u32, Reg<u32, _CC0_CCVB>>`[src]

`pub fn ccvb(&mut self) -> CCVB_W`[src]

Bits 0:15 - CC Channel Value Buffer

`impl W<u32, Reg<u32, _CC1_CTRL>>`[src]

`pub fn mode(&mut self) -> MODE_W`[src]

Bits 0:1 - CC Channel Mode

`pub fn outinv(&mut self) -> OUTINV_W`[src]

Bit 2 - Output Invert

`pub fn coist(&mut self) -> COIST_W`[src]

Bit 4 - Compare Output Initial State

`pub fn cmoa(&mut self) -> CMOA_W`[src]

Bits 8:9 - Compare Match Output Action

`pub fn cofoa(&mut self) -> COFOA_W`[src]

Bits 10:11 - Counter Overflow Output Action

`pub fn cufoa(&mut self) -> CUFOA_W`[src]

Bits 12:13 - Counter Underflow Output Action

`pub fn prssel(&mut self) -> PRSSEL_W`[src]

Bits 16:19 - Compare/Capture Channel PRS Input Channel Selection

`pub fn icedge(&mut self) -> ICEDGE_W`[src]

Bits 24:25 - Input Capture Edge Select

`pub fn icevctrl(&mut self) -> ICEVCTRL_W`[src]

Bits 26:27 - Input Capture Event Control

`pub fn prsconf(&mut self) -> PRSCONF_W`[src]

Bit 28 - PRS Configuration

`pub fn insel(&mut self) -> INSEL_W`[src]

Bit 29 - Input Selection

`pub fn filt(&mut self) -> FILT_W`[src]

Bit 30 - Digital Filter

`impl W<u32, Reg<u32, _CC1_CCV>>`[src]

`pub fn ccv(&mut self) -> CCV_W`[src]

Bits 0:15 - CC Channel Value

`impl W<u32, Reg<u32, _CC1_CCVB>>`[src]

`pub fn ccvb(&mut self) -> CCVB_W`[src]

Bits 0:15 - CC Channel Value Buffer

`impl W<u32, Reg<u32, _CC2_CTRL>>`[src]

`pub fn mode(&mut self) -> MODE_W`[src]

Bits 0:1 - CC Channel Mode

`pub fn outinv(&mut self) -> OUTINV_W`[src]

Bit 2 - Output Invert

`pub fn coist(&mut self) -> COIST_W`[src]

Bit 4 - Compare Output Initial State

`pub fn cmoa(&mut self) -> CMOA_W`[src]

Bits 8:9 - Compare Match Output Action

`pub fn cofoa(&mut self) -> COFOA_W`[src]

Bits 10:11 - Counter Overflow Output Action

`pub fn cufoa(&mut self) -> CUFOA_W`[src]

Bits 12:13 - Counter Underflow Output Action

`pub fn prssel(&mut self) -> PRSSEL_W`[src]

Bits 16:19 - Compare/Capture Channel PRS Input Channel Selection

`pub fn icedge(&mut self) -> ICEDGE_W`[src]

Bits 24:25 - Input Capture Edge Select

`pub fn icevctrl(&mut self) -> ICEVCTRL_W`[src]

Bits 26:27 - Input Capture Event Control

`pub fn prsconf(&mut self) -> PRSCONF_W`[src]

Bit 28 - PRS Configuration

`pub fn insel(&mut self) -> INSEL_W`[src]

Bit 29 - Input Selection

`pub fn filt(&mut self) -> FILT_W`[src]

Bit 30 - Digital Filter

`impl W<u32, Reg<u32, _CC2_CCV>>`[src]

`pub fn ccv(&mut self) -> CCV_W`[src]

Bits 0:15 - CC Channel Value

`impl W<u32, Reg<u32, _CC2_CCVB>>`[src]

`pub fn ccvb(&mut self) -> CCVB_W`[src]

Bits 0:15 - CC Channel Value Buffer

`impl W<u32, Reg<u32, _CC3_CTRL>>`[src]

`pub fn mode(&mut self) -> MODE_W`[src]

Bits 0:1 - CC Channel Mode

`pub fn outinv(&mut self) -> OUTINV_W`[src]

Bit 2 - Output Invert

`pub fn coist(&mut self) -> COIST_W`[src]

Bit 4 - Compare Output Initial State

`pub fn cmoa(&mut self) -> CMOA_W`[src]

Bits 8:9 - Compare Match Output Action

`pub fn cofoa(&mut self) -> COFOA_W`[src]

Bits 10:11 - Counter Overflow Output Action

`pub fn cufoa(&mut self) -> CUFOA_W`[src]

Bits 12:13 - Counter Underflow Output Action

`pub fn prssel(&mut self) -> PRSSEL_W`[src]

Bits 16:19 - Compare/Capture Channel PRS Input Channel Selection

`pub fn icedge(&mut self) -> ICEDGE_W`[src]

Bits 24:25 - Input Capture Edge Select

`pub fn icevctrl(&mut self) -> ICEVCTRL_W`[src]

Bits 26:27 - Input Capture Event Control

`pub fn prsconf(&mut self) -> PRSCONF_W`[src]

Bit 28 - PRS Configuration

`pub fn insel(&mut self) -> INSEL_W`[src]

Bit 29 - Input Selection

`pub fn filt(&mut self) -> FILT_W`[src]

Bit 30 - Digital Filter

`impl W<u32, Reg<u32, _CC3_CCV>>`[src]

`pub fn ccv(&mut self) -> CCV_W`[src]

Bits 0:15 - CC Channel Value

`impl W<u32, Reg<u32, _CC3_CCVB>>`[src]

`pub fn ccvb(&mut self) -> CCVB_W`[src]

Bits 0:15 - CC Channel Value Buffer

`impl W<u32, Reg<u32, _DTCTRL>>`[src]

`pub fn dten(&mut self) -> DTEN_W`[src]

Bit 0 - DTI Enable

`pub fn dtdas(&mut self) -> DTDAS_W`[src]

Bit 1 - DTI Automatic Start-up Functionality

`pub fn dtipol(&mut self) -> DTIPOL_W`[src]

Bit 2 - DTI Inactive Polarity

`pub fn dtcinv(&mut self) -> DTCINV_W`[src]

Bit 3 - DTI Complementary Output Invert

`pub fn dtprssel(&mut self) -> DTPRSSEL_W`[src]

Bits 4:7 - DTI PRS Source Channel Select

`pub fn dtar(&mut self) -> DTAR_W`[src]

Bit 9 - DTI Always Run

`pub fn dtfats(&mut self) -> DTFATS_W`[src]

Bit 10 - DTI Fault Action on Timer Stop

`pub fn dtprsen(&mut self) -> DTPRSEN_W`[src]

Bit 24 - DTI PRS Source Enable

`impl W<u32, Reg<u32, _DTTIME>>`[src]

`pub fn dtpresc(&mut self) -> DTPRESC_W`[src]

Bits 0:3 - DTI Prescaler Setting

`pub fn dtriset(&mut self) -> DTRISET_W`[src]

Bits 8:13 - DTI Rise-time

`pub fn dtfallt(&mut self) -> DTFALLT_W`[src]

Bits 16:21 - DTI Fall-time

`impl W<u32, Reg<u32, _DTFC>>`[src]

`pub fn dtprs0fsel(&mut self) -> DTPRS0FSEL_W`[src]

Bits 0:3 - DTI PRS Fault Source 0 Select

`pub fn dtprs1fsel(&mut self) -> DTPRS1FSEL_W`[src]

Bits 8:11 - DTI PRS Fault Source 1 Select

`pub fn dtfa(&mut self) -> DTFA_W`[src]

Bits 16:17 - DTI Fault Action

`pub fn dtprs0fen(&mut self) -> DTPRS0FEN_W`[src]

Bit 24 - DTI PRS 0 Fault Enable

`pub fn dtprs1fen(&mut self) -> DTPRS1FEN_W`[src]

Bit 25 - DTI PRS 1 Fault Enable

`pub fn dtdbgfen(&mut self) -> DTDBGFEN_W`[src]

Bit 26 - DTI Debugger Fault Enable

`pub fn dtlockupfen(&mut self) -> DTLOCKUPFEN_W`[src]

Bit 27 - DTI Lockup Fault Enable

`impl W<u32, Reg<u32, _DTOGEN>>`[src]

`pub fn dtogcc0en(&mut self) -> DTOGCC0EN_W`[src]

Bit 0 - DTI CC0 Output Generation Enable

`pub fn dtogcc1en(&mut self) -> DTOGCC1EN_W`[src]

Bit 1 - DTI CC1 Output Generation Enable

`pub fn dtogcc2en(&mut self) -> DTOGCC2EN_W`[src]

Bit 2 - DTI CC2 Output Generation Enable

`pub fn dtogcdti0en(&mut self) -> DTOGCDTI0EN_W`[src]

Bit 3 - DTI CDTI0 Output Generation Enable

`pub fn dtogcdti1en(&mut self) -> DTOGCDTI1EN_W`[src]

Bit 4 - DTI CDTI1 Output Generation Enable

`pub fn dtogcdti2en(&mut self) -> DTOGCDTI2EN_W`[src]

Bit 5 - DTI CDTI2 Output Generation Enable

`impl W<u32, Reg<u32, _DTFAULTC>>`[src]

`pub fn dtprs0fc(&mut self) -> DTPRS0FC_W`[src]

Bit 0 - DTI PRS0 Fault Clear

`pub fn dtprs1fc(&mut self) -> DTPRS1FC_W`[src]

Bit 1 - DTI PRS1 Fault Clear

`pub fn dtdbgfc(&mut self) -> DTDBGFC_W`[src]

Bit 2 - DTI Debugger Fault Clear

`pub fn tlockupfc(&mut self) -> TLOCKUPFC_W`[src]

Bit 3 - DTI Lockup Fault Clear

`impl W<u32, Reg<u32, _DTLOCK>>`[src]

`pub fn lockkey(&mut self) -> LOCKKEY_W`[src]

Bits 0:15 - DTI Lock Key

`impl W<u32, Reg<u32, _CTRL>>`[src]

`pub fn sync(&mut self) -> SYNC_W`[src]

Bit 0 - USART Synchronous Mode

`pub fn loopbk(&mut self) -> LOOPBK_W`[src]

Bit 1 - Loopback Enable

`pub fn ccen(&mut self) -> CCEN_W`[src]

Bit 2 - Collision Check Enable

`pub fn mpm(&mut self) -> MPM_W`[src]

Bit 3 - Multi-Processor Mode

`pub fn mpab(&mut self) -> MPAB_W`[src]

Bit 4 - Multi-Processor Address-Bit

`pub fn ovs(&mut self) -> OVS_W`[src]

Bits 5:6 - Oversampling

`pub fn clkpol(&mut self) -> CLKPOL_W`[src]

Bit 8 - Clock Polarity

`pub fn clkpha(&mut self) -> CLKPHA_W`[src]

Bit 9 - Clock Edge for Setup/Sample

`pub fn msbf(&mut self) -> MSBF_W`[src]

Bit 10 - Most Significant Bit First

`pub fn csma(&mut self) -> CSMA_W`[src]

Bit 11 - Action on Slave-Select in Master Mode

`pub fn txbil(&mut self) -> TXBIL_W`[src]

Bit 12 - TX Buffer Interrupt Level

`pub fn rxinv(&mut self) -> RXINV_W`[src]

Bit 13 - Receiver Input Invert

`pub fn txinv(&mut self) -> TXINV_W`[src]

Bit 14 - Transmitter Output Invert

`pub fn csinv(&mut self) -> CSINV_W`[src]

Bit 15 - Chip Select Invert

`pub fn autocs(&mut self) -> AUTOCS_W`[src]

Bit 16 - Automatic Chip Select

`pub fn autotri(&mut self) -> AUTOTRI_W`[src]

Bit 17 - Automatic TX Tristate

`pub fn scmode(&mut self) -> SCMODE_W`[src]

Bit 18 - SmartCard Mode

`pub fn scretrans(&mut self) -> SCRETRANS_W`[src]

Bit 19 - SmartCard Retransmit

`pub fn skipperrf(&mut self) -> SKIPPERRF_W`[src]

Bit 20 - Skip Parity Error Frames

`pub fn bit8dv(&mut self) -> BIT8DV_W`[src]

Bit 21 - Bit 8 Default Value

`pub fn errsdma(&mut self) -> ERRSDMA_W`[src]

Bit 22 - Halt DMA on Error

`pub fn errsrx(&mut self) -> ERRSRX_W`[src]

Bit 23 - Disable RX on Error

`pub fn errstx(&mut self) -> ERRSTX_W`[src]

Bit 24 - Disable TX on Error

`pub fn sssearly(&mut self) -> SSSEARLY_W`[src]

Bit 25 - Synchronous Slave Setup Early

`pub fn byteswap(&mut self) -> BYTESWAP_W`[src]

Bit 28 - Byteswap in Double Accesses

`pub fn autotx(&mut self) -> AUTOTX_W`[src]

Bit 29 - Always Transmit When RX Not Full

`pub fn mvdis(&mut self) -> MVDIS_W`[src]

Bit 30 - Majority Vote Disable

`pub fn smsdelay(&mut self) -> SMSDELAY_W`[src]

Bit 31 - Synchronous Master Sample Delay

`impl W<u32, Reg<u32, _FRAME>>`[src]

`pub fn databits(&mut self) -> DATABITS_W`[src]

Bits 0:3 - Data-Bit Mode

`pub fn parity(&mut self) -> PARITY_W`[src]

Bits 8:9 - Parity-Bit Mode

`pub fn stopbits(&mut self) -> STOPBITS_W`[src]

Bits 12:13 - Stop-Bit Mode

`impl W<u32, Reg<u32, _TRIGCTRL>>`[src]

`pub fn rxten(&mut self) -> RXTEN_W`[src]

Bit 4 - Receive Trigger Enable

`pub fn txten(&mut self) -> TXTEN_W`[src]

Bit 5 - Transmit Trigger Enable

`pub fn autotxten(&mut self) -> AUTOTXTEN_W`[src]

Bit 6 - AUTOTX Trigger Enable

`pub fn txarx0en(&mut self) -> TXARX0EN_W`[src]

Bit 7 - Enable Transmit Trigger After RX End of Frame Plus TCMP0VAL

`pub fn txarx1en(&mut self) -> TXARX1EN_W`[src]

Bit 8 - Enable Transmit Trigger After RX End of Frame Plus TCMP1VAL

`pub fn txarx2en(&mut self) -> TXARX2EN_W`[src]

Bit 9 - Enable Transmit Trigger After RX End of Frame Plus TCMP2VAL

`pub fn rxatx0en(&mut self) -> RXATX0EN_W`[src]

Bit 10 - Enable Receive Trigger After TX End of Frame Plus TCMPVAL0 Baud-times

`pub fn rxatx1en(&mut self) -> RXATX1EN_W`[src]

Bit 11 - Enable Receive Trigger After TX End of Frame Plus TCMPVAL1 Baud-times

`pub fn rxatx2en(&mut self) -> RXATX2EN_W`[src]

Bit 12 - Enable Receive Trigger After TX End of Frame Plus TCMPVAL2 Baud-times

`pub fn tsel(&mut self) -> TSEL_W`[src]

Bits 16:19 - Trigger PRS Channel Select

`impl W<u32, Reg<u32, _CMD>>`[src]

`pub fn rxen(&mut self) -> RXEN_W`[src]

Bit 0 - Receiver Enable

`pub fn rxdis(&mut self) -> RXDIS_W`[src]

Bit 1 - Receiver Disable

`pub fn txen(&mut self) -> TXEN_W`[src]

Bit 2 - Transmitter Enable

`pub fn txdis(&mut self) -> TXDIS_W`[src]

Bit 3 - Transmitter Disable

`pub fn masteren(&mut self) -> MASTEREN_W`[src]

Bit 4 - Master Enable

`pub fn masterdis(&mut self) -> MASTERDIS_W`[src]

Bit 5 - Master Disable

`pub fn rxblocken(&mut self) -> RXBLOCKEN_W`[src]

Bit 6 - Receiver Block Enable

`pub fn rxblockdis(&mut self) -> RXBLOCKDIS_W`[src]

Bit 7 - Receiver Block Disable

`pub fn txtrien(&mut self) -> TXTRIEN_W`[src]

Bit 8 - Transmitter Tristate Enable

`pub fn txtridis(&mut self) -> TXTRIDIS_W`[src]

Bit 9 - Transmitter Tristate Disable

`pub fn cleartx(&mut self) -> CLEARTX_W`[src]

Bit 10 - Clear TX

`pub fn clearrx(&mut self) -> CLEARRX_W`[src]

Bit 11 - Clear RX

`impl W<u32, Reg<u32, _CLKDIV>>`[src]

`pub fn div(&mut self) -> DIV_W`[src]

Bits 3:22 - Fractional Clock Divider

`pub fn autobauden(&mut self) -> AUTOBAUDEN_W`[src]

Bit 31 - AUTOBAUD Detection Enable

`impl W<u32, Reg<u32, _TXDATAX>>`[src]

`pub fn txdatax(&mut self) -> TXDATAX_W`[src]

Bits 0:8 - TX Data

`pub fn ubrxat(&mut self) -> UBRXAT_W`[src]

Bit 11 - Unblock RX After Transmission

`pub fn txtriat(&mut self) -> TXTRIAT_W`[src]

Bit 12 - Set TXTRI After Transmission

`pub fn txbreak(&mut self) -> TXBREAK_W`[src]

Bit 13 - Transmit Data as Break

`pub fn txdisat(&mut self) -> TXDISAT_W`[src]

Bit 14 - Clear TXEN After Transmission

`pub fn rxenat(&mut self) -> RXENAT_W`[src]

Bit 15 - Enable RX After Transmission

`impl W<u32, Reg<u32, _TXDATA>>`[src]

`pub fn txdata(&mut self) -> TXDATA_W`[src]

Bits 0:7 - TX Data

`impl W<u32, Reg<u32, _TXDOUBLEX>>`[src]

`pub fn txdata0(&mut self) -> TXDATA0_W`[src]

Bits 0:8 - TX Data

`pub fn ubrxat0(&mut self) -> UBRXAT0_W`[src]

Bit 11 - Unblock RX After Transmission

`pub fn txtriat0(&mut self) -> TXTRIAT0_W`[src]

Bit 12 - Set TXTRI After Transmission

`pub fn txbreak0(&mut self) -> TXBREAK0_W`[src]

Bit 13 - Transmit Data as Break

`pub fn txdisat0(&mut self) -> TXDISAT0_W`[src]

Bit 14 - Clear TXEN After Transmission

`pub fn rxenat0(&mut self) -> RXENAT0_W`[src]

Bit 15 - Enable RX After Transmission

`pub fn txdata1(&mut self) -> TXDATA1_W`[src]

Bits 16:24 - TX Data

`pub fn ubrxat1(&mut self) -> UBRXAT1_W`[src]

Bit 27 - Unblock RX After Transmission

`pub fn txtriat1(&mut self) -> TXTRIAT1_W`[src]

Bit 28 - Set TXTRI After Transmission

`pub fn txbreak1(&mut self) -> TXBREAK1_W`[src]

Bit 29 - Transmit Data as Break

`pub fn txdisat1(&mut self) -> TXDISAT1_W`[src]

Bit 30 - Clear TXEN After Transmission

`pub fn rxenat1(&mut self) -> RXENAT1_W`[src]

Bit 31 - Enable RX After Transmission

`impl W<u32, Reg<u32, _TXDOUBLE>>`[src]

`pub fn txdata0(&mut self) -> TXDATA0_W`[src]

Bits 0:7 - TX Data

`pub fn txdata1(&mut self) -> TXDATA1_W`[src]

Bits 8:15 - TX Data

`impl W<u32, Reg<u32, _IFS>>`[src]

`pub fn txc(&mut self) -> TXC_W`[src]

Bit 0 - Set TXC Interrupt Flag

`pub fn rxfull(&mut self) -> RXFULL_W`[src]

Bit 3 - Set RXFULL Interrupt Flag

`pub fn rxof(&mut self) -> RXOF_W`[src]

Bit 4 - Set RXOF Interrupt Flag

`pub fn rxuf(&mut self) -> RXUF_W`[src]

Bit 5 - Set RXUF Interrupt Flag

`pub fn txof(&mut self) -> TXOF_W`[src]

Bit 6 - Set TXOF Interrupt Flag

`pub fn txuf(&mut self) -> TXUF_W`[src]

Bit 7 - Set TXUF Interrupt Flag

`pub fn perr(&mut self) -> PERR_W`[src]

Bit 8 - Set PERR Interrupt Flag

`pub fn ferr(&mut self) -> FERR_W`[src]

Bit 9 - Set FERR Interrupt Flag

`pub fn mpaf(&mut self) -> MPAF_W`[src]

Bit 10 - Set MPAF Interrupt Flag

`pub fn ssm(&mut self) -> SSM_W`[src]

Bit 11 - Set SSM Interrupt Flag

`pub fn ccf(&mut self) -> CCF_W`[src]

Bit 12 - Set CCF Interrupt Flag

`pub fn txidle(&mut self) -> TXIDLE_W`[src]

Bit 13 - Set TXIDLE Interrupt Flag

`pub fn tcmp0(&mut self) -> TCMP0_W`[src]

Bit 14 - Set TCMP0 Interrupt Flag

`pub fn tcmp1(&mut self) -> TCMP1_W`[src]

Bit 15 - Set TCMP1 Interrupt Flag

`pub fn tcmp2(&mut self) -> TCMP2_W`[src]

Bit 16 - Set TCMP2 Interrupt Flag

`impl W<u32, Reg<u32, _IFC>>`[src]

`pub fn txc(&mut self) -> TXC_W`[src]

Bit 0 - Clear TXC Interrupt Flag

`pub fn rxfull(&mut self) -> RXFULL_W`[src]

Bit 3 - Clear RXFULL Interrupt Flag

`pub fn rxof(&mut self) -> RXOF_W`[src]

Bit 4 - Clear RXOF Interrupt Flag

`pub fn rxuf(&mut self) -> RXUF_W`[src]

Bit 5 - Clear RXUF Interrupt Flag

`pub fn txof(&mut self) -> TXOF_W`[src]

Bit 6 - Clear TXOF Interrupt Flag

`pub fn txuf(&mut self) -> TXUF_W`[src]

Bit 7 - Clear TXUF Interrupt Flag

`pub fn perr(&mut self) -> PERR_W`[src]

Bit 8 - Clear PERR Interrupt Flag

`pub fn ferr(&mut self) -> FERR_W`[src]

Bit 9 - Clear FERR Interrupt Flag

`pub fn mpaf(&mut self) -> MPAF_W`[src]

Bit 10 - Clear MPAF Interrupt Flag

`pub fn ssm(&mut self) -> SSM_W`[src]

Bit 11 - Clear SSM Interrupt Flag

`pub fn ccf(&mut self) -> CCF_W`[src]

Bit 12 - Clear CCF Interrupt Flag

`pub fn txidle(&mut self) -> TXIDLE_W`[src]

Bit 13 - Clear TXIDLE Interrupt Flag

`pub fn tcmp0(&mut self) -> TCMP0_W`[src]

Bit 14 - Clear TCMP0 Interrupt Flag

`pub fn tcmp1(&mut self) -> TCMP1_W`[src]

Bit 15 - Clear TCMP1 Interrupt Flag

`pub fn tcmp2(&mut self) -> TCMP2_W`[src]

Bit 16 - Clear TCMP2 Interrupt Flag

`impl W<u32, Reg<u32, _IEN>>`[src]

`pub fn txc(&mut self) -> TXC_W`[src]

Bit 0 - TXC Interrupt Enable

`pub fn txbl(&mut self) -> TXBL_W`[src]

Bit 1 - TXBL Interrupt Enable

`pub fn rxdatav(&mut self) -> RXDATAV_W`[src]

Bit 2 - RXDATAV Interrupt Enable

`pub fn rxfull(&mut self) -> RXFULL_W`[src]

Bit 3 - RXFULL Interrupt Enable

`pub fn rxof(&mut self) -> RXOF_W`[src]

Bit 4 - RXOF Interrupt Enable

`pub fn rxuf(&mut self) -> RXUF_W`[src]

Bit 5 - RXUF Interrupt Enable

`pub fn txof(&mut self) -> TXOF_W`[src]

Bit 6 - TXOF Interrupt Enable

`pub fn txuf(&mut self) -> TXUF_W`[src]

Bit 7 - TXUF Interrupt Enable

`pub fn perr(&mut self) -> PERR_W`[src]

Bit 8 - PERR Interrupt Enable

`pub fn ferr(&mut self) -> FERR_W`[src]

Bit 9 - FERR Interrupt Enable

`pub fn mpaf(&mut self) -> MPAF_W`[src]

Bit 10 - MPAF Interrupt Enable

`pub fn ssm(&mut self) -> SSM_W`[src]

Bit 11 - SSM Interrupt Enable

`pub fn ccf(&mut self) -> CCF_W`[src]

Bit 12 - CCF Interrupt Enable

`pub fn txidle(&mut self) -> TXIDLE_W`[src]

Bit 13 - TXIDLE Interrupt Enable

`pub fn tcmp0(&mut self) -> TCMP0_W`[src]

Bit 14 - TCMP0 Interrupt Enable

`pub fn tcmp1(&mut self) -> TCMP1_W`[src]

Bit 15 - TCMP1 Interrupt Enable

`pub fn tcmp2(&mut self) -> TCMP2_W`[src]

Bit 16 - TCMP2 Interrupt Enable

`impl W<u32, Reg<u32, _IRCTRL>>`[src]

`pub fn iren(&mut self) -> IREN_W`[src]

Bit 0 - Enable IrDA Module

`pub fn irpw(&mut self) -> IRPW_W`[src]

Bits 1:2 - IrDA TX Pulse Width

`pub fn irfilt(&mut self) -> IRFILT_W`[src]

Bit 3 - IrDA RX Filter

`pub fn irprsen(&mut self) -> IRPRSEN_W`[src]

Bit 7 - IrDA PRS Channel Enable

`pub fn irprssel(&mut self) -> IRPRSSEL_W`[src]

Bits 8:11 - IrDA PRS Channel Select

`impl W<u32, Reg<u32, _INPUT>>`[src]

`pub fn rxprssel(&mut self) -> RXPRSSEL_W`[src]

Bits 0:3 - RX PRS Channel Select

`pub fn rxprs(&mut self) -> RXPRS_W`[src]

Bit 7 - PRS RX Enable

`pub fn clkprssel(&mut self) -> CLKPRSSEL_W`[src]

Bits 8:11 - CLK PRS Channel Select

`pub fn clkprs(&mut self) -> CLKPRS_W`[src]

Bit 15 - PRS CLK Enable

`impl W<u32, Reg<u32, _I2SCTRL>>`[src]

`pub fn en(&mut self) -> EN_W`[src]

Bit 0 - Enable I2S Mode

`pub fn mono(&mut self) -> MONO_W`[src]

Bit 1 - Stero or Mono

`pub fn justify(&mut self) -> JUSTIFY_W`[src]

Bit 2 - Justification of I2S Data

`pub fn dmasplit(&mut self) -> DMASPLIT_W`[src]

Bit 3 - Separate DMA Request for Left/Right Data

`pub fn delay(&mut self) -> DELAY_W`[src]

Bit 4 - Delay on I2S Data

`pub fn format(&mut self) -> FORMAT_W`[src]

Bits 8:10 - I2S Word Format

`impl W<u32, Reg<u32, _TIMING>>`[src]

`pub fn txdelay(&mut self) -> TXDELAY_W`[src]

Bits 16:18 - TX Frame Start Delay

`pub fn cssetup(&mut self) -> CSSETUP_W`[src]

Bits 20:22 - Chip Select Setup

`pub fn ics(&mut self) -> ICS_W`[src]

Bits 24:26 - Inter-character Spacing

`pub fn cshold(&mut self) -> CSHOLD_W`[src]

Bits 28:30 - Chip Select Hold

`impl W<u32, Reg<u32, _CTRLX>>`[src]

`pub fn dbghalt(&mut self) -> DBGHALT_W`[src]

Bit 0 - Debug Halt

`pub fn ctsinv(&mut self) -> CTSINV_W`[src]

Bit 1 - CTS Pin Inversion

`pub fn ctsen(&mut self) -> CTSEN_W`[src]

Bit 2 - CTS Function Enabled

`pub fn rtsinv(&mut self) -> RTSINV_W`[src]

Bit 3 - RTS Pin Inversion

`impl W<u32, Reg<u32, _TIMECMP0>>`[src]

`pub fn tcmpval(&mut self) -> TCMPVAL_W`[src]

Bits 0:7 - Timer Comparator 0

`pub fn tstart(&mut self) -> TSTART_W`[src]

Bits 16:18 - Timer Start Source

`pub fn tstop(&mut self) -> TSTOP_W`[src]

Bits 20:22 - Source Used to Disable Comparator 0

`pub fn restarten(&mut self) -> RESTARTEN_W`[src]

Bit 24 - Restart Timer on TCMP0

`impl W<u32, Reg<u32, _TIMECMP1>>`[src]

`pub fn tcmpval(&mut self) -> TCMPVAL_W`[src]

Bits 0:7 - Timer Comparator 1

`pub fn tstart(&mut self) -> TSTART_W`[src]

Bits 16:18 - Timer Start Source

`pub fn tstop(&mut self) -> TSTOP_W`[src]

Bits 20:22 - Source Used to Disable Comparator 1

`pub fn restarten(&mut self) -> RESTARTEN_W`[src]

Bit 24 - Restart Timer on TCMP1

`impl W<u32, Reg<u32, _TIMECMP2>>`[src]

`pub fn tcmpval(&mut self) -> TCMPVAL_W`[src]

Bits 0:7 - Timer Comparator 2

`pub fn tstart(&mut self) -> TSTART_W`[src]

Bits 16:18 - Timer Start Source

`pub fn tstop(&mut self) -> TSTOP_W`[src]

Bits 20:22 - Source Used to Disable Comparator 2

`pub fn restarten(&mut self) -> RESTARTEN_W`[src]

Bit 24 - Restart Timer on TCMP2

`impl W<u32, Reg<u32, _ROUTEPEN>>`[src]

`pub fn rxpen(&mut self) -> RXPEN_W`[src]

Bit 0 - RX Pin Enable

`pub fn txpen(&mut self) -> TXPEN_W`[src]

Bit 1 - TX Pin Enable

`pub fn cspen(&mut self) -> CSPEN_W`[src]

Bit 2 - CS Pin Enable

`pub fn clkpen(&mut self) -> CLKPEN_W`[src]

Bit 3 - CLK Pin Enable

`pub fn ctspen(&mut self) -> CTSPEN_W`[src]

Bit 4 - CTS Pin Enable

`pub fn rtspen(&mut self) -> RTSPEN_W`[src]

Bit 5 - RTS Pin Enable

`impl W<u32, Reg<u32, _ROUTELOC0>>`[src]

`pub fn rxloc(&mut self) -> RXLOC_W`[src]

Bits 0:5 - I/O Location

`pub fn txloc(&mut self) -> TXLOC_W`[src]

Bits 8:13 - I/O Location

`pub fn csloc(&mut self) -> CSLOC_W`[src]

Bits 16:21 - I/O Location

`pub fn clkloc(&mut self) -> CLKLOC_W`[src]

Bits 24:29 - I/O Location

`impl W<u32, Reg<u32, _ROUTELOC1>>`[src]

`pub fn ctsloc(&mut self) -> CTSLOC_W`[src]

Bits 0:5 - I/O Location

`pub fn rtsloc(&mut self) -> RTSLOC_W`[src]

Bits 8:13 - I/O Location

`impl W<u32, Reg<u32, _CTRL>>`[src]

`pub fn sync(&mut self) -> SYNC_W`[src]

Bit 0 - USART Synchronous Mode

`pub fn loopbk(&mut self) -> LOOPBK_W`[src]

Bit 1 - Loopback Enable

`pub fn ccen(&mut self) -> CCEN_W`[src]

Bit 2 - Collision Check Enable

`pub fn mpm(&mut self) -> MPM_W`[src]

Bit 3 - Multi-Processor Mode

`pub fn mpab(&mut self) -> MPAB_W`[src]

Bit 4 - Multi-Processor Address-Bit

`pub fn ovs(&mut self) -> OVS_W`[src]

Bits 5:6 - Oversampling

`pub fn clkpol(&mut self) -> CLKPOL_W`[src]

Bit 8 - Clock Polarity

`pub fn clkpha(&mut self) -> CLKPHA_W`[src]

Bit 9 - Clock Edge for Setup/Sample

`pub fn msbf(&mut self) -> MSBF_W`[src]

Bit 10 - Most Significant Bit First

`pub fn csma(&mut self) -> CSMA_W`[src]

Bit 11 - Action on Slave-Select in Master Mode

`pub fn txbil(&mut self) -> TXBIL_W`[src]

Bit 12 - TX Buffer Interrupt Level

`pub fn rxinv(&mut self) -> RXINV_W`[src]

Bit 13 - Receiver Input Invert

`pub fn txinv(&mut self) -> TXINV_W`[src]

Bit 14 - Transmitter Output Invert

`pub fn csinv(&mut self) -> CSINV_W`[src]

Bit 15 - Chip Select Invert

`pub fn autocs(&mut self) -> AUTOCS_W`[src]

Bit 16 - Automatic Chip Select

`pub fn autotri(&mut self) -> AUTOTRI_W`[src]

Bit 17 - Automatic TX Tristate

`pub fn scmode(&mut self) -> SCMODE_W`[src]

Bit 18 - SmartCard Mode

`pub fn scretrans(&mut self) -> SCRETRANS_W`[src]

Bit 19 - SmartCard Retransmit

`pub fn skipperrf(&mut self) -> SKIPPERRF_W`[src]

Bit 20 - Skip Parity Error Frames

`pub fn bit8dv(&mut self) -> BIT8DV_W`[src]

Bit 21 - Bit 8 Default Value

`pub fn errsdma(&mut self) -> ERRSDMA_W`[src]

Bit 22 - Halt DMA on Error

`pub fn errsrx(&mut self) -> ERRSRX_W`[src]

Bit 23 - Disable RX on Error

`pub fn errstx(&mut self) -> ERRSTX_W`[src]

Bit 24 - Disable TX on Error

`pub fn sssearly(&mut self) -> SSSEARLY_W`[src]

Bit 25 - Synchronous Slave Setup Early

`pub fn byteswap(&mut self) -> BYTESWAP_W`[src]

Bit 28 - Byteswap in Double Accesses

`pub fn autotx(&mut self) -> AUTOTX_W`[src]

Bit 29 - Always Transmit When RX Not Full

`pub fn mvdis(&mut self) -> MVDIS_W`[src]

Bit 30 - Majority Vote Disable

`pub fn smsdelay(&mut self) -> SMSDELAY_W`[src]

Bit 31 - Synchronous Master Sample Delay

`impl W<u32, Reg<u32, _FRAME>>`[src]

`pub fn databits(&mut self) -> DATABITS_W`[src]

Bits 0:3 - Data-Bit Mode

`pub fn parity(&mut self) -> PARITY_W`[src]

Bits 8:9 - Parity-Bit Mode

`pub fn stopbits(&mut self) -> STOPBITS_W`[src]

Bits 12:13 - Stop-Bit Mode

`impl W<u32, Reg<u32, _TRIGCTRL>>`[src]

`pub fn rxten(&mut self) -> RXTEN_W`[src]

Bit 4 - Receive Trigger Enable

`pub fn txten(&mut self) -> TXTEN_W`[src]

Bit 5 - Transmit Trigger Enable

`pub fn autotxten(&mut self) -> AUTOTXTEN_W`[src]

Bit 6 - AUTOTX Trigger Enable

`pub fn txarx0en(&mut self) -> TXARX0EN_W`[src]

Bit 7 - Enable Transmit Trigger After RX End of Frame Plus TCMP0VAL

`pub fn txarx1en(&mut self) -> TXARX1EN_W`[src]

Bit 8 - Enable Transmit Trigger After RX End of Frame Plus TCMP1VAL

`pub fn txarx2en(&mut self) -> TXARX2EN_W`[src]

Bit 9 - Enable Transmit Trigger After RX End of Frame Plus TCMP2VAL

`pub fn rxatx0en(&mut self) -> RXATX0EN_W`[src]

Bit 10 - Enable Receive Trigger After TX End of Frame Plus TCMPVAL0 Baud-times

`pub fn rxatx1en(&mut self) -> RXATX1EN_W`[src]

Bit 11 - Enable Receive Trigger After TX End of Frame Plus TCMPVAL1 Baud-times

`pub fn rxatx2en(&mut self) -> RXATX2EN_W`[src]

Bit 12 - Enable Receive Trigger After TX End of Frame Plus TCMPVAL2 Baud-times

`pub fn tsel(&mut self) -> TSEL_W`[src]

Bits 16:19 - Trigger PRS Channel Select

`impl W<u32, Reg<u32, _CMD>>`[src]

`pub fn rxen(&mut self) -> RXEN_W`[src]

Bit 0 - Receiver Enable

`pub fn rxdis(&mut self) -> RXDIS_W`[src]

Bit 1 - Receiver Disable

`pub fn txen(&mut self) -> TXEN_W`[src]

Bit 2 - Transmitter Enable

`pub fn txdis(&mut self) -> TXDIS_W`[src]

Bit 3 - Transmitter Disable

`pub fn masteren(&mut self) -> MASTEREN_W`[src]

Bit 4 - Master Enable

`pub fn masterdis(&mut self) -> MASTERDIS_W`[src]

Bit 5 - Master Disable

`pub fn rxblocken(&mut self) -> RXBLOCKEN_W`[src]

Bit 6 - Receiver Block Enable

`pub fn rxblockdis(&mut self) -> RXBLOCKDIS_W`[src]

Bit 7 - Receiver Block Disable

`pub fn txtrien(&mut self) -> TXTRIEN_W`[src]

Bit 8 - Transmitter Tristate Enable

`pub fn txtridis(&mut self) -> TXTRIDIS_W`[src]

Bit 9 - Transmitter Tristate Disable

`pub fn cleartx(&mut self) -> CLEARTX_W`[src]

Bit 10 - Clear TX

`pub fn clearrx(&mut self) -> CLEARRX_W`[src]

Bit 11 - Clear RX

`impl W<u32, Reg<u32, _CLKDIV>>`[src]

`pub fn div(&mut self) -> DIV_W`[src]

Bits 3:22 - Fractional Clock Divider

`pub fn autobauden(&mut self) -> AUTOBAUDEN_W`[src]

Bit 31 - AUTOBAUD Detection Enable

`impl W<u32, Reg<u32, _TXDATAX>>`[src]

`pub fn txdatax(&mut self) -> TXDATAX_W`[src]

Bits 0:8 - TX Data

`pub fn ubrxat(&mut self) -> UBRXAT_W`[src]

Bit 11 - Unblock RX After Transmission

`pub fn txtriat(&mut self) -> TXTRIAT_W`[src]

Bit 12 - Set TXTRI After Transmission

`pub fn txbreak(&mut self) -> TXBREAK_W`[src]

Bit 13 - Transmit Data as Break

`pub fn txdisat(&mut self) -> TXDISAT_W`[src]

Bit 14 - Clear TXEN After Transmission

`pub fn rxenat(&mut self) -> RXENAT_W`[src]

Bit 15 - Enable RX After Transmission

`impl W<u32, Reg<u32, _TXDATA>>`[src]

`pub fn txdata(&mut self) -> TXDATA_W`[src]

Bits 0:7 - TX Data

`impl W<u32, Reg<u32, _TXDOUBLEX>>`[src]

`pub fn txdata0(&mut self) -> TXDATA0_W`[src]

Bits 0:8 - TX Data

`pub fn ubrxat0(&mut self) -> UBRXAT0_W`[src]

Bit 11 - Unblock RX After Transmission

`pub fn txtriat0(&mut self) -> TXTRIAT0_W`[src]

Bit 12 - Set TXTRI After Transmission

`pub fn txbreak0(&mut self) -> TXBREAK0_W`[src]

Bit 13 - Transmit Data as Break

`pub fn txdisat0(&mut self) -> TXDISAT0_W`[src]

Bit 14 - Clear TXEN After Transmission

`pub fn rxenat0(&mut self) -> RXENAT0_W`[src]

Bit 15 - Enable RX After Transmission

`pub fn txdata1(&mut self) -> TXDATA1_W`[src]

Bits 16:24 - TX Data

`pub fn ubrxat1(&mut self) -> UBRXAT1_W`[src]

Bit 27 - Unblock RX After Transmission

`pub fn txtriat1(&mut self) -> TXTRIAT1_W`[src]

Bit 28 - Set TXTRI After Transmission

`pub fn txbreak1(&mut self) -> TXBREAK1_W`[src]

Bit 29 - Transmit Data as Break

`pub fn txdisat1(&mut self) -> TXDISAT1_W`[src]

Bit 30 - Clear TXEN After Transmission

`pub fn rxenat1(&mut self) -> RXENAT1_W`[src]

Bit 31 - Enable RX After Transmission

`impl W<u32, Reg<u32, _TXDOUBLE>>`[src]

`pub fn txdata0(&mut self) -> TXDATA0_W`[src]

Bits 0:7 - TX Data

`pub fn txdata1(&mut self) -> TXDATA1_W`[src]

Bits 8:15 - TX Data

`impl W<u32, Reg<u32, _IFS>>`[src]

`pub fn txc(&mut self) -> TXC_W`[src]

Bit 0 - Set TXC Interrupt Flag

`pub fn rxfull(&mut self) -> RXFULL_W`[src]

Bit 3 - Set RXFULL Interrupt Flag

`pub fn rxof(&mut self) -> RXOF_W`[src]

Bit 4 - Set RXOF Interrupt Flag

`pub fn rxuf(&mut self) -> RXUF_W`[src]

Bit 5 - Set RXUF Interrupt Flag

`pub fn txof(&mut self) -> TXOF_W`[src]

Bit 6 - Set TXOF Interrupt Flag

`pub fn txuf(&mut self) -> TXUF_W`[src]

Bit 7 - Set TXUF Interrupt Flag

`pub fn perr(&mut self) -> PERR_W`[src]

Bit 8 - Set PERR Interrupt Flag

`pub fn ferr(&mut self) -> FERR_W`[src]

Bit 9 - Set FERR Interrupt Flag

`pub fn mpaf(&mut self) -> MPAF_W`[src]

Bit 10 - Set MPAF Interrupt Flag

`pub fn ssm(&mut self) -> SSM_W`[src]

Bit 11 - Set SSM Interrupt Flag

`pub fn ccf(&mut self) -> CCF_W`[src]

Bit 12 - Set CCF Interrupt Flag

`pub fn txidle(&mut self) -> TXIDLE_W`[src]

Bit 13 - Set TXIDLE Interrupt Flag

`pub fn tcmp0(&mut self) -> TCMP0_W`[src]

Bit 14 - Set TCMP0 Interrupt Flag

`pub fn tcmp1(&mut self) -> TCMP1_W`[src]

Bit 15 - Set TCMP1 Interrupt Flag

`pub fn tcmp2(&mut self) -> TCMP2_W`[src]

Bit 16 - Set TCMP2 Interrupt Flag

`impl W<u32, Reg<u32, _IFC>>`[src]

`pub fn txc(&mut self) -> TXC_W`[src]

Bit 0 - Clear TXC Interrupt Flag

`pub fn rxfull(&mut self) -> RXFULL_W`[src]

Bit 3 - Clear RXFULL Interrupt Flag

`pub fn rxof(&mut self) -> RXOF_W`[src]

Bit 4 - Clear RXOF Interrupt Flag

`pub fn rxuf(&mut self) -> RXUF_W`[src]

Bit 5 - Clear RXUF Interrupt Flag

`pub fn txof(&mut self) -> TXOF_W`[src]

Bit 6 - Clear TXOF Interrupt Flag

`pub fn txuf(&mut self) -> TXUF_W`[src]

Bit 7 - Clear TXUF Interrupt Flag

`pub fn perr(&mut self) -> PERR_W`[src]

Bit 8 - Clear PERR Interrupt Flag

`pub fn ferr(&mut self) -> FERR_W`[src]

Bit 9 - Clear FERR Interrupt Flag

`pub fn mpaf(&mut self) -> MPAF_W`[src]

Bit 10 - Clear MPAF Interrupt Flag

`pub fn ssm(&mut self) -> SSM_W`[src]

Bit 11 - Clear SSM Interrupt Flag

`pub fn ccf(&mut self) -> CCF_W`[src]

Bit 12 - Clear CCF Interrupt Flag

`pub fn txidle(&mut self) -> TXIDLE_W`[src]

Bit 13 - Clear TXIDLE Interrupt Flag

`pub fn tcmp0(&mut self) -> TCMP0_W`[src]

Bit 14 - Clear TCMP0 Interrupt Flag

`pub fn tcmp1(&mut self) -> TCMP1_W`[src]

Bit 15 - Clear TCMP1 Interrupt Flag

`pub fn tcmp2(&mut self) -> TCMP2_W`[src]

Bit 16 - Clear TCMP2 Interrupt Flag

`impl W<u32, Reg<u32, _IEN>>`[src]

`pub fn txc(&mut self) -> TXC_W`[src]

Bit 0 - TXC Interrupt Enable

`pub fn txbl(&mut self) -> TXBL_W`[src]

Bit 1 - TXBL Interrupt Enable

`pub fn rxdatav(&mut self) -> RXDATAV_W`[src]

Bit 2 - RXDATAV Interrupt Enable

`pub fn rxfull(&mut self) -> RXFULL_W`[src]

Bit 3 - RXFULL Interrupt Enable

`pub fn rxof(&mut self) -> RXOF_W`[src]

Bit 4 - RXOF Interrupt Enable

`pub fn rxuf(&mut self) -> RXUF_W`[src]

Bit 5 - RXUF Interrupt Enable

`pub fn txof(&mut self) -> TXOF_W`[src]

Bit 6 - TXOF Interrupt Enable

`pub fn txuf(&mut self) -> TXUF_W`[src]

Bit 7 - TXUF Interrupt Enable

`pub fn perr(&mut self) -> PERR_W`[src]

Bit 8 - PERR Interrupt Enable

`pub fn ferr(&mut self) -> FERR_W`[src]

Bit 9 - FERR Interrupt Enable

`pub fn mpaf(&mut self) -> MPAF_W`[src]

Bit 10 - MPAF Interrupt Enable

`pub fn ssm(&mut self) -> SSM_W`[src]

Bit 11 - SSM Interrupt Enable

`pub fn ccf(&mut self) -> CCF_W`[src]

Bit 12 - CCF Interrupt Enable

`pub fn txidle(&mut self) -> TXIDLE_W`[src]

Bit 13 - TXIDLE Interrupt Enable

`pub fn tcmp0(&mut self) -> TCMP0_W`[src]

Bit 14 - TCMP0 Interrupt Enable

`pub fn tcmp1(&mut self) -> TCMP1_W`[src]

Bit 15 - TCMP1 Interrupt Enable

`pub fn tcmp2(&mut self) -> TCMP2_W`[src]

Bit 16 - TCMP2 Interrupt Enable

`impl W<u32, Reg<u32, _IRCTRL>>`[src]

`pub fn iren(&mut self) -> IREN_W`[src]

Bit 0 - Enable IrDA Module

`pub fn irpw(&mut self) -> IRPW_W`[src]

Bits 1:2 - IrDA TX Pulse Width

`pub fn irfilt(&mut self) -> IRFILT_W`[src]

Bit 3 - IrDA RX Filter

`pub fn irprsen(&mut self) -> IRPRSEN_W`[src]

Bit 7 - IrDA PRS Channel Enable

`pub fn irprssel(&mut self) -> IRPRSSEL_W`[src]

Bits 8:11 - IrDA PRS Channel Select

`impl W<u32, Reg<u32, _INPUT>>`[src]

`pub fn rxprssel(&mut self) -> RXPRSSEL_W`[src]

Bits 0:3 - RX PRS Channel Select

`pub fn rxprs(&mut self) -> RXPRS_W`[src]

Bit 7 - PRS RX Enable

`pub fn clkprssel(&mut self) -> CLKPRSSEL_W`[src]

Bits 8:11 - CLK PRS Channel Select

`pub fn clkprs(&mut self) -> CLKPRS_W`[src]

Bit 15 - PRS CLK Enable

`impl W<u32, Reg<u32, _I2SCTRL>>`[src]

`pub fn en(&mut self) -> EN_W`[src]

Bit 0 - Enable I2S Mode

`pub fn mono(&mut self) -> MONO_W`[src]

Bit 1 - Stero or Mono

`pub fn justify(&mut self) -> JUSTIFY_W`[src]

Bit 2 - Justification of I2S Data

`pub fn dmasplit(&mut self) -> DMASPLIT_W`[src]

Bit 3 - Separate DMA Request for Left/Right Data

`pub fn delay(&mut self) -> DELAY_W`[src]

Bit 4 - Delay on I2S Data

`pub fn format(&mut self) -> FORMAT_W`[src]

Bits 8:10 - I2S Word Format

`impl W<u32, Reg<u32, _TIMING>>`[src]

`pub fn txdelay(&mut self) -> TXDELAY_W`[src]

Bits 16:18 - TX Frame Start Delay

`pub fn cssetup(&mut self) -> CSSETUP_W`[src]

Bits 20:22 - Chip Select Setup

`pub fn ics(&mut self) -> ICS_W`[src]

Bits 24:26 - Inter-character Spacing

`pub fn cshold(&mut self) -> CSHOLD_W`[src]

Bits 28:30 - Chip Select Hold

`impl W<u32, Reg<u32, _CTRLX>>`[src]

`pub fn dbghalt(&mut self) -> DBGHALT_W`[src]

Bit 0 - Debug Halt

`pub fn ctsinv(&mut self) -> CTSINV_W`[src]

Bit 1 - CTS Pin Inversion

`pub fn ctsen(&mut self) -> CTSEN_W`[src]

Bit 2 - CTS Function Enabled

`pub fn rtsinv(&mut self) -> RTSINV_W`[src]

Bit 3 - RTS Pin Inversion

`impl W<u32, Reg<u32, _TIMECMP0>>`[src]

`pub fn tcmpval(&mut self) -> TCMPVAL_W`[src]

Bits 0:7 - Timer Comparator 0

`pub fn tstart(&mut self) -> TSTART_W`[src]

Bits 16:18 - Timer Start Source

`pub fn tstop(&mut self) -> TSTOP_W`[src]

Bits 20:22 - Source Used to Disable Comparator 0

`pub fn restarten(&mut self) -> RESTARTEN_W`[src]

Bit 24 - Restart Timer on TCMP0

`impl W<u32, Reg<u32, _TIMECMP1>>`[src]

`pub fn tcmpval(&mut self) -> TCMPVAL_W`[src]

Bits 0:7 - Timer Comparator 1

`pub fn tstart(&mut self) -> TSTART_W`[src]

Bits 16:18 - Timer Start Source

`pub fn tstop(&mut self) -> TSTOP_W`[src]

Bits 20:22 - Source Used to Disable Comparator 1

`pub fn restarten(&mut self) -> RESTARTEN_W`[src]

Bit 24 - Restart Timer on TCMP1

`impl W<u32, Reg<u32, _TIMECMP2>>`[src]

`pub fn tcmpval(&mut self) -> TCMPVAL_W`[src]

Bits 0:7 - Timer Comparator 2

`pub fn tstart(&mut self) -> TSTART_W`[src]

Bits 16:18 - Timer Start Source

`pub fn tstop(&mut self) -> TSTOP_W`[src]

Bits 20:22 - Source Used to Disable Comparator 2

`pub fn restarten(&mut self) -> RESTARTEN_W`[src]

Bit 24 - Restart Timer on TCMP2

`impl W<u32, Reg<u32, _ROUTEPEN>>`[src]

`pub fn rxpen(&mut self) -> RXPEN_W`[src]

Bit 0 - RX Pin Enable

`pub fn txpen(&mut self) -> TXPEN_W`[src]

Bit 1 - TX Pin Enable

`pub fn cspen(&mut self) -> CSPEN_W`[src]

Bit 2 - CS Pin Enable

`pub fn clkpen(&mut self) -> CLKPEN_W`[src]

Bit 3 - CLK Pin Enable

`pub fn ctspen(&mut self) -> CTSPEN_W`[src]

Bit 4 - CTS Pin Enable

`pub fn rtspen(&mut self) -> RTSPEN_W`[src]

Bit 5 - RTS Pin Enable

`impl W<u32, Reg<u32, _ROUTELOC0>>`[src]

`pub fn rxloc(&mut self) -> RXLOC_W`[src]

Bits 0:5 - I/O Location

`pub fn txloc(&mut self) -> TXLOC_W`[src]

Bits 8:13 - I/O Location

`pub fn csloc(&mut self) -> CSLOC_W`[src]

Bits 16:21 - I/O Location

`pub fn clkloc(&mut self) -> CLKLOC_W`[src]

Bits 24:29 - I/O Location

`impl W<u32, Reg<u32, _ROUTELOC1>>`[src]

`pub fn ctsloc(&mut self) -> CTSLOC_W`[src]

Bits 0:5 - I/O Location

`pub fn rtsloc(&mut self) -> RTSLOC_W`[src]

Bits 8:13 - I/O Location

`impl W<u32, Reg<u32, _CTRL>>`[src]

`pub fn autotri(&mut self) -> AUTOTRI_W`[src]

Bit 0 - Automatic Transmitter Tristate

`pub fn databits(&mut self) -> DATABITS_W`[src]

Bit 1 - Data-Bit Mode

`pub fn parity(&mut self) -> PARITY_W`[src]

Bits 2:3 - Parity-Bit Mode

`pub fn stopbits(&mut self) -> STOPBITS_W`[src]

Bit 4 - Stop-Bit Mode

`pub fn inv(&mut self) -> INV_W`[src]

Bit 5 - Invert Input and Output

`pub fn errsdma(&mut self) -> ERRSDMA_W`[src]

Bit 6 - Clear RX DMA on Error

`pub fn loopbk(&mut self) -> LOOPBK_W`[src]

Bit 7 - Loopback Enable

`pub fn sfubrx(&mut self) -> SFUBRX_W`[src]

Bit 8 - Start-Frame UnBlock RX

`pub fn mpm(&mut self) -> MPM_W`[src]

Bit 9 - Multi-Processor Mode

`pub fn mpab(&mut self) -> MPAB_W`[src]

Bit 10 - Multi-Processor Address-Bit

`pub fn bit8dv(&mut self) -> BIT8DV_W`[src]

Bit 11 - Bit 8 Default Value

`pub fn rxdmawu(&mut self) -> RXDMAWU_W`[src]

Bit 12 - RX DMA Wakeup

`pub fn txdmawu(&mut self) -> TXDMAWU_W`[src]

Bit 13 - TX DMA Wakeup

`pub fn txdelay(&mut self) -> TXDELAY_W`[src]

Bits 14:15 - TX Delay Transmission

`impl W<u32, Reg<u32, _CMD>>`[src]

`pub fn rxen(&mut self) -> RXEN_W`[src]

Bit 0 - Receiver Enable

`pub fn rxdis(&mut self) -> RXDIS_W`[src]

Bit 1 - Receiver Disable

`pub fn txen(&mut self) -> TXEN_W`[src]

Bit 2 - Transmitter Enable

`pub fn txdis(&mut self) -> TXDIS_W`[src]

Bit 3 - Transmitter Disable

`pub fn rxblocken(&mut self) -> RXBLOCKEN_W`[src]

Bit 4 - Receiver Block Enable

`pub fn rxblockdis(&mut self) -> RXBLOCKDIS_W`[src]

Bit 5 - Receiver Block Disable

`pub fn cleartx(&mut self) -> CLEARTX_W`[src]

Bit 6 - Clear TX

`pub fn clearrx(&mut self) -> CLEARRX_W`[src]

Bit 7 - Clear RX

`impl W<u32, Reg<u32, _CLKDIV>>`[src]

`pub fn div(&mut self) -> DIV_W`[src]

Bits 3:16 - Fractional Clock Divider

`impl W<u32, Reg<u32, _STARTFRAME>>`[src]

`pub fn startframe(&mut self) -> STARTFRAME_W`[src]

Bits 0:8 - Start Frame

`impl W<u32, Reg<u32, _SIGFRAME>>`[src]

`pub fn sigframe(&mut self) -> SIGFRAME_W`[src]

Bits 0:8 - Signal Frame

`impl W<u32, Reg<u32, _TXDATAX>>`[src]

`pub fn txdata(&mut self) -> TXDATA_W`[src]

Bits 0:8 - TX Data

`pub fn txbreak(&mut self) -> TXBREAK_W`[src]

Bit 13 - Transmit Data as Break

`pub fn txdisat(&mut self) -> TXDISAT_W`[src]

Bit 14 - Disable TX After Transmission

`pub fn rxenat(&mut self) -> RXENAT_W`[src]

Bit 15 - Enable RX After Transmission

`impl W<u32, Reg<u32, _TXDATA>>`[src]

`pub fn txdata(&mut self) -> TXDATA_W`[src]

Bits 0:7 - TX Data

`impl W<u32, Reg<u32, _IFS>>`[src]

`pub fn txc(&mut self) -> TXC_W`[src]

Bit 0 - Set TXC Interrupt Flag

`pub fn rxof(&mut self) -> RXOF_W`[src]

Bit 3 - Set RXOF Interrupt Flag

`pub fn rxuf(&mut self) -> RXUF_W`[src]

Bit 4 - Set RXUF Interrupt Flag

`pub fn txof(&mut self) -> TXOF_W`[src]

Bit 5 - Set TXOF Interrupt Flag

`pub fn perr(&mut self) -> PERR_W`[src]

Bit 6 - Set PERR Interrupt Flag

`pub fn ferr(&mut self) -> FERR_W`[src]

Bit 7 - Set FERR Interrupt Flag

`pub fn mpaf(&mut self) -> MPAF_W`[src]

Bit 8 - Set MPAF Interrupt Flag

`pub fn startf(&mut self) -> STARTF_W`[src]

Bit 9 - Set STARTF Interrupt Flag

`pub fn sigf(&mut self) -> SIGF_W`[src]

Bit 10 - Set SIGF Interrupt Flag

`impl W<u32, Reg<u32, _IFC>>`[src]

`pub fn txc(&mut self) -> TXC_W`[src]

Bit 0 - Clear TXC Interrupt Flag

`pub fn rxof(&mut self) -> RXOF_W`[src]

Bit 3 - Clear RXOF Interrupt Flag

`pub fn rxuf(&mut self) -> RXUF_W`[src]

Bit 4 - Clear RXUF Interrupt Flag

`pub fn txof(&mut self) -> TXOF_W`[src]

Bit 5 - Clear TXOF Interrupt Flag

`pub fn perr(&mut self) -> PERR_W`[src]

Bit 6 - Clear PERR Interrupt Flag

`pub fn ferr(&mut self) -> FERR_W`[src]

Bit 7 - Clear FERR Interrupt Flag

`pub fn mpaf(&mut self) -> MPAF_W`[src]

Bit 8 - Clear MPAF Interrupt Flag

`pub fn startf(&mut self) -> STARTF_W`[src]

Bit 9 - Clear STARTF Interrupt Flag

`pub fn sigf(&mut self) -> SIGF_W`[src]

Bit 10 - Clear SIGF Interrupt Flag

`impl W<u32, Reg<u32, _IEN>>`[src]

`pub fn txc(&mut self) -> TXC_W`[src]

Bit 0 - TXC Interrupt Enable

`pub fn txbl(&mut self) -> TXBL_W`[src]

Bit 1 - TXBL Interrupt Enable

`pub fn rxdatav(&mut self) -> RXDATAV_W`[src]

Bit 2 - RXDATAV Interrupt Enable

`pub fn rxof(&mut self) -> RXOF_W`[src]

Bit 3 - RXOF Interrupt Enable

`pub fn rxuf(&mut self) -> RXUF_W`[src]

Bit 4 - RXUF Interrupt Enable

`pub fn txof(&mut self) -> TXOF_W`[src]

Bit 5 - TXOF Interrupt Enable

`pub fn perr(&mut self) -> PERR_W`[src]

Bit 6 - PERR Interrupt Enable

`pub fn ferr(&mut self) -> FERR_W`[src]

Bit 7 - FERR Interrupt Enable

`pub fn mpaf(&mut self) -> MPAF_W`[src]

Bit 8 - MPAF Interrupt Enable

`pub fn startf(&mut self) -> STARTF_W`[src]

Bit 9 - STARTF Interrupt Enable

`pub fn sigf(&mut self) -> SIGF_W`[src]

Bit 10 - SIGF Interrupt Enable

`impl W<u32, Reg<u32, _PULSECTRL>>`[src]

`pub fn pulsew(&mut self) -> PULSEW_W`[src]

Bits 0:3 - Pulse Width

`pub fn pulseen(&mut self) -> PULSEEN_W`[src]

Bit 4 - Pulse Generator/Extender Enable

`pub fn pulsefilt(&mut self) -> PULSEFILT_W`[src]

Bit 5 - Pulse Filter

`impl W<u32, Reg<u32, _FREEZE>>`[src]

`pub fn regfreeze(&mut self) -> REGFREEZE_W`[src]

Bit 0 - Register Update Freeze

`impl W<u32, Reg<u32, _ROUTEPEN>>`[src]

`pub fn rxpen(&mut self) -> RXPEN_W`[src]

Bit 0 - RX Pin Enable

`pub fn txpen(&mut self) -> TXPEN_W`[src]

Bit 1 - TX Pin Enable

`impl W<u32, Reg<u32, _ROUTELOC0>>`[src]

`pub fn rxloc(&mut self) -> RXLOC_W`[src]

Bits 0:5 - I/O Location

`pub fn txloc(&mut self) -> TXLOC_W`[src]

Bits 8:13 - I/O Location

`impl W<u32, Reg<u32, _INPUT>>`[src]

`pub fn rxprssel(&mut self) -> RXPRSSEL_W`[src]

Bits 0:3 - RX PRS Channel Select

`pub fn rxprs(&mut self) -> RXPRS_W`[src]

Bit 5 - PRS RX Enable

`impl W<u32, Reg<u32, _CTRL>>`[src]

`pub fn repmode(&mut self) -> REPMODE_W`[src]

Bits 0:1 - Repeat Mode

`pub fn ufoa0(&mut self) -> UFOA0_W`[src]

Bits 2:3 - Underflow Output Action 0

`pub fn ufoa1(&mut self) -> UFOA1_W`[src]

Bits 4:5 - Underflow Output Action 1

`pub fn opol0(&mut self) -> OPOL0_W`[src]

Bit 6 - Output 0 Polarity

`pub fn opol1(&mut self) -> OPOL1_W`[src]

Bit 7 - Output 1 Polarity

`pub fn buftop(&mut self) -> BUFTOP_W`[src]

Bit 8 - Buffered Top

`pub fn comp0top(&mut self) -> COMP0TOP_W`[src]

Bit 9 - Compare Value 0 is Top Value

`pub fn debugrun(&mut self) -> DEBUGRUN_W`[src]

Bit 12 - Debug Mode Run Enable

`impl W<u32, Reg<u32, _CMD>>`[src]

`pub fn start(&mut self) -> START_W`[src]

Bit 0 - Start LETIMER

`pub fn stop(&mut self) -> STOP_W`[src]

Bit 1 - Stop LETIMER

`pub fn clear(&mut self) -> CLEAR_W`[src]

Bit 2 - Clear LETIMER

`pub fn cto0(&mut self) -> CTO0_W`[src]

Bit 3 - Clear Toggle Output 0

`pub fn cto1(&mut self) -> CTO1_W`[src]

Bit 4 - Clear Toggle Output 1

`impl W<u32, Reg<u32, _CNT>>`[src]

`pub fn cnt(&mut self) -> CNT_W`[src]

Bits 0:15 - Counter Value

`impl W<u32, Reg<u32, _COMP0>>`[src]

`pub fn comp0(&mut self) -> COMP0_W`[src]

Bits 0:15 - Compare Value 0

`impl W<u32, Reg<u32, _COMP1>>`[src]

`pub fn comp1(&mut self) -> COMP1_W`[src]

Bits 0:15 - Compare Value 1

`impl W<u32, Reg<u32, _REP0>>`[src]

`pub fn rep0(&mut self) -> REP0_W`[src]

Bits 0:7 - Repeat Counter 0

`impl W<u32, Reg<u32, _REP1>>`[src]

`pub fn rep1(&mut self) -> REP1_W`[src]

Bits 0:7 - Repeat Counter 1

`impl W<u32, Reg<u32, _IFS>>`[src]

`pub fn comp0(&mut self) -> COMP0_W`[src]

Bit 0 - Set COMP0 Interrupt Flag

`pub fn comp1(&mut self) -> COMP1_W`[src]

Bit 1 - Set COMP1 Interrupt Flag

`pub fn uf(&mut self) -> UF_W`[src]

Bit 2 - Set UF Interrupt Flag

`pub fn rep0(&mut self) -> REP0_W`[src]

Bit 3 - Set REP0 Interrupt Flag

`pub fn rep1(&mut self) -> REP1_W`[src]

Bit 4 - Set REP1 Interrupt Flag

`impl W<u32, Reg<u32, _IFC>>`[src]

`pub fn comp0(&mut self) -> COMP0_W`[src]

Bit 0 - Clear COMP0 Interrupt Flag

`pub fn comp1(&mut self) -> COMP1_W`[src]

Bit 1 - Clear COMP1 Interrupt Flag

`pub fn uf(&mut self) -> UF_W`[src]

Bit 2 - Clear UF Interrupt Flag

`pub fn rep0(&mut self) -> REP0_W`[src]

Bit 3 - Clear REP0 Interrupt Flag

`pub fn rep1(&mut self) -> REP1_W`[src]

Bit 4 - Clear REP1 Interrupt Flag

`impl W<u32, Reg<u32, _IEN>>`[src]

`pub fn comp0(&mut self) -> COMP0_W`[src]

Bit 0 - COMP0 Interrupt Enable

`pub fn comp1(&mut self) -> COMP1_W`[src]

Bit 1 - COMP1 Interrupt Enable

`pub fn uf(&mut self) -> UF_W`[src]

Bit 2 - UF Interrupt Enable

`pub fn rep0(&mut self) -> REP0_W`[src]

Bit 3 - REP0 Interrupt Enable

`pub fn rep1(&mut self) -> REP1_W`[src]

Bit 4 - REP1 Interrupt Enable

`impl W<u32, Reg<u32, _ROUTEPEN>>`[src]

`pub fn out0pen(&mut self) -> OUT0PEN_W`[src]

Bit 0 - Output 0 Pin Enable

`pub fn out1pen(&mut self) -> OUT1PEN_W`[src]

Bit 1 - Output 1 Pin Enable

`impl W<u32, Reg<u32, _ROUTELOC0>>`[src]

`pub fn out0loc(&mut self) -> OUT0LOC_W`[src]

Bits 0:5 - I/O Location

`pub fn out1loc(&mut self) -> OUT1LOC_W`[src]

Bits 8:13 - I/O Location

`impl W<u32, Reg<u32, _PRSSEL>>`[src]

`pub fn prsstartsel(&mut self) -> PRSSTARTSEL_W`[src]

Bits 0:3 - PRS Start Select

`pub fn prsstopsel(&mut self) -> PRSSTOPSEL_W`[src]

Bits 6:9 - PRS Stop Select

`pub fn prsclearsel(&mut self) -> PRSCLEARSEL_W`[src]

Bits 12:15 - PRS Clear Select

`pub fn prsstartmode(&mut self) -> PRSSTARTMODE_W`[src]

Bits 18:19 - PRS Start Mode

`pub fn prsstopmode(&mut self) -> PRSSTOPMODE_W`[src]

Bits 22:23 - PRS Stop Mode

`pub fn prsclearmode(&mut self) -> PRSCLEARMODE_W`[src]

Bits 26:27 - PRS Clear Mode

`impl W<u32, Reg<u32, _CTRL>>`[src]

`pub fn en(&mut self) -> EN_W`[src]

Bit 0 - Enable CRYOTIMER

`pub fn debugrun(&mut self) -> DEBUGRUN_W`[src]

Bit 1 - Debug Mode Run Enable

`pub fn oscsel(&mut self) -> OSCSEL_W`[src]

Bits 2:3 - Select Low Frequency Oscillator

`pub fn presc(&mut self) -> PRESC_W`[src]

Bits 5:7 - Prescaler Setting

`impl W<u32, Reg<u32, _PERIODSEL>>`[src]

`pub fn periodsel(&mut self) -> PERIODSEL_W`[src]

Bits 0:5 - Interrupts/Wakeup Events Period Setting

`impl W<u32, Reg<u32, _EM4WUEN>>`[src]

`pub fn em4wu(&mut self) -> EM4WU_W`[src]

Bit 0 - EM4 Wake-up Enable

`impl W<u32, Reg<u32, _IFS>>`[src]

`pub fn period(&mut self) -> PERIOD_W`[src]

Bit 0 - Set PERIOD Interrupt Flag

`impl W<u32, Reg<u32, _IFC>>`[src]

`pub fn period(&mut self) -> PERIOD_W`[src]

Bit 0 - Clear PERIOD Interrupt Flag

`impl W<u32, Reg<u32, _IEN>>`[src]

`pub fn period(&mut self) -> PERIOD_W`[src]

Bit 0 - PERIOD Interrupt Enable

`impl W<u32, Reg<u32, _CTRL>>`[src]

`pub fn mode(&mut self) -> MODE_W`[src]

Bits 0:2 - Mode Select

`pub fn filt(&mut self) -> FILT_W`[src]

Bit 3 - Enable Digital Pulse Width Filter

`pub fn rsten(&mut self) -> RSTEN_W`[src]

Bit 4 - Enable PCNT Clock Domain Reset

`pub fn cntrsten(&mut self) -> CNTRSTEN_W`[src]

Bit 5 - Enable CNT Reset

`pub fn auxcntrsten(&mut self) -> AUXCNTRSTEN_W`[src]

Bit 6 - Enable AUXCNT Reset

`pub fn debughalt(&mut self) -> DEBUGHALT_W`[src]

Bit 7 - Debug Mode Halt Enable

`pub fn hyst(&mut self) -> HYST_W`[src]

Bit 8 - Enable Hysteresis

`pub fn s1cdir(&mut self) -> S1CDIR_W`[src]

Bit 9 - Count Direction Determined By S1

`pub fn cntev(&mut self) -> CNTEV_W`[src]

Bits 10:11 - Controls When the Counter Counts

`pub fn auxcntev(&mut self) -> AUXCNTEV_W`[src]

Bits 12:13 - Controls When the Auxiliary Counter Counts

`pub fn cntdir(&mut self) -> CNTDIR_W`[src]

Bit 14 - Non-Quadrature Mode Counter Direction Control

`pub fn edge(&mut self) -> EDGE_W`[src]

Bit 15 - Edge Select

`pub fn tccmode(&mut self) -> TCCMODE_W`[src]

Bits 16:17 - Sets the Mode for Triggered Compare and Clear

`pub fn tccpresc(&mut self) -> TCCPRESC_W`[src]

Bits 19:20 - Set the LFA Prescaler for Triggered Compare and Clear

`pub fn tcccomp(&mut self) -> TCCCOMP_W`[src]

Bits 22:23 - Triggered Compare and Clear Compare Mode

`pub fn prsgateen(&mut self) -> PRSGATEEN_W`[src]

Bit 24 - PRS Gate Enable

`pub fn tccprspol(&mut self) -> TCCPRSPOL_W`[src]

Bit 25 - TCC PRS Polarity Select

`pub fn tccprssel(&mut self) -> TCCPRSSEL_W`[src]

Bits 26:29 - TCC PRS Channel Select

`pub fn topbhfsel(&mut self) -> TOPBHFSEL_W`[src]

Bit 31 - TOPB High Frequency Value Select

`impl W<u32, Reg<u32, _CMD>>`[src]

`pub fn lcntim(&mut self) -> LCNTIM_W`[src]

Bit 0 - Load CNT Immediately

`pub fn ltopbim(&mut self) -> LTOPBIM_W`[src]

Bit 1 - Load TOPB Immediately

`impl W<u32, Reg<u32, _TOPB>>`[src]

`pub fn topb(&mut self) -> TOPB_W`[src]

Bits 0:15 - Counter Top Buffer

`impl W<u32, Reg<u32, _IFS>>`[src]

`pub fn uf(&mut self) -> UF_W`[src]

Bit 0 - Set UF Interrupt Flag

`pub fn of(&mut self) -> OF_W`[src]

Bit 1 - Set OF Interrupt Flag

`pub fn dircng(&mut self) -> DIRCNG_W`[src]

Bit 2 - Set DIRCNG Interrupt Flag

`pub fn auxof(&mut self) -> AUXOF_W`[src]

Bit 3 - Set AUXOF Interrupt Flag

`pub fn tcc(&mut self) -> TCC_W`[src]

Bit 4 - Set TCC Interrupt Flag

`pub fn oqsterr(&mut self) -> OQSTERR_W`[src]

Bit 5 - Set OQSTERR Interrupt Flag

`impl W<u32, Reg<u32, _IFC>>`[src]

`pub fn uf(&mut self) -> UF_W`[src]

Bit 0 - Clear UF Interrupt Flag

`pub fn of(&mut self) -> OF_W`[src]

Bit 1 - Clear OF Interrupt Flag

`pub fn dircng(&mut self) -> DIRCNG_W`[src]

Bit 2 - Clear DIRCNG Interrupt Flag

`pub fn auxof(&mut self) -> AUXOF_W`[src]

Bit 3 - Clear AUXOF Interrupt Flag

`pub fn tcc(&mut self) -> TCC_W`[src]

Bit 4 - Clear TCC Interrupt Flag

`pub fn oqsterr(&mut self) -> OQSTERR_W`[src]

Bit 5 - Clear OQSTERR Interrupt Flag

`impl W<u32, Reg<u32, _IEN>>`[src]

`pub fn uf(&mut self) -> UF_W`[src]

Bit 0 - UF Interrupt Enable

`pub fn of(&mut self) -> OF_W`[src]

Bit 1 - OF Interrupt Enable

`pub fn dircng(&mut self) -> DIRCNG_W`[src]

Bit 2 - DIRCNG Interrupt Enable

`pub fn auxof(&mut self) -> AUXOF_W`[src]

Bit 3 - AUXOF Interrupt Enable

`pub fn tcc(&mut self) -> TCC_W`[src]

Bit 4 - TCC Interrupt Enable

`pub fn oqsterr(&mut self) -> OQSTERR_W`[src]

Bit 5 - OQSTERR Interrupt Enable

`impl W<u32, Reg<u32, _ROUTELOC0>>`[src]

`pub fn s0inloc(&mut self) -> S0INLOC_W`[src]

Bits 0:5 - I/O Location

`pub fn s1inloc(&mut self) -> S1INLOC_W`[src]

Bits 8:13 - I/O Location

`impl W<u32, Reg<u32, _FREEZE>>`[src]

`pub fn regfreeze(&mut self) -> REGFREEZE_W`[src]

Bit 0 - Register Update Freeze

`impl W<u32, Reg<u32, _INPUT>>`[src]

`pub fn s0prssel(&mut self) -> S0PRSSEL_W`[src]

Bits 0:3 - S0IN PRS Channel Select

`pub fn s0prsen(&mut self) -> S0PRSEN_W`[src]

Bit 5 - S0IN PRS Enable

`pub fn s1prssel(&mut self) -> S1PRSSEL_W`[src]

Bits 6:9 - S1IN PRS Channel Select

`pub fn s1prsen(&mut self) -> S1PRSEN_W`[src]

Bit 11 - S1IN PRS Enable

`impl W<u32, Reg<u32, _OVSCFG>>`[src]

`pub fn filtlen(&mut self) -> FILTLEN_W`[src]

Bits 0:7 - Configure Filter Length for Inputs S0IN and S1IN

`pub fn flutterrm(&mut self) -> FLUTTERRM_W`[src]

Bit 12 - Flutter Remove

`impl W<u32, Reg<u32, _CTRL>>`[src]

`pub fn en(&mut self) -> EN_W`[src]

Bit 0 - I2C Enable

`pub fn slave(&mut self) -> SLAVE_W`[src]

Bit 1 - Addressable as Slave

`pub fn autoack(&mut self) -> AUTOACK_W`[src]

Bit 2 - Automatic Acknowledge

`pub fn autose(&mut self) -> AUTOSE_W`[src]

Bit 3 - Automatic STOP When Empty

`pub fn autosn(&mut self) -> AUTOSN_W`[src]

Bit 4 - Automatic STOP on NACK

`pub fn arbdis(&mut self) -> ARBDIS_W`[src]

Bit 5 - Arbitration Disable

`pub fn gcamen(&mut self) -> GCAMEN_W`[src]

Bit 6 - General Call Address Match Enable

`pub fn txbil(&mut self) -> TXBIL_W`[src]

Bit 7 - TX Buffer Interrupt Level

`pub fn clhr(&mut self) -> CLHR_W`[src]

Bits 8:9 - Clock Low High Ratio

`pub fn bito(&mut self) -> BITO_W`[src]

Bits 12:13 - Bus Idle Timeout

`pub fn gibito(&mut self) -> GIBITO_W`[src]

Bit 15 - Go Idle on Bus Idle Timeout

`pub fn clto(&mut self) -> CLTO_W`[src]

Bits 16:18 - Clock Low Timeout

`impl W<u32, Reg<u32, _CMD>>`[src]

`pub fn start(&mut self) -> START_W`[src]

Bit 0 - Send Start Condition

`pub fn stop(&mut self) -> STOP_W`[src]

Bit 1 - Send Stop Condition

`pub fn ack(&mut self) -> ACK_W`[src]

Bit 2 - Send ACK

`pub fn nack(&mut self) -> NACK_W`[src]

Bit 3 - Send NACK

`pub fn cont(&mut self) -> CONT_W`[src]

Bit 4 - Continue Transmission

`pub fn abort(&mut self) -> ABORT_W`[src]

Bit 5 - Abort Transmission

`pub fn cleartx(&mut self) -> CLEARTX_W`[src]

Bit 6 - Clear TX

`pub fn clearpc(&mut self) -> CLEARPC_W`[src]

Bit 7 - Clear Pending Commands

`impl W<u32, Reg<u32, _CLKDIV>>`[src]

`pub fn div(&mut self) -> DIV_W`[src]

Bits 0:8 - Clock Divider

`impl W<u32, Reg<u32, _SADDR>>`[src]

`pub fn addr(&mut self) -> ADDR_W`[src]

Bits 1:7 - Slave Address

`impl W<u32, Reg<u32, _SADDRMASK>>`[src]

`pub fn mask(&mut self) -> MASK_W`[src]

Bits 1:7 - Slave Address Mask

`impl W<u32, Reg<u32, _TXDATA>>`[src]

`pub fn txdata(&mut self) -> TXDATA_W`[src]

Bits 0:7 - TX Data

`impl W<u32, Reg<u32, _TXDOUBLE>>`[src]

`pub fn txdata0(&mut self) -> TXDATA0_W`[src]

Bits 0:7 - TX Data

`pub fn txdata1(&mut self) -> TXDATA1_W`[src]

Bits 8:15 - TX Data

`impl W<u32, Reg<u32, _IFS>>`[src]

`pub fn start(&mut self) -> START_W`[src]

Bit 0 - Set START Interrupt Flag

`pub fn rstart(&mut self) -> RSTART_W`[src]

Bit 1 - Set RSTART Interrupt Flag

`pub fn addr(&mut self) -> ADDR_W`[src]

Bit 2 - Set ADDR Interrupt Flag

`pub fn txc(&mut self) -> TXC_W`[src]

Bit 3 - Set TXC Interrupt Flag

`pub fn ack(&mut self) -> ACK_W`[src]

Bit 6 - Set ACK Interrupt Flag

`pub fn nack(&mut self) -> NACK_W`[src]

Bit 7 - Set NACK Interrupt Flag

`pub fn mstop(&mut self) -> MSTOP_W`[src]

Bit 8 - Set MSTOP Interrupt Flag

`pub fn arblost(&mut self) -> ARBLOST_W`[src]

Bit 9 - Set ARBLOST Interrupt Flag

`pub fn buserr(&mut self) -> BUSERR_W`[src]

Bit 10 - Set BUSERR Interrupt Flag

`pub fn bushold(&mut self) -> BUSHOLD_W`[src]

Bit 11 - Set BUSHOLD Interrupt Flag

`pub fn txof(&mut self) -> TXOF_W`[src]

Bit 12 - Set TXOF Interrupt Flag

`pub fn rxuf(&mut self) -> RXUF_W`[src]

Bit 13 - Set RXUF Interrupt Flag

`pub fn bito(&mut self) -> BITO_W`[src]

Bit 14 - Set BITO Interrupt Flag

`pub fn clto(&mut self) -> CLTO_W`[src]

Bit 15 - Set CLTO Interrupt Flag

`pub fn sstop(&mut self) -> SSTOP_W`[src]

Bit 16 - Set SSTOP Interrupt Flag

`pub fn rxfull(&mut self) -> RXFULL_W`[src]

Bit 17 - Set RXFULL Interrupt Flag

`pub fn clerr(&mut self) -> CLERR_W`[src]

Bit 18 - Set CLERR Interrupt Flag

`impl W<u32, Reg<u32, _IFC>>`[src]

`pub fn start(&mut self) -> START_W`[src]

Bit 0 - Clear START Interrupt Flag

`pub fn rstart(&mut self) -> RSTART_W`[src]

Bit 1 - Clear RSTART Interrupt Flag

`pub fn addr(&mut self) -> ADDR_W`[src]

Bit 2 - Clear ADDR Interrupt Flag

`pub fn txc(&mut self) -> TXC_W`[src]

Bit 3 - Clear TXC Interrupt Flag

`pub fn ack(&mut self) -> ACK_W`[src]

Bit 6 - Clear ACK Interrupt Flag

`pub fn nack(&mut self) -> NACK_W`[src]

Bit 7 - Clear NACK Interrupt Flag

`pub fn mstop(&mut self) -> MSTOP_W`[src]

Bit 8 - Clear MSTOP Interrupt Flag

`pub fn arblost(&mut self) -> ARBLOST_W`[src]

Bit 9 - Clear ARBLOST Interrupt Flag

`pub fn buserr(&mut self) -> BUSERR_W`[src]

Bit 10 - Clear BUSERR Interrupt Flag

`pub fn bushold(&mut self) -> BUSHOLD_W`[src]

Bit 11 - Clear BUSHOLD Interrupt Flag

`pub fn txof(&mut self) -> TXOF_W`[src]

Bit 12 - Clear TXOF Interrupt Flag

`pub fn rxuf(&mut self) -> RXUF_W`[src]

Bit 13 - Clear RXUF Interrupt Flag

`pub fn bito(&mut self) -> BITO_W`[src]

Bit 14 - Clear BITO Interrupt Flag

`pub fn clto(&mut self) -> CLTO_W`[src]

Bit 15 - Clear CLTO Interrupt Flag

`pub fn sstop(&mut self) -> SSTOP_W`[src]

Bit 16 - Clear SSTOP Interrupt Flag

`pub fn rxfull(&mut self) -> RXFULL_W`[src]

Bit 17 - Clear RXFULL Interrupt Flag

`pub fn clerr(&mut self) -> CLERR_W`[src]

Bit 18 - Clear CLERR Interrupt Flag

`impl W<u32, Reg<u32, _IEN>>`[src]

`pub fn start(&mut self) -> START_W`[src]

Bit 0 - START Interrupt Enable

`pub fn rstart(&mut self) -> RSTART_W`[src]

Bit 1 - RSTART Interrupt Enable

`pub fn addr(&mut self) -> ADDR_W`[src]

Bit 2 - ADDR Interrupt Enable

`pub fn txc(&mut self) -> TXC_W`[src]

Bit 3 - TXC Interrupt Enable

`pub fn txbl(&mut self) -> TXBL_W`[src]

Bit 4 - TXBL Interrupt Enable

`pub fn rxdatav(&mut self) -> RXDATAV_W`[src]

Bit 5 - RXDATAV Interrupt Enable

`pub fn ack(&mut self) -> ACK_W`[src]

Bit 6 - ACK Interrupt Enable

`pub fn nack(&mut self) -> NACK_W`[src]

Bit 7 - NACK Interrupt Enable

`pub fn mstop(&mut self) -> MSTOP_W`[src]

Bit 8 - MSTOP Interrupt Enable

`pub fn arblost(&mut self) -> ARBLOST_W`[src]

Bit 9 - ARBLOST Interrupt Enable

`pub fn buserr(&mut self) -> BUSERR_W`[src]

Bit 10 - BUSERR Interrupt Enable

`pub fn bushold(&mut self) -> BUSHOLD_W`[src]

Bit 11 - BUSHOLD Interrupt Enable

`pub fn txof(&mut self) -> TXOF_W`[src]

Bit 12 - TXOF Interrupt Enable

`pub fn rxuf(&mut self) -> RXUF_W`[src]

Bit 13 - RXUF Interrupt Enable

`pub fn bito(&mut self) -> BITO_W`[src]

Bit 14 - BITO Interrupt Enable

`pub fn clto(&mut self) -> CLTO_W`[src]

Bit 15 - CLTO Interrupt Enable

`pub fn sstop(&mut self) -> SSTOP_W`[src]

Bit 16 - SSTOP Interrupt Enable

`pub fn rxfull(&mut self) -> RXFULL_W`[src]

Bit 17 - RXFULL Interrupt Enable

`pub fn clerr(&mut self) -> CLERR_W`[src]

Bit 18 - CLERR Interrupt Enable

`impl W<u32, Reg<u32, _ROUTEPEN>>`[src]

`pub fn sdapen(&mut self) -> SDAPEN_W`[src]

Bit 0 - SDA Pin Enable

`pub fn sclpen(&mut self) -> SCLPEN_W`[src]

Bit 1 - SCL Pin Enable

`impl W<u32, Reg<u32, _ROUTELOC0>>`[src]

`pub fn sdaloc(&mut self) -> SDALOC_W`[src]

Bits 0:5 - I/O Location

`pub fn sclloc(&mut self) -> SCLLOC_W`[src]

Bits 8:13 - I/O Location

`impl W<u32, Reg<u32, _CTRL>>`[src]

`pub fn warmupmode(&mut self) -> WARMUPMODE_W`[src]

Bits 0:1 - Warm-up Mode

`pub fn singledmawu(&mut self) -> SINGLEDMAWU_W`[src]

Bit 2 - SINGLEFIFO DMA Wakeup

`pub fn scandmawu(&mut self) -> SCANDMAWU_W`[src]

Bit 3 - SCANFIFO DMA Wakeup

`pub fn tailgate(&mut self) -> TAILGATE_W`[src]

Bit 4 - Conversion Tailgating

`pub fn asyncclken(&mut self) -> ASYNCCLKEN_W`[src]

Bit 6 - Selects ASYNC CLK Enable Mode When ADCCLKMODE=1

`pub fn adcclkmode(&mut self) -> ADCCLKMODE_W`[src]

Bit 7 - ADC Clock Mode

`pub fn presc(&mut self) -> PRESC_W`[src]

Bits 8:14 - Prescalar Setting for ADC Sample and Conversion Clock

`pub fn timebase(&mut self) -> TIMEBASE_W`[src]

Bits 16:22 - 1us Time Base

`pub fn ovsrsel(&mut self) -> OVSRSEL_W`[src]

Bits 24:27 - Oversample Rate Select

`pub fn chconmode(&mut self) -> CHCONMODE_W`[src]

Bit 29 - Channel Connect

`impl W<u32, Reg<u32, _CMD>>`[src]

`pub fn singlestart(&mut self) -> SINGLESTART_W`[src]

Bit 0 - Single Channel Conversion Start

`pub fn singlestop(&mut self) -> SINGLESTOP_W`[src]

Bit 1 - Single Channel Conversion Stop

`pub fn scanstart(&mut self) -> SCANSTART_W`[src]

Bit 2 - Scan Sequence Start

`pub fn scanstop(&mut self) -> SCANSTOP_W`[src]

Bit 3 - Scan Sequence Stop

`impl W<u32, Reg<u32, _SINGLECTRL>>`[src]

`pub fn rep(&mut self) -> REP_W`[src]

Bit 0 - Single Channel Repetitive Mode

`pub fn diff(&mut self) -> DIFF_W`[src]

Bit 1 - Single Channel Differential Mode

`pub fn adj(&mut self) -> ADJ_W`[src]

Bit 2 - Single Channel Result Adjustment

`pub fn res(&mut self) -> RES_W`[src]

Bits 3:4 - Single Channel Resolution Select

`pub fn ref_(&mut self) -> REF_W`[src]

Bits 5:7 - Single Channel Reference Selection

`pub fn possel(&mut self) -> POSSEL_W`[src]

Bits 8:15 - Single Channel Positive Input Selection

`pub fn negsel(&mut self) -> NEGSEL_W`[src]

Bits 16:23 - Single Channel Negative Input Selection

`pub fn at(&mut self) -> AT_W`[src]

Bits 24:27 - Single Channel Acquisition Time

`pub fn prsen(&mut self) -> PRSEN_W`[src]

Bit 29 - Single Channel PRS Trigger Enable

`pub fn cmpen(&mut self) -> CMPEN_W`[src]

Bit 31 - Compare Logic Enable for Single Channel

`impl W<u32, Reg<u32, _SINGLECTRLX>>`[src]

`pub fn vrefsel(&mut self) -> VREFSEL_W`[src]

Bits 0:2 - Single Channel Reference Selection

`pub fn vrefattfix(&mut self) -> VREFATTFIX_W`[src]

Bit 3 - Enable Fixed Scaling on VREF

`pub fn vrefatt(&mut self) -> VREFATT_W`[src]

Bits 4:7 - Code for VREF Attenuation Factor When VREFSEL is 1, 2 or 5

`pub fn vinatt(&mut self) -> VINATT_W`[src]

Bits 8:11 - Code for VIN Attenuation Factor

`pub fn dvl(&mut self) -> DVL_W`[src]

Bits 12:13 - Single Channel DV Level Select

`pub fn fifoofact(&mut self) -> FIFOOFACT_W`[src]

Bit 14 - Single Channel FIFO Overflow Action

`pub fn prsmode(&mut self) -> PRSMODE_W`[src]

Bit 16 - Single Channel PRS Trigger Mode

`pub fn prssel(&mut self) -> PRSSEL_W`[src]

Bits 17:20 - Single Channel PRS Trigger Select

`pub fn convstartdelay(&mut self) -> CONVSTARTDELAY_W`[src]

Bits 24:26 - Delay Value for Next Conversion Start If CONVSTARTDELAYEN is Set

`pub fn convstartdelayen(&mut self) -> CONVSTARTDELAYEN_W`[src]

Bit 27 - Enable Delaying Next Conversion Start

`impl W<u32, Reg<u32, _SCANCTRL>>`[src]

`pub fn rep(&mut self) -> REP_W`[src]

Bit 0 - Scan Sequence Repetitive Mode

`pub fn diff(&mut self) -> DIFF_W`[src]

Bit 1 - Scan Sequence Differential Mode

`pub fn adj(&mut self) -> ADJ_W`[src]

Bit 2 - Scan Sequence Result Adjustment

`pub fn res(&mut self) -> RES_W`[src]

Bits 3:4 - Scan Sequence Resolution Select

`pub fn ref_(&mut self) -> REF_W`[src]

Bits 5:7 - Scan Sequence Reference Selection

`pub fn at(&mut self) -> AT_W`[src]

Bits 24:27 - Scan Acquisition Time

`pub fn prsen(&mut self) -> PRSEN_W`[src]

Bit 29 - Scan Sequence PRS Trigger Enable

`pub fn cmpen(&mut self) -> CMPEN_W`[src]

Bit 31 - Compare Logic Enable for Scan

`impl W<u32, Reg<u32, _SCANCTRLX>>`[src]

`pub fn vrefsel(&mut self) -> VREFSEL_W`[src]

Bits 0:2 - Scan Channel Reference Selection

`pub fn vrefattfix(&mut self) -> VREFATTFIX_W`[src]

Bit 3 - Enable Fixed Scaling on VREF

`pub fn vrefatt(&mut self) -> VREFATT_W`[src]

Bits 4:7 - Code for VREF Attenuation Factor When VREFSEL is 1, 2 or 5

`pub fn vinatt(&mut self) -> VINATT_W`[src]

Bits 8:11 - Code for VIN Attenuation Factor

`pub fn dvl(&mut self) -> DVL_W`[src]

Bits 12:13 - Scan DV Level Select

`pub fn fifoofact(&mut self) -> FIFOOFACT_W`[src]

Bit 14 - Scan FIFO Overflow Action

`pub fn prsmode(&mut self) -> PRSMODE_W`[src]

Bit 16 - Scan PRS Trigger Mode

`pub fn prssel(&mut self) -> PRSSEL_W`[src]

Bits 17:20 - Scan Sequence PRS Trigger Select

`pub fn convstartdelay(&mut self) -> CONVSTARTDELAY_W`[src]

Bits 24:26 - Delay Next Conversion Start If CONVSTARTDELAYEN is Set

`pub fn convstartdelayen(&mut self) -> CONVSTARTDELAYEN_W`[src]

Bit 27 - Enable Delaying Next Conversion Start

`impl W<u32, Reg<u32, _SCANMASK>>`[src]

`pub fn scaninputen(&mut self) -> SCANINPUTEN_W`[src]

Bits 0:31 - Scan Sequence Input Mask

`impl W<u32, Reg<u32, _SCANINPUTSEL>>`[src]

`pub fn input0to7sel(&mut self) -> INPUT0TO7SEL_W`[src]

Bits 0:4 - Inputs Chosen for ADCn_INPUT7-ADCn_INPUT0 as Referred in SCANMASK

`pub fn input8to15sel(&mut self) -> INPUT8TO15SEL_W`[src]

Bits 8:12 - Inputs Chosen for ADCn_INPUT8-ADCn_INPUT15 as Referred in SCANMASK

`pub fn input16to23sel(&mut self) -> INPUT16TO23SEL_W`[src]

Bits 16:20 - Inputs Chosen for ADCn_INPUT16-ADCn_INPUT23 as Referred in SCANMASK

`pub fn input24to31sel(&mut self) -> INPUT24TO31SEL_W`[src]

Bits 24:28 - Inputs Chosen for ADCn_INPUT24-ADCn_INPUT31 as Referred in SCANMASK

`impl W<u32, Reg<u32, _SCANNEGSEL>>`[src]

`pub fn input0negsel(&mut self) -> INPUT0NEGSEL_W`[src]

Bits 0:1 - Negative Input Select Register for ADCn_INPUT0 in Differential Scan Mode

`pub fn input2negsel(&mut self) -> INPUT2NEGSEL_W`[src]

Bits 2:3 - Negative Input Select Register for ADCn_INPUT2 in Differential Scan Mode

`pub fn input4negsel(&mut self) -> INPUT4NEGSEL_W`[src]

Bits 4:5 - Negative Input Select Register for ADCn_INPUT4 in Differential Scan Mode

`pub fn input6negsel(&mut self) -> INPUT6NEGSEL_W`[src]

Bits 6:7 - Negative Input Select Register for ADCn_INPUT1 in Differential Scan Mode

`pub fn input9negsel(&mut self) -> INPUT9NEGSEL_W`[src]

Bits 8:9 - Negative Input Select Register for ADCn_INPUT9 in Differential Scan Mode

`pub fn input11negsel(&mut self) -> INPUT11NEGSEL_W`[src]

Bits 10:11 - Negative Input Select Register for ADCn_INPUT11 in Differential Scan Mode

`pub fn input13negsel(&mut self) -> INPUT13NEGSEL_W`[src]

Bits 12:13 - Negative Input Select Register for ADCn_INPUT13 in Differential Scan Mode

`pub fn input15negsel(&mut self) -> INPUT15NEGSEL_W`[src]

Bits 14:15 - Negative Input Select Register for ADCn_INPUT15 in Differential Scan Mode

`impl W<u32, Reg<u32, _CMPTHR>>`[src]

`pub fn adlt(&mut self) -> ADLT_W`[src]

Bits 0:15 - Less Than Compare Threshold

`pub fn adgt(&mut self) -> ADGT_W`[src]

Bits 16:31 - Greater Than Compare Threshold

`impl W<u32, Reg<u32, _BIASPROG>>`[src]

`pub fn adcbiasprog(&mut self) -> ADCBIASPROG_W`[src]

Bits 0:3 - Bias Programming Value of Analog ADC Block

`pub fn vfaultclr(&mut self) -> VFAULTCLR_W`[src]

Bit 12 - Clear VREFOF Flag

`pub fn gpbiasacc(&mut self) -> GPBIASACC_W`[src]

Bit 16 - Accuracy Setting for the System Bias During ADC Operation

`impl W<u32, Reg<u32, _CAL>>`[src]

`pub fn singleoffset(&mut self) -> SINGLEOFFSET_W`[src]

Bits 0:3 - Single Mode Offset Calibration Value for Differential or Positive Single-ended Mode

`pub fn singleoffsetinv(&mut self) -> SINGLEOFFSETINV_W`[src]

Bits 4:7 - Single Mode Offset Calibration Value for Negative Single-ended Mode

`pub fn singlegain(&mut self) -> SINGLEGAIN_W`[src]

Bits 8:14 - Single Mode Gain Calibration Value

`pub fn offsetinvmode(&mut self) -> OFFSETINVMODE_W`[src]

Bit 15 - Negative Single-ended Offset Calibration is Enabled

`pub fn scanoffset(&mut self) -> SCANOFFSET_W`[src]

Bits 16:19 - Scan Mode Offset Calibration Value for Differential or Positive Single-ended Mode

`pub fn scanoffsetinv(&mut self) -> SCANOFFSETINV_W`[src]

Bits 20:23 - Scan Mode Offset Calibration Value for Negative Single-ended Mode

`pub fn scangain(&mut self) -> SCANGAIN_W`[src]

Bits 24:30 - Scan Mode Gain Calibration Value

`pub fn calen(&mut self) -> CALEN_W`[src]

Bit 31 - Calibration Mode is Enabled

`impl W<u32, Reg<u32, _IFS>>`[src]

`pub fn singleof(&mut self) -> SINGLEOF_W`[src]

Bit 8 - Set SINGLEOF Interrupt Flag

`pub fn scanof(&mut self) -> SCANOF_W`[src]

Bit 9 - Set SCANOF Interrupt Flag

`pub fn singleuf(&mut self) -> SINGLEUF_W`[src]

Bit 10 - Set SINGLEUF Interrupt Flag

`pub fn scanuf(&mut self) -> SCANUF_W`[src]

Bit 11 - Set SCANUF Interrupt Flag

`pub fn singlecmp(&mut self) -> SINGLECMP_W`[src]

Bit 16 - Set SINGLECMP Interrupt Flag

`pub fn scancmp(&mut self) -> SCANCMP_W`[src]

Bit 17 - Set SCANCMP Interrupt Flag

`pub fn vrefov(&mut self) -> VREFOV_W`[src]

Bit 24 - Set VREFOV Interrupt Flag

`pub fn progerr(&mut self) -> PROGERR_W`[src]

Bit 25 - Set PROGERR Interrupt Flag

`impl W<u32, Reg<u32, _IFC>>`[src]

`pub fn singleof(&mut self) -> SINGLEOF_W`[src]

Bit 8 - Clear SINGLEOF Interrupt Flag

`pub fn scanof(&mut self) -> SCANOF_W`[src]

Bit 9 - Clear SCANOF Interrupt Flag

`pub fn singleuf(&mut self) -> SINGLEUF_W`[src]

Bit 10 - Clear SINGLEUF Interrupt Flag

`pub fn scanuf(&mut self) -> SCANUF_W`[src]

Bit 11 - Clear SCANUF Interrupt Flag

`pub fn singlecmp(&mut self) -> SINGLECMP_W`[src]

Bit 16 - Clear SINGLECMP Interrupt Flag

`pub fn scancmp(&mut self) -> SCANCMP_W`[src]

Bit 17 - Clear SCANCMP Interrupt Flag

`pub fn vrefov(&mut self) -> VREFOV_W`[src]

Bit 24 - Clear VREFOV Interrupt Flag

`pub fn progerr(&mut self) -> PROGERR_W`[src]

Bit 25 - Clear PROGERR Interrupt Flag

`impl W<u32, Reg<u32, _IEN>>`[src]

`pub fn single(&mut self) -> SINGLE_W`[src]

Bit 0 - SINGLE Interrupt Enable

`pub fn scan(&mut self) -> SCAN_W`[src]

Bit 1 - SCAN Interrupt Enable

`pub fn singleof(&mut self) -> SINGLEOF_W`[src]

Bit 8 - SINGLEOF Interrupt Enable

`pub fn scanof(&mut self) -> SCANOF_W`[src]

Bit 9 - SCANOF Interrupt Enable

`pub fn singleuf(&mut self) -> SINGLEUF_W`[src]

Bit 10 - SINGLEUF Interrupt Enable

`pub fn scanuf(&mut self) -> SCANUF_W`[src]

Bit 11 - SCANUF Interrupt Enable

`pub fn singlecmp(&mut self) -> SINGLECMP_W`[src]

Bit 16 - SINGLECMP Interrupt Enable

`pub fn scancmp(&mut self) -> SCANCMP_W`[src]

Bit 17 - SCANCMP Interrupt Enable

`pub fn vrefov(&mut self) -> VREFOV_W`[src]

Bit 24 - VREFOV Interrupt Enable

`pub fn progerr(&mut self) -> PROGERR_W`[src]

Bit 25 - PROGERR Interrupt Enable

`impl W<u32, Reg<u32, _SINGLEFIFOCLEAR>>`[src]

`pub fn singlefifoclear(&mut self) -> SINGLEFIFOCLEAR_W`[src]

Bit 0 - Clear Single FIFO Content

`impl W<u32, Reg<u32, _SCANFIFOCLEAR>>`[src]

`pub fn scanfifoclear(&mut self) -> SCANFIFOCLEAR_W`[src]

Bit 0 - Clear Scan FIFO Content

`impl W<u32, Reg<u32, _APORTMASTERDIS>>`[src]

`pub fn aport1xmasterdis(&mut self) -> APORT1XMASTERDIS_W`[src]

Bit 2 - APORT1X Master Disable

`pub fn aport1ymasterdis(&mut self) -> APORT1YMASTERDIS_W`[src]

Bit 3 - APORT1Y Master Disable

`pub fn aport2xmasterdis(&mut self) -> APORT2XMASTERDIS_W`[src]

Bit 4 - APORT2X Master Disable

`pub fn aport2ymasterdis(&mut self) -> APORT2YMASTERDIS_W`[src]

Bit 5 - APORT2Y Master Disable

`pub fn aport3xmasterdis(&mut self) -> APORT3XMASTERDIS_W`[src]

Bit 6 - APORT3X Master Disable

`pub fn aport3ymasterdis(&mut self) -> APORT3YMASTERDIS_W`[src]

Bit 7 - APORT3Y Master Disable

`pub fn aport4xmasterdis(&mut self) -> APORT4XMASTERDIS_W`[src]

Bit 8 - APORT4X Master Disable

`pub fn aport4ymasterdis(&mut self) -> APORT4YMASTERDIS_W`[src]

Bit 9 - APORT4Y Master Disable

`impl W<u32, Reg<u32, _CTRL>>`[src]

`pub fn en(&mut self) -> EN_W`[src]

Bit 0 - Analog Comparator Enable

`pub fn inactval(&mut self) -> INACTVAL_W`[src]

Bit 2 - Inactive Value

`pub fn gpioinv(&mut self) -> GPIOINV_W`[src]

Bit 3 - Comparator GPIO Output Invert

`pub fn aportxmasterdis(&mut self) -> APORTXMASTERDIS_W`[src]

Bit 8 - APORT Bus X Master Disable

`pub fn aportymasterdis(&mut self) -> APORTYMASTERDIS_W`[src]

Bit 9 - APORT Bus Y Master Disable

`pub fn aportvmasterdis(&mut self) -> APORTVMASTERDIS_W`[src]

Bit 10 - APORT Bus Master Disable for Bus Selected By VASEL

`pub fn pwrsel(&mut self) -> PWRSEL_W`[src]

Bits 12:14 - Power Select

`pub fn accuracy(&mut self) -> ACCURACY_W`[src]

Bit 15 - ACMP Accuracy Mode

`pub fn inputrange(&mut self) -> INPUTRANGE_W`[src]

Bits 18:19 - Input Range

`pub fn irise(&mut self) -> IRISE_W`[src]

Bit 20 - Rising Edge Interrupt Sense

`pub fn ifall(&mut self) -> IFALL_W`[src]

Bit 21 - Falling Edge Interrupt Sense

`pub fn biasprog(&mut self) -> BIASPROG_W`[src]

Bits 24:29 - Bias Configuration

`pub fn fullbias(&mut self) -> FULLBIAS_W`[src]

Bit 31 - Full Bias Current

`impl W<u32, Reg<u32, _INPUTSEL>>`[src]

`pub fn possel(&mut self) -> POSSEL_W`[src]

Bits 0:7 - Positive Input Select

`pub fn negsel(&mut self) -> NEGSEL_W`[src]

Bits 8:15 - Negative Input Select

`pub fn vasel(&mut self) -> VASEL_W`[src]

Bits 16:21 - VA Selection

`pub fn vbsel(&mut self) -> VBSEL_W`[src]

Bit 22 - VB Selection

`pub fn vlpsel(&mut self) -> VLPSEL_W`[src]

Bit 24 - Low-Power Sampled Voltage Selection

`pub fn csresen(&mut self) -> CSRESEN_W`[src]

Bit 26 - Capacitive Sense Mode Internal Resistor Enable

`pub fn csressel(&mut self) -> CSRESSEL_W`[src]

Bits 28:30 - Capacitive Sense Mode Internal Resistor Select

`impl W<u32, Reg<u32, _IFS>>`[src]

`pub fn edge(&mut self) -> EDGE_W`[src]

Bit 0 - Set EDGE Interrupt Flag

`pub fn warmup(&mut self) -> WARMUP_W`[src]

Bit 1 - Set WARMUP Interrupt Flag

`pub fn aportconflict(&mut self) -> APORTCONFLICT_W`[src]

Bit 2 - Set APORTCONFLICT Interrupt Flag

`impl W<u32, Reg<u32, _IFC>>`[src]

`pub fn edge(&mut self) -> EDGE_W`[src]

Bit 0 - Clear EDGE Interrupt Flag

`pub fn warmup(&mut self) -> WARMUP_W`[src]

Bit 1 - Clear WARMUP Interrupt Flag

`pub fn aportconflict(&mut self) -> APORTCONFLICT_W`[src]

Bit 2 - Clear APORTCONFLICT Interrupt Flag

`impl W<u32, Reg<u32, _IEN>>`[src]

`pub fn edge(&mut self) -> EDGE_W`[src]

Bit 0 - EDGE Interrupt Enable

`pub fn warmup(&mut self) -> WARMUP_W`[src]

Bit 1 - WARMUP Interrupt Enable

`pub fn aportconflict(&mut self) -> APORTCONFLICT_W`[src]

Bit 2 - APORTCONFLICT Interrupt Enable

`impl W<u32, Reg<u32, _HYSTERESIS0>>`[src]

`pub fn hyst(&mut self) -> HYST_W`[src]

Bits 0:3 - Hysteresis Select When ACMPOUT=0

`pub fn divva(&mut self) -> DIVVA_W`[src]

Bits 16:21 - Divider for VA Voltage When ACMPOUT=0

`pub fn divvb(&mut self) -> DIVVB_W`[src]

Bits 24:29 - Divider for VB Voltage When ACMPOUT=0

`impl W<u32, Reg<u32, _HYSTERESIS1>>`[src]

`pub fn hyst(&mut self) -> HYST_W`[src]

Bits 0:3 - Hysteresis Select When ACMPOUT=1

`pub fn divva(&mut self) -> DIVVA_W`[src]

Bits 16:21 - Divider for VA Voltage When ACMPOUT=1

`pub fn divvb(&mut self) -> DIVVB_W`[src]

Bits 24:29 - Divider for VB Voltage When ACMPOUT=1

`impl W<u32, Reg<u32, _ROUTEPEN>>`[src]

`pub fn outpen(&mut self) -> OUTPEN_W`[src]

Bit 0 - ACMP Output Pin Enable

`impl W<u32, Reg<u32, _ROUTELOC0>>`[src]

`pub fn outloc(&mut self) -> OUTLOC_W`[src]

Bits 0:5 - I/O Location

`impl W<u32, Reg<u32, _CTRL>>`[src]

`pub fn en(&mut self) -> EN_W`[src]

Bit 0 - Analog Comparator Enable

`pub fn inactval(&mut self) -> INACTVAL_W`[src]

Bit 2 - Inactive Value

`pub fn gpioinv(&mut self) -> GPIOINV_W`[src]

Bit 3 - Comparator GPIO Output Invert

`pub fn aportxmasterdis(&mut self) -> APORTXMASTERDIS_W`[src]

Bit 8 - APORT Bus X Master Disable

`pub fn aportymasterdis(&mut self) -> APORTYMASTERDIS_W`[src]

Bit 9 - APORT Bus Y Master Disable

`pub fn aportvmasterdis(&mut self) -> APORTVMASTERDIS_W`[src]

Bit 10 - APORT Bus Master Disable for Bus Selected By VASEL

`pub fn pwrsel(&mut self) -> PWRSEL_W`[src]

Bits 12:14 - Power Select

`pub fn accuracy(&mut self) -> ACCURACY_W`[src]

Bit 15 - ACMP Accuracy Mode

`pub fn inputrange(&mut self) -> INPUTRANGE_W`[src]

Bits 18:19 - Input Range

`pub fn irise(&mut self) -> IRISE_W`[src]

Bit 20 - Rising Edge Interrupt Sense

`pub fn ifall(&mut self) -> IFALL_W`[src]

Bit 21 - Falling Edge Interrupt Sense

`pub fn biasprog(&mut self) -> BIASPROG_W`[src]

Bits 24:29 - Bias Configuration

`pub fn fullbias(&mut self) -> FULLBIAS_W`[src]

Bit 31 - Full Bias Current

`impl W<u32, Reg<u32, _INPUTSEL>>`[src]

`pub fn possel(&mut self) -> POSSEL_W`[src]

Bits 0:7 - Positive Input Select

`pub fn negsel(&mut self) -> NEGSEL_W`[src]

Bits 8:15 - Negative Input Select

`pub fn vasel(&mut self) -> VASEL_W`[src]

Bits 16:21 - VA Selection

`pub fn vbsel(&mut self) -> VBSEL_W`[src]

Bit 22 - VB Selection

`pub fn vlpsel(&mut self) -> VLPSEL_W`[src]

Bit 24 - Low-Power Sampled Voltage Selection

`pub fn csresen(&mut self) -> CSRESEN_W`[src]

Bit 26 - Capacitive Sense Mode Internal Resistor Enable

`pub fn csressel(&mut self) -> CSRESSEL_W`[src]

Bits 28:30 - Capacitive Sense Mode Internal Resistor Select

`impl W<u32, Reg<u32, _IFS>>`[src]

`pub fn edge(&mut self) -> EDGE_W`[src]

Bit 0 - Set EDGE Interrupt Flag

`pub fn warmup(&mut self) -> WARMUP_W`[src]

Bit 1 - Set WARMUP Interrupt Flag

`pub fn aportconflict(&mut self) -> APORTCONFLICT_W`[src]

Bit 2 - Set APORTCONFLICT Interrupt Flag

`impl W<u32, Reg<u32, _IFC>>`[src]

`pub fn edge(&mut self) -> EDGE_W`[src]

Bit 0 - Clear EDGE Interrupt Flag

`pub fn warmup(&mut self) -> WARMUP_W`[src]

Bit 1 - Clear WARMUP Interrupt Flag

`pub fn aportconflict(&mut self) -> APORTCONFLICT_W`[src]

Bit 2 - Clear APORTCONFLICT Interrupt Flag

`impl W<u32, Reg<u32, _IEN>>`[src]

`pub fn edge(&mut self) -> EDGE_W`[src]

Bit 0 - EDGE Interrupt Enable

`pub fn warmup(&mut self) -> WARMUP_W`[src]

Bit 1 - WARMUP Interrupt Enable

`pub fn aportconflict(&mut self) -> APORTCONFLICT_W`[src]

Bit 2 - APORTCONFLICT Interrupt Enable

`impl W<u32, Reg<u32, _HYSTERESIS0>>`[src]

`pub fn hyst(&mut self) -> HYST_W`[src]

Bits 0:3 - Hysteresis Select When ACMPOUT=0

`pub fn divva(&mut self) -> DIVVA_W`[src]

Bits 16:21 - Divider for VA Voltage When ACMPOUT=0

`pub fn divvb(&mut self) -> DIVVB_W`[src]

Bits 24:29 - Divider for VB Voltage When ACMPOUT=0

`impl W<u32, Reg<u32, _HYSTERESIS1>>`[src]

`pub fn hyst(&mut self) -> HYST_W`[src]

Bits 0:3 - Hysteresis Select When ACMPOUT=1

`pub fn divva(&mut self) -> DIVVA_W`[src]

Bits 16:21 - Divider for VA Voltage When ACMPOUT=1

`pub fn divvb(&mut self) -> DIVVB_W`[src]

Bits 24:29 - Divider for VB Voltage When ACMPOUT=1

`impl W<u32, Reg<u32, _ROUTEPEN>>`[src]

`pub fn outpen(&mut self) -> OUTPEN_W`[src]

Bit 0 - ACMP Output Pin Enable

`impl W<u32, Reg<u32, _ROUTELOC0>>`[src]

`pub fn outloc(&mut self) -> OUTLOC_W`[src]

Bits 0:5 - I/O Location

`impl W<u32, Reg<u32, _CTRL>>`[src]

`pub fn en(&mut self) -> EN_W`[src]

Bit 0 - Current DAC Enable

`pub fn cursink(&mut self) -> CURSINK_W`[src]

Bit 1 - Current Sink Enable

`pub fn minouttrans(&mut self) -> MINOUTTRANS_W`[src]

Bit 2 - Minimum Output Transition Enable

`pub fn aportouten(&mut self) -> APORTOUTEN_W`[src]

Bit 3 - APORT Output Enable

`pub fn aportoutsel(&mut self) -> APORTOUTSEL_W`[src]

Bits 4:11 - APORT Output Select

`pub fn pwrsel(&mut self) -> PWRSEL_W`[src]

Bit 12 - Power Select

`pub fn em2delay(&mut self) -> EM2DELAY_W`[src]

Bit 13 - EM2 Delay

`pub fn aportmasterdis(&mut self) -> APORTMASTERDIS_W`[src]

Bit 14 - APORT Bus Master Disable

`pub fn aportoutenprs(&mut self) -> APORTOUTENPRS_W`[src]

Bit 16 - PRS Controlled APORT Output Enable

`pub fn prssel(&mut self) -> PRSSEL_W`[src]

Bits 20:23 - IDAC Output Enable PRS Channel Select

`impl W<u32, Reg<u32, _CURPROG>>`[src]

`pub fn rangesel(&mut self) -> RANGESEL_W`[src]

Bits 0:1 - Current Range Select

`pub fn stepsel(&mut self) -> STEPSEL_W`[src]

Bits 8:12 - Current Step Size Select

`pub fn tuning(&mut self) -> TUNING_W`[src]

Bits 16:23 - Tune the Current to Given Accuracy

`impl W<u32, Reg<u32, _DUTYCONFIG>>`[src]

`pub fn em2dutycycledis(&mut self) -> EM2DUTYCYCLEDIS_W`[src]

Bit 1 - Duty Cycle Enable

`impl W<u32, Reg<u32, _IFS>>`[src]

`pub fn aportconflict(&mut self) -> APORTCONFLICT_W`[src]

Bit 1 - Set APORTCONFLICT Interrupt Flag

`impl W<u32, Reg<u32, _IFC>>`[src]

`pub fn aportconflict(&mut self) -> APORTCONFLICT_W`[src]

Bit 1 - Clear APORTCONFLICT Interrupt Flag

`impl W<u32, Reg<u32, _IEN>>`[src]

`pub fn aportconflict(&mut self) -> APORTCONFLICT_W`[src]

Bit 1 - APORTCONFLICT Interrupt Enable

`impl W<u32, Reg<u32, _CTRL>>`[src]

`pub fn enable(&mut self) -> ENABLE_W`[src]

Bit 0 - RTCC Enable

`pub fn debugrun(&mut self) -> DEBUGRUN_W`[src]

Bit 2 - Debug Mode Run Enable

`pub fn preccv0top(&mut self) -> PRECCV0TOP_W`[src]

Bit 4 - Pre-counter CCV0 Top Value Enable

`pub fn ccv1top(&mut self) -> CCV1TOP_W`[src]

Bit 5 - CCV1 Top Value Enable

`pub fn cntpresc(&mut self) -> CNTPRESC_W`[src]

Bits 8:11 - Counter Prescaler Value

`pub fn cnttick(&mut self) -> CNTTICK_W`[src]

Bit 12 - Counter Prescaler Mode

`pub fn oscfdeten(&mut self) -> OSCFDETEN_W`[src]

Bit 15 - Oscillator Failure Detection Enable

`pub fn cntmode(&mut self) -> CNTMODE_W`[src]

Bit 16 - Main Counter Mode

`pub fn lyearcorrdis(&mut self) -> LYEARCORRDIS_W`[src]

Bit 17 - Leap Year Correction Disabled

`impl W<u32, Reg<u32, _PRECNT>>`[src]

`pub fn precnt(&mut self) -> PRECNT_W`[src]

Bits 0:14 - Pre-Counter Value

`impl W<u32, Reg<u32, _CNT>>`[src]

`pub fn cnt(&mut self) -> CNT_W`[src]

Bits 0:31 - Counter Value

`impl W<u32, Reg<u32, _TIME>>`[src]

`pub fn secu(&mut self) -> SECU_W`[src]

Bits 0:3 - Seconds, Units

`pub fn sect(&mut self) -> SECT_W`[src]

Bits 4:6 - Seconds, Tens

`pub fn minu(&mut self) -> MINU_W`[src]

Bits 8:11 - Minutes, Units

`pub fn mint(&mut self) -> MINT_W`[src]

Bits 12:14 - Minutes, Tens

`pub fn houru(&mut self) -> HOURU_W`[src]

Bits 16:19 - Hours, Units

`pub fn hourt(&mut self) -> HOURT_W`[src]

Bits 20:21 - Hours, Tens

`impl W<u32, Reg<u32, _DATE>>`[src]

`pub fn dayomu(&mut self) -> DAYOMU_W`[src]

Bits 0:3 - Day of Month, Units

`pub fn dayomt(&mut self) -> DAYOMT_W`[src]

Bits 4:5 - Day of Month, Tens

`pub fn monthu(&mut self) -> MONTHU_W`[src]

Bits 8:11 - Month, Units

`pub fn montht(&mut self) -> MONTHT_W`[src]

Bit 12 - Month, Tens

`pub fn yearu(&mut self) -> YEARU_W`[src]

Bits 16:19 - Year, Units

`pub fn yeart(&mut self) -> YEART_W`[src]

Bits 20:23 - Year, Tens

`pub fn dayow(&mut self) -> DAYOW_W`[src]

Bits 24:26 - Day of Week

`impl W<u32, Reg<u32, _IFS>>`[src]

`pub fn of(&mut self) -> OF_W`[src]

Bit 0 - Set OF Interrupt Flag

`pub fn cc0(&mut self) -> CC0_W`[src]

Bit 1 - Set CC0 Interrupt Flag

`pub fn cc1(&mut self) -> CC1_W`[src]

Bit 2 - Set CC1 Interrupt Flag

`pub fn cc2(&mut self) -> CC2_W`[src]

Bit 3 - Set CC2 Interrupt Flag

`pub fn oscfail(&mut self) -> OSCFAIL_W`[src]

Bit 4 - Set OSCFAIL Interrupt Flag

`pub fn cnttick(&mut self) -> CNTTICK_W`[src]

Bit 5 - Set CNTTICK Interrupt Flag

`pub fn mintick(&mut self) -> MINTICK_W`[src]

Bit 6 - Set MINTICK Interrupt Flag

`pub fn hourtick(&mut self) -> HOURTICK_W`[src]

Bit 7 - Set HOURTICK Interrupt Flag

`pub fn daytick(&mut self) -> DAYTICK_W`[src]

Bit 8 - Set DAYTICK Interrupt Flag

`pub fn dayowof(&mut self) -> DAYOWOF_W`[src]

Bit 9 - Set DAYOWOF Interrupt Flag

`pub fn monthtick(&mut self) -> MONTHTICK_W`[src]

Bit 10 - Set MONTHTICK Interrupt Flag

`impl W<u32, Reg<u32, _IFC>>`[src]

`pub fn of(&mut self) -> OF_W`[src]

Bit 0 - Clear OF Interrupt Flag

`pub fn cc0(&mut self) -> CC0_W`[src]

Bit 1 - Clear CC0 Interrupt Flag

`pub fn cc1(&mut self) -> CC1_W`[src]

Bit 2 - Clear CC1 Interrupt Flag

`pub fn cc2(&mut self) -> CC2_W`[src]

Bit 3 - Clear CC2 Interrupt Flag

`pub fn oscfail(&mut self) -> OSCFAIL_W`[src]

Bit 4 - Clear OSCFAIL Interrupt Flag

`pub fn cnttick(&mut self) -> CNTTICK_W`[src]

Bit 5 - Clear CNTTICK Interrupt Flag

`pub fn mintick(&mut self) -> MINTICK_W`[src]

Bit 6 - Clear MINTICK Interrupt Flag

`pub fn hourtick(&mut self) -> HOURTICK_W`[src]

Bit 7 - Clear HOURTICK Interrupt Flag

`pub fn daytick(&mut self) -> DAYTICK_W`[src]

Bit 8 - Clear DAYTICK Interrupt Flag

`pub fn dayowof(&mut self) -> DAYOWOF_W`[src]

Bit 9 - Clear DAYOWOF Interrupt Flag

`pub fn monthtick(&mut self) -> MONTHTICK_W`[src]

Bit 10 - Clear MONTHTICK Interrupt Flag

`impl W<u32, Reg<u32, _IEN>>`[src]

`pub fn of(&mut self) -> OF_W`[src]

Bit 0 - OF Interrupt Enable

`pub fn cc0(&mut self) -> CC0_W`[src]

Bit 1 - CC0 Interrupt Enable

`pub fn cc1(&mut self) -> CC1_W`[src]

Bit 2 - CC1 Interrupt Enable

`pub fn cc2(&mut self) -> CC2_W`[src]

Bit 3 - CC2 Interrupt Enable

`pub fn oscfail(&mut self) -> OSCFAIL_W`[src]

Bit 4 - OSCFAIL Interrupt Enable

`pub fn cnttick(&mut self) -> CNTTICK_W`[src]

Bit 5 - CNTTICK Interrupt Enable

`pub fn mintick(&mut self) -> MINTICK_W`[src]

Bit 6 - MINTICK Interrupt Enable

`pub fn hourtick(&mut self) -> HOURTICK_W`[src]

Bit 7 - HOURTICK Interrupt Enable

`pub fn daytick(&mut self) -> DAYTICK_W`[src]

Bit 8 - DAYTICK Interrupt Enable

`pub fn dayowof(&mut self) -> DAYOWOF_W`[src]

Bit 9 - DAYOWOF Interrupt Enable

`pub fn monthtick(&mut self) -> MONTHTICK_W`[src]

Bit 10 - MONTHTICK Interrupt Enable

`impl W<u32, Reg<u32, _CMD>>`[src]

`pub fn clrstatus(&mut self) -> CLRSTATUS_W`[src]

Bit 0 - Clear RTCC_STATUS Register

`impl W<u32, Reg<u32, _POWERDOWN>>`[src]

`pub fn ram(&mut self) -> RAM_W`[src]

Bit 0 - Retention RAM Power-down

`impl W<u32, Reg<u32, _LOCK>>`[src]

`pub fn lockkey(&mut self) -> LOCKKEY_W`[src]

Bits 0:15 - Configuration Lock Key

`impl W<u32, Reg<u32, _EM4WUEN>>`[src]

`pub fn em4wu(&mut self) -> EM4WU_W`[src]

Bit 0 - EM4 Wake-up Enable

`impl W<u32, Reg<u32, _CC0_CTRL>>`[src]

`pub fn mode(&mut self) -> MODE_W`[src]

Bits 0:1 - CC Channel Mode

`pub fn cmoa(&mut self) -> CMOA_W`[src]

Bits 2:3 - Compare Match Output Action

`pub fn icedge(&mut self) -> ICEDGE_W`[src]

Bits 4:5 - Input Capture Edge Select

`pub fn prssel(&mut self) -> PRSSEL_W`[src]

Bits 6:9 - Compare/Capture Channel PRS Input Channel Selection

`pub fn compbase(&mut self) -> COMPBASE_W`[src]

Bit 11 - Capture Compare Channel Comparison Base

`pub fn compmask(&mut self) -> COMPMASK_W`[src]

Bits 12:16 - Capture Compare Channel Comparison Mask

`pub fn daycc(&mut self) -> DAYCC_W`[src]

Bit 17 - Day Capture/Compare Selection

`impl W<u32, Reg<u32, _CC0_CCV>>`[src]

`pub fn ccv(&mut self) -> CCV_W`[src]

Bits 0:31 - Capture/Compare Value

`impl W<u32, Reg<u32, _CC0_TIME>>`[src]

`pub fn secu(&mut self) -> SECU_W`[src]

Bits 0:3 - Seconds, Units

`pub fn sect(&mut self) -> SECT_W`[src]

Bits 4:6 - Seconds, Tens

`pub fn minu(&mut self) -> MINU_W`[src]

Bits 8:11 - Minutes, Units

`pub fn mint(&mut self) -> MINT_W`[src]

Bits 12:14 - Minutes, Tens

`pub fn houru(&mut self) -> HOURU_W`[src]

Bits 16:19 - Hours, Units

`pub fn hourt(&mut self) -> HOURT_W`[src]

Bits 20:21 - Hours, Tens

`impl W<u32, Reg<u32, _CC0_DATE>>`[src]

`pub fn dayu(&mut self) -> DAYU_W`[src]

Bits 0:3 - Day of Month/week, Units

`pub fn dayt(&mut self) -> DAYT_W`[src]

Bits 4:5 - Day of Month/week, Tens

`pub fn monthu(&mut self) -> MONTHU_W`[src]

Bits 8:11 - Month, Units

`pub fn montht(&mut self) -> MONTHT_W`[src]

Bit 12 - Month, Tens

`impl W<u32, Reg<u32, _CC1_CTRL>>`[src]

`pub fn mode(&mut self) -> MODE_W`[src]

Bits 0:1 - CC Channel Mode

`pub fn cmoa(&mut self) -> CMOA_W`[src]

Bits 2:3 - Compare Match Output Action

`pub fn icedge(&mut self) -> ICEDGE_W`[src]

Bits 4:5 - Input Capture Edge Select

`pub fn prssel(&mut self) -> PRSSEL_W`[src]

Bits 6:9 - Compare/Capture Channel PRS Input Channel Selection

`pub fn compbase(&mut self) -> COMPBASE_W`[src]

Bit 11 - Capture Compare Channel Comparison Base

`pub fn compmask(&mut self) -> COMPMASK_W`[src]

Bits 12:16 - Capture Compare Channel Comparison Mask

`pub fn daycc(&mut self) -> DAYCC_W`[src]

Bit 17 - Day Capture/Compare Selection

`impl W<u32, Reg<u32, _CC1_CCV>>`[src]

`pub fn ccv(&mut self) -> CCV_W`[src]

Bits 0:31 - Capture/Compare Value

`impl W<u32, Reg<u32, _CC1_TIME>>`[src]

`pub fn secu(&mut self) -> SECU_W`[src]

Bits 0:3 - Seconds, Units

`pub fn sect(&mut self) -> SECT_W`[src]

Bits 4:6 - Seconds, Tens

`pub fn minu(&mut self) -> MINU_W`[src]

Bits 8:11 - Minutes, Units

`pub fn mint(&mut self) -> MINT_W`[src]

Bits 12:14 - Minutes, Tens

`pub fn houru(&mut self) -> HOURU_W`[src]

Bits 16:19 - Hours, Units

`pub fn hourt(&mut self) -> HOURT_W`[src]

Bits 20:21 - Hours, Tens

`impl W<u32, Reg<u32, _CC1_DATE>>`[src]

`pub fn dayu(&mut self) -> DAYU_W`[src]

Bits 0:3 - Day of Month/week, Units

`pub fn dayt(&mut self) -> DAYT_W`[src]

Bits 4:5 - Day of Month/week, Tens

`pub fn monthu(&mut self) -> MONTHU_W`[src]

Bits 8:11 - Month, Units

`pub fn montht(&mut self) -> MONTHT_W`[src]

Bit 12 - Month, Tens

`impl W<u32, Reg<u32, _CC2_CTRL>>`[src]

`pub fn mode(&mut self) -> MODE_W`[src]

Bits 0:1 - CC Channel Mode

`pub fn cmoa(&mut self) -> CMOA_W`[src]

Bits 2:3 - Compare Match Output Action

`pub fn icedge(&mut self) -> ICEDGE_W`[src]

Bits 4:5 - Input Capture Edge Select

`pub fn prssel(&mut self) -> PRSSEL_W`[src]

Bits 6:9 - Compare/Capture Channel PRS Input Channel Selection

`pub fn compbase(&mut self) -> COMPBASE_W`[src]

Bit 11 - Capture Compare Channel Comparison Base

`pub fn compmask(&mut self) -> COMPMASK_W`[src]

Bits 12:16 - Capture Compare Channel Comparison Mask

`pub fn daycc(&mut self) -> DAYCC_W`[src]

Bit 17 - Day Capture/Compare Selection

`impl W<u32, Reg<u32, _CC2_CCV>>`[src]

`pub fn ccv(&mut self) -> CCV_W`[src]

Bits 0:31 - Capture/Compare Value

`impl W<u32, Reg<u32, _CC2_TIME>>`[src]

`pub fn secu(&mut self) -> SECU_W`[src]

Bits 0:3 - Seconds, Units

`pub fn sect(&mut self) -> SECT_W`[src]

Bits 4:6 - Seconds, Tens

`pub fn minu(&mut self) -> MINU_W`[src]

Bits 8:11 - Minutes, Units

`pub fn mint(&mut self) -> MINT_W`[src]

Bits 12:14 - Minutes, Tens

`pub fn houru(&mut self) -> HOURU_W`[src]

Bits 16:19 - Hours, Units

`pub fn hourt(&mut self) -> HOURT_W`[src]

Bits 20:21 - Hours, Tens

`impl W<u32, Reg<u32, _CC2_DATE>>`[src]

`pub fn dayu(&mut self) -> DAYU_W`[src]

Bits 0:3 - Day of Month/week, Units

`pub fn dayt(&mut self) -> DAYT_W`[src]

Bits 4:5 - Day of Month/week, Tens

`pub fn monthu(&mut self) -> MONTHU_W`[src]

Bits 8:11 - Month, Units