efm32pg12b500_pac/vdac0/
status.rs1#[doc = "Register `STATUS` reader"]
2pub struct R(crate::R<STATUS_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<STATUS_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<STATUS_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<STATUS_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Field `CH0ENS` reader - Channel 0 Enabled Status"]
17pub type CH0ENS_R = crate::BitReader<bool>;
18#[doc = "Field `CH1ENS` reader - Channel 1 Enabled Status"]
19pub type CH1ENS_R = crate::BitReader<bool>;
20#[doc = "Field `CH0BL` reader - Channel 0 Buffer Level"]
21pub type CH0BL_R = crate::BitReader<bool>;
22#[doc = "Field `CH1BL` reader - Channel 1 Buffer Level"]
23pub type CH1BL_R = crate::BitReader<bool>;
24#[doc = "Field `CH0WARM` reader - Channel 0 Warm"]
25pub type CH0WARM_R = crate::BitReader<bool>;
26#[doc = "Field `CH1WARM` reader - Channel 1 Warm"]
27pub type CH1WARM_R = crate::BitReader<bool>;
28#[doc = "Field `OPA0APORTCONFLICT` reader - OPA0 Bus Conflict Output"]
29pub type OPA0APORTCONFLICT_R = crate::BitReader<bool>;
30#[doc = "Field `OPA1APORTCONFLICT` reader - OPA1 Bus Conflict Output"]
31pub type OPA1APORTCONFLICT_R = crate::BitReader<bool>;
32#[doc = "Field `OPA2APORTCONFLICT` reader - OPA2 Bus Conflict Output"]
33pub type OPA2APORTCONFLICT_R = crate::BitReader<bool>;
34#[doc = "Field `OPA0ENS` reader - OPA0 Enabled Status"]
35pub type OPA0ENS_R = crate::BitReader<bool>;
36#[doc = "Field `OPA1ENS` reader - OPA1 Enabled Status"]
37pub type OPA1ENS_R = crate::BitReader<bool>;
38#[doc = "Field `OPA2ENS` reader - OPA2 Enabled Status"]
39pub type OPA2ENS_R = crate::BitReader<bool>;
40#[doc = "Field `OPA0WARM` reader - OPA0 Warm Status"]
41pub type OPA0WARM_R = crate::BitReader<bool>;
42#[doc = "Field `OPA1WARM` reader - OPA1 Warm Status"]
43pub type OPA1WARM_R = crate::BitReader<bool>;
44#[doc = "Field `OPA2WARM` reader - OPA2 Warm Status"]
45pub type OPA2WARM_R = crate::BitReader<bool>;
46#[doc = "Field `OPA0OUTVALID` reader - OPA0 Output Valid Status"]
47pub type OPA0OUTVALID_R = crate::BitReader<bool>;
48#[doc = "Field `OPA1OUTVALID` reader - OPA1 Output Valid Status"]
49pub type OPA1OUTVALID_R = crate::BitReader<bool>;
50#[doc = "Field `OPA2OUTVALID` reader - OPA2 Output Valid Status"]
51pub type OPA2OUTVALID_R = crate::BitReader<bool>;
52impl R {
53 #[doc = "Bit 0 - Channel 0 Enabled Status"]
54 #[inline(always)]
55 pub fn ch0ens(&self) -> CH0ENS_R {
56 CH0ENS_R::new((self.bits & 1) != 0)
57 }
58 #[doc = "Bit 1 - Channel 1 Enabled Status"]
59 #[inline(always)]
60 pub fn ch1ens(&self) -> CH1ENS_R {
61 CH1ENS_R::new(((self.bits >> 1) & 1) != 0)
62 }
63 #[doc = "Bit 2 - Channel 0 Buffer Level"]
64 #[inline(always)]
65 pub fn ch0bl(&self) -> CH0BL_R {
66 CH0BL_R::new(((self.bits >> 2) & 1) != 0)
67 }
68 #[doc = "Bit 3 - Channel 1 Buffer Level"]
69 #[inline(always)]
70 pub fn ch1bl(&self) -> CH1BL_R {
71 CH1BL_R::new(((self.bits >> 3) & 1) != 0)
72 }
73 #[doc = "Bit 4 - Channel 0 Warm"]
74 #[inline(always)]
75 pub fn ch0warm(&self) -> CH0WARM_R {
76 CH0WARM_R::new(((self.bits >> 4) & 1) != 0)
77 }
78 #[doc = "Bit 5 - Channel 1 Warm"]
79 #[inline(always)]
80 pub fn ch1warm(&self) -> CH1WARM_R {
81 CH1WARM_R::new(((self.bits >> 5) & 1) != 0)
82 }
83 #[doc = "Bit 16 - OPA0 Bus Conflict Output"]
84 #[inline(always)]
85 pub fn opa0aportconflict(&self) -> OPA0APORTCONFLICT_R {
86 OPA0APORTCONFLICT_R::new(((self.bits >> 16) & 1) != 0)
87 }
88 #[doc = "Bit 17 - OPA1 Bus Conflict Output"]
89 #[inline(always)]
90 pub fn opa1aportconflict(&self) -> OPA1APORTCONFLICT_R {
91 OPA1APORTCONFLICT_R::new(((self.bits >> 17) & 1) != 0)
92 }
93 #[doc = "Bit 18 - OPA2 Bus Conflict Output"]
94 #[inline(always)]
95 pub fn opa2aportconflict(&self) -> OPA2APORTCONFLICT_R {
96 OPA2APORTCONFLICT_R::new(((self.bits >> 18) & 1) != 0)
97 }
98 #[doc = "Bit 20 - OPA0 Enabled Status"]
99 #[inline(always)]
100 pub fn opa0ens(&self) -> OPA0ENS_R {
101 OPA0ENS_R::new(((self.bits >> 20) & 1) != 0)
102 }
103 #[doc = "Bit 21 - OPA1 Enabled Status"]
104 #[inline(always)]
105 pub fn opa1ens(&self) -> OPA1ENS_R {
106 OPA1ENS_R::new(((self.bits >> 21) & 1) != 0)
107 }
108 #[doc = "Bit 22 - OPA2 Enabled Status"]
109 #[inline(always)]
110 pub fn opa2ens(&self) -> OPA2ENS_R {
111 OPA2ENS_R::new(((self.bits >> 22) & 1) != 0)
112 }
113 #[doc = "Bit 24 - OPA0 Warm Status"]
114 #[inline(always)]
115 pub fn opa0warm(&self) -> OPA0WARM_R {
116 OPA0WARM_R::new(((self.bits >> 24) & 1) != 0)
117 }
118 #[doc = "Bit 25 - OPA1 Warm Status"]
119 #[inline(always)]
120 pub fn opa1warm(&self) -> OPA1WARM_R {
121 OPA1WARM_R::new(((self.bits >> 25) & 1) != 0)
122 }
123 #[doc = "Bit 26 - OPA2 Warm Status"]
124 #[inline(always)]
125 pub fn opa2warm(&self) -> OPA2WARM_R {
126 OPA2WARM_R::new(((self.bits >> 26) & 1) != 0)
127 }
128 #[doc = "Bit 28 - OPA0 Output Valid Status"]
129 #[inline(always)]
130 pub fn opa0outvalid(&self) -> OPA0OUTVALID_R {
131 OPA0OUTVALID_R::new(((self.bits >> 28) & 1) != 0)
132 }
133 #[doc = "Bit 29 - OPA1 Output Valid Status"]
134 #[inline(always)]
135 pub fn opa1outvalid(&self) -> OPA1OUTVALID_R {
136 OPA1OUTVALID_R::new(((self.bits >> 29) & 1) != 0)
137 }
138 #[doc = "Bit 30 - OPA2 Output Valid Status"]
139 #[inline(always)]
140 pub fn opa2outvalid(&self) -> OPA2OUTVALID_R {
141 OPA2OUTVALID_R::new(((self.bits >> 30) & 1) != 0)
142 }
143}
144#[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"]
145pub struct STATUS_SPEC;
146impl crate::RegisterSpec for STATUS_SPEC {
147 type Ux = u32;
148}
149#[doc = "`read()` method returns [status::R](R) reader structure"]
150impl crate::Readable for STATUS_SPEC {
151 type Reader = R;
152}
153#[doc = "`reset()` method sets STATUS to value 0x0c"]
154impl crate::Resettable for STATUS_SPEC {
155 #[inline(always)]
156 fn reset_value() -> Self::Ux {
157 0x0c
158 }
159}