efm32pg12b500_pac/msc/
readctrl.rs

1#[doc = "Register `READCTRL` reader"]
2pub struct R(crate::R<READCTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<READCTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<READCTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<READCTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `READCTRL` writer"]
17pub struct W(crate::W<READCTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<READCTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<READCTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<READCTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `IFCDIS` reader - Internal Flash Cache Disable"]
38pub type IFCDIS_R = crate::BitReader<bool>;
39#[doc = "Field `IFCDIS` writer - Internal Flash Cache Disable"]
40pub type IFCDIS_W<'a> = crate::BitWriter<'a, u32, READCTRL_SPEC, bool, 3>;
41#[doc = "Field `AIDIS` reader - Automatic Invalidate Disable"]
42pub type AIDIS_R = crate::BitReader<bool>;
43#[doc = "Field `AIDIS` writer - Automatic Invalidate Disable"]
44pub type AIDIS_W<'a> = crate::BitWriter<'a, u32, READCTRL_SPEC, bool, 4>;
45#[doc = "Field `ICCDIS` reader - Interrupt Context Cache Disable"]
46pub type ICCDIS_R = crate::BitReader<bool>;
47#[doc = "Field `ICCDIS` writer - Interrupt Context Cache Disable"]
48pub type ICCDIS_W<'a> = crate::BitWriter<'a, u32, READCTRL_SPEC, bool, 5>;
49#[doc = "Field `PREFETCH` reader - Prefetch Mode"]
50pub type PREFETCH_R = crate::BitReader<bool>;
51#[doc = "Field `PREFETCH` writer - Prefetch Mode"]
52pub type PREFETCH_W<'a> = crate::BitWriter<'a, u32, READCTRL_SPEC, bool, 8>;
53#[doc = "Field `USEHPROT` reader - AHB_HPROT Mode"]
54pub type USEHPROT_R = crate::BitReader<bool>;
55#[doc = "Field `USEHPROT` writer - AHB_HPROT Mode"]
56pub type USEHPROT_W<'a> = crate::BitWriter<'a, u32, READCTRL_SPEC, bool, 9>;
57#[doc = "Read Mode\n\nValue on reset: 1"]
58#[derive(Clone, Copy, Debug, PartialEq)]
59#[repr(u8)]
60pub enum MODE_A {
61    #[doc = "0: Zero wait-states inserted in fetch or read transfers"]
62    WS0 = 0,
63    #[doc = "1: One wait-state inserted for each fetch or read transfer. See Flash Wait-States table for details"]
64    WS1 = 1,
65    #[doc = "2: Two wait-states inserted for eatch fetch or read transfer. See Flash Wait-States table for details"]
66    WS2 = 2,
67    #[doc = "3: Three wait-states inserted for eatch fetch or read transfer. See Flash Wait-States table for details"]
68    WS3 = 3,
69}
70impl From<MODE_A> for u8 {
71    #[inline(always)]
72    fn from(variant: MODE_A) -> Self {
73        variant as _
74    }
75}
76#[doc = "Field `MODE` reader - Read Mode"]
77pub type MODE_R = crate::FieldReader<u8, MODE_A>;
78impl MODE_R {
79    #[doc = "Get enumerated values variant"]
80    #[inline(always)]
81    pub fn variant(&self) -> MODE_A {
82        match self.bits {
83            0 => MODE_A::WS0,
84            1 => MODE_A::WS1,
85            2 => MODE_A::WS2,
86            3 => MODE_A::WS3,
87            _ => unreachable!(),
88        }
89    }
90    #[doc = "Checks if the value of the field is `WS0`"]
91    #[inline(always)]
92    pub fn is_ws0(&self) -> bool {
93        *self == MODE_A::WS0
94    }
95    #[doc = "Checks if the value of the field is `WS1`"]
96    #[inline(always)]
97    pub fn is_ws1(&self) -> bool {
98        *self == MODE_A::WS1
99    }
100    #[doc = "Checks if the value of the field is `WS2`"]
101    #[inline(always)]
102    pub fn is_ws2(&self) -> bool {
103        *self == MODE_A::WS2
104    }
105    #[doc = "Checks if the value of the field is `WS3`"]
106    #[inline(always)]
107    pub fn is_ws3(&self) -> bool {
108        *self == MODE_A::WS3
109    }
110}
111#[doc = "Field `MODE` writer - Read Mode"]
112pub type MODE_W<'a> = crate::FieldWriterSafe<'a, u32, READCTRL_SPEC, u8, MODE_A, 2, 24>;
113impl<'a> MODE_W<'a> {
114    #[doc = "Zero wait-states inserted in fetch or read transfers"]
115    #[inline(always)]
116    pub fn ws0(self) -> &'a mut W {
117        self.variant(MODE_A::WS0)
118    }
119    #[doc = "One wait-state inserted for each fetch or read transfer. See Flash Wait-States table for details"]
120    #[inline(always)]
121    pub fn ws1(self) -> &'a mut W {
122        self.variant(MODE_A::WS1)
123    }
124    #[doc = "Two wait-states inserted for eatch fetch or read transfer. See Flash Wait-States table for details"]
125    #[inline(always)]
126    pub fn ws2(self) -> &'a mut W {
127        self.variant(MODE_A::WS2)
128    }
129    #[doc = "Three wait-states inserted for eatch fetch or read transfer. See Flash Wait-States table for details"]
130    #[inline(always)]
131    pub fn ws3(self) -> &'a mut W {
132        self.variant(MODE_A::WS3)
133    }
134}
135#[doc = "Field `SCBTP` reader - Suppress Conditional Branch Target Perfetch"]
136pub type SCBTP_R = crate::BitReader<bool>;
137#[doc = "Field `SCBTP` writer - Suppress Conditional Branch Target Perfetch"]
138pub type SCBTP_W<'a> = crate::BitWriter<'a, u32, READCTRL_SPEC, bool, 28>;
139impl R {
140    #[doc = "Bit 3 - Internal Flash Cache Disable"]
141    #[inline(always)]
142    pub fn ifcdis(&self) -> IFCDIS_R {
143        IFCDIS_R::new(((self.bits >> 3) & 1) != 0)
144    }
145    #[doc = "Bit 4 - Automatic Invalidate Disable"]
146    #[inline(always)]
147    pub fn aidis(&self) -> AIDIS_R {
148        AIDIS_R::new(((self.bits >> 4) & 1) != 0)
149    }
150    #[doc = "Bit 5 - Interrupt Context Cache Disable"]
151    #[inline(always)]
152    pub fn iccdis(&self) -> ICCDIS_R {
153        ICCDIS_R::new(((self.bits >> 5) & 1) != 0)
154    }
155    #[doc = "Bit 8 - Prefetch Mode"]
156    #[inline(always)]
157    pub fn prefetch(&self) -> PREFETCH_R {
158        PREFETCH_R::new(((self.bits >> 8) & 1) != 0)
159    }
160    #[doc = "Bit 9 - AHB_HPROT Mode"]
161    #[inline(always)]
162    pub fn usehprot(&self) -> USEHPROT_R {
163        USEHPROT_R::new(((self.bits >> 9) & 1) != 0)
164    }
165    #[doc = "Bits 24:25 - Read Mode"]
166    #[inline(always)]
167    pub fn mode(&self) -> MODE_R {
168        MODE_R::new(((self.bits >> 24) & 3) as u8)
169    }
170    #[doc = "Bit 28 - Suppress Conditional Branch Target Perfetch"]
171    #[inline(always)]
172    pub fn scbtp(&self) -> SCBTP_R {
173        SCBTP_R::new(((self.bits >> 28) & 1) != 0)
174    }
175}
176impl W {
177    #[doc = "Bit 3 - Internal Flash Cache Disable"]
178    #[inline(always)]
179    pub fn ifcdis(&mut self) -> IFCDIS_W {
180        IFCDIS_W::new(self)
181    }
182    #[doc = "Bit 4 - Automatic Invalidate Disable"]
183    #[inline(always)]
184    pub fn aidis(&mut self) -> AIDIS_W {
185        AIDIS_W::new(self)
186    }
187    #[doc = "Bit 5 - Interrupt Context Cache Disable"]
188    #[inline(always)]
189    pub fn iccdis(&mut self) -> ICCDIS_W {
190        ICCDIS_W::new(self)
191    }
192    #[doc = "Bit 8 - Prefetch Mode"]
193    #[inline(always)]
194    pub fn prefetch(&mut self) -> PREFETCH_W {
195        PREFETCH_W::new(self)
196    }
197    #[doc = "Bit 9 - AHB_HPROT Mode"]
198    #[inline(always)]
199    pub fn usehprot(&mut self) -> USEHPROT_W {
200        USEHPROT_W::new(self)
201    }
202    #[doc = "Bits 24:25 - Read Mode"]
203    #[inline(always)]
204    pub fn mode(&mut self) -> MODE_W {
205        MODE_W::new(self)
206    }
207    #[doc = "Bit 28 - Suppress Conditional Branch Target Perfetch"]
208    #[inline(always)]
209    pub fn scbtp(&mut self) -> SCBTP_W {
210        SCBTP_W::new(self)
211    }
212    #[doc = "Writes raw bits to the register."]
213    #[inline(always)]
214    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
215        self.0.bits(bits);
216        self
217    }
218}
219#[doc = "Read Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [readctrl](index.html) module"]
220pub struct READCTRL_SPEC;
221impl crate::RegisterSpec for READCTRL_SPEC {
222    type Ux = u32;
223}
224#[doc = "`read()` method returns [readctrl::R](R) reader structure"]
225impl crate::Readable for READCTRL_SPEC {
226    type Reader = R;
227}
228#[doc = "`write(|w| ..)` method takes [readctrl::W](W) writer structure"]
229impl crate::Writable for READCTRL_SPEC {
230    type Writer = W;
231}
232#[doc = "`reset()` method sets READCTRL to value 0x0100_0100"]
233impl crate::Resettable for READCTRL_SPEC {
234    #[inline(always)]
235    fn reset_value() -> Self::Ux {
236        0x0100_0100
237    }
238}
efm32pg12b500_pac/msc/readctrl.rs

efm32pg12b500_pac/msc/
readctrl.rs
