efm32pg12b500_pac/msc/
ctrl.rs

1#[doc = "Register `CTRL` reader"]
2pub struct R(crate::R<CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CTRL` writer"]
17pub struct W(crate::W<CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `ADDRFAULTEN` reader - Invalid Address Bus Fault Response Enable"]
38pub type ADDRFAULTEN_R = crate::BitReader<bool>;
39#[doc = "Field `ADDRFAULTEN` writer - Invalid Address Bus Fault Response Enable"]
40pub type ADDRFAULTEN_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 0>;
41#[doc = "Field `CLKDISFAULTEN` reader - Clock-disabled Bus Fault Response Enable"]
42pub type CLKDISFAULTEN_R = crate::BitReader<bool>;
43#[doc = "Field `CLKDISFAULTEN` writer - Clock-disabled Bus Fault Response Enable"]
44pub type CLKDISFAULTEN_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 1>;
45#[doc = "Field `PWRUPONDEMAND` reader - Power Up on Demand During Wake Up"]
46pub type PWRUPONDEMAND_R = crate::BitReader<bool>;
47#[doc = "Field `PWRUPONDEMAND` writer - Power Up on Demand During Wake Up"]
48pub type PWRUPONDEMAND_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 2>;
49#[doc = "Field `IFCREADCLEAR` reader - IFC Read Clears IF"]
50pub type IFCREADCLEAR_R = crate::BitReader<bool>;
51#[doc = "Field `IFCREADCLEAR` writer - IFC Read Clears IF"]
52pub type IFCREADCLEAR_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 3>;
53#[doc = "Field `TIMEOUTFAULTEN` reader - Timeout Bus Fault Response Enable"]
54pub type TIMEOUTFAULTEN_R = crate::BitReader<bool>;
55#[doc = "Field `TIMEOUTFAULTEN` writer - Timeout Bus Fault Response Enable"]
56pub type TIMEOUTFAULTEN_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 4>;
57impl R {
58    #[doc = "Bit 0 - Invalid Address Bus Fault Response Enable"]
59    #[inline(always)]
60    pub fn addrfaulten(&self) -> ADDRFAULTEN_R {
61        ADDRFAULTEN_R::new((self.bits & 1) != 0)
62    }
63    #[doc = "Bit 1 - Clock-disabled Bus Fault Response Enable"]
64    #[inline(always)]
65    pub fn clkdisfaulten(&self) -> CLKDISFAULTEN_R {
66        CLKDISFAULTEN_R::new(((self.bits >> 1) & 1) != 0)
67    }
68    #[doc = "Bit 2 - Power Up on Demand During Wake Up"]
69    #[inline(always)]
70    pub fn pwrupondemand(&self) -> PWRUPONDEMAND_R {
71        PWRUPONDEMAND_R::new(((self.bits >> 2) & 1) != 0)
72    }
73    #[doc = "Bit 3 - IFC Read Clears IF"]
74    #[inline(always)]
75    pub fn ifcreadclear(&self) -> IFCREADCLEAR_R {
76        IFCREADCLEAR_R::new(((self.bits >> 3) & 1) != 0)
77    }
78    #[doc = "Bit 4 - Timeout Bus Fault Response Enable"]
79    #[inline(always)]
80    pub fn timeoutfaulten(&self) -> TIMEOUTFAULTEN_R {
81        TIMEOUTFAULTEN_R::new(((self.bits >> 4) & 1) != 0)
82    }
83}
84impl W {
85    #[doc = "Bit 0 - Invalid Address Bus Fault Response Enable"]
86    #[inline(always)]
87    pub fn addrfaulten(&mut self) -> ADDRFAULTEN_W {
88        ADDRFAULTEN_W::new(self)
89    }
90    #[doc = "Bit 1 - Clock-disabled Bus Fault Response Enable"]
91    #[inline(always)]
92    pub fn clkdisfaulten(&mut self) -> CLKDISFAULTEN_W {
93        CLKDISFAULTEN_W::new(self)
94    }
95    #[doc = "Bit 2 - Power Up on Demand During Wake Up"]
96    #[inline(always)]
97    pub fn pwrupondemand(&mut self) -> PWRUPONDEMAND_W {
98        PWRUPONDEMAND_W::new(self)
99    }
100    #[doc = "Bit 3 - IFC Read Clears IF"]
101    #[inline(always)]
102    pub fn ifcreadclear(&mut self) -> IFCREADCLEAR_W {
103        IFCREADCLEAR_W::new(self)
104    }
105    #[doc = "Bit 4 - Timeout Bus Fault Response Enable"]
106    #[inline(always)]
107    pub fn timeoutfaulten(&mut self) -> TIMEOUTFAULTEN_W {
108        TIMEOUTFAULTEN_W::new(self)
109    }
110    #[doc = "Writes raw bits to the register."]
111    #[inline(always)]
112    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
113        self.0.bits(bits);
114        self
115    }
116}
117#[doc = "Memory System Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
118pub struct CTRL_SPEC;
119impl crate::RegisterSpec for CTRL_SPEC {
120    type Ux = u32;
121}
122#[doc = "`read()` method returns [ctrl::R](R) reader structure"]
123impl crate::Readable for CTRL_SPEC {
124    type Reader = R;
125}
126#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
127impl crate::Writable for CTRL_SPEC {
128    type Writer = W;
129}
130#[doc = "`reset()` method sets CTRL to value 0x01"]
131impl crate::Resettable for CTRL_SPEC {
132    #[inline(always)]
133    fn reset_value() -> Self::Ux {
134        0x01
135    }
136}
efm32pg12b500_pac/msc/ctrl.rs

efm32pg12b500_pac/msc/
ctrl.rs
