efm32pg12b500_pac/vdac0/
if_.rs

1#[doc = "Register `IF` reader"]
2pub struct R(crate::R<IF_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<IF_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<IF_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<IF_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `CH0CD` reader - Channel 0 Conversion Done Interrupt Flag"]
17pub type CH0CD_R = crate::BitReader<bool>;
18#[doc = "Field `CH1CD` reader - Channel 1 Conversion Done Interrupt Flag"]
19pub type CH1CD_R = crate::BitReader<bool>;
20#[doc = "Field `CH0OF` reader - Channel 0 Data Overflow Interrupt Flag"]
21pub type CH0OF_R = crate::BitReader<bool>;
22#[doc = "Field `CH1OF` reader - Channel 1 Data Overflow Interrupt Flag"]
23pub type CH1OF_R = crate::BitReader<bool>;
24#[doc = "Field `CH0UF` reader - Channel 0 Data Underflow Interrupt Flag"]
25pub type CH0UF_R = crate::BitReader<bool>;
26#[doc = "Field `CH1UF` reader - Channel 1 Data Underflow Interrupt Flag"]
27pub type CH1UF_R = crate::BitReader<bool>;
28#[doc = "Field `CH0BL` reader - Channel 0 Buffer Level Interrupt Flag"]
29pub type CH0BL_R = crate::BitReader<bool>;
30#[doc = "Field `CH1BL` reader - Channel 1 Buffer Level Interrupt Flag"]
31pub type CH1BL_R = crate::BitReader<bool>;
32#[doc = "Field `EM23ERR` reader - EM2/3 Entry Error Flag"]
33pub type EM23ERR_R = crate::BitReader<bool>;
34#[doc = "Field `OPA0APORTCONFLICT` reader - OPA0 Bus Conflict Output Interrupt Flag"]
35pub type OPA0APORTCONFLICT_R = crate::BitReader<bool>;
36#[doc = "Field `OPA1APORTCONFLICT` reader - OPA1 Bus Conflict Output Interrupt Flag"]
37pub type OPA1APORTCONFLICT_R = crate::BitReader<bool>;
38#[doc = "Field `OPA2APORTCONFLICT` reader - OPA2 Bus Conflict Output Interrupt Flag"]
39pub type OPA2APORTCONFLICT_R = crate::BitReader<bool>;
40#[doc = "Field `OPA0PRSTIMEDERR` reader - OPA0 PRS Trigger Mode Error Interrupt Flag"]
41pub type OPA0PRSTIMEDERR_R = crate::BitReader<bool>;
42#[doc = "Field `OPA1PRSTIMEDERR` reader - OPA1 PRS Trigger Mode Error Interrupt Flag"]
43pub type OPA1PRSTIMEDERR_R = crate::BitReader<bool>;
44#[doc = "Field `OPA2PRSTIMEDERR` reader - OPA2 PRS Trigger Mode Error Interrupt Flag"]
45pub type OPA2PRSTIMEDERR_R = crate::BitReader<bool>;
46#[doc = "Field `OPA0OUTVALID` reader - OPA0 Output Valid Interrupt Flag"]
47pub type OPA0OUTVALID_R = crate::BitReader<bool>;
48#[doc = "Field `OPA1OUTVALID` reader - OPA1 Output Valid Interrupt Flag"]
49pub type OPA1OUTVALID_R = crate::BitReader<bool>;
50#[doc = "Field `OPA2OUTVALID` reader - OPA3 Output Valid Interrupt Flag"]
51pub type OPA2OUTVALID_R = crate::BitReader<bool>;
52impl R {
53    #[doc = "Bit 0 - Channel 0 Conversion Done Interrupt Flag"]
54    #[inline(always)]
55    pub fn ch0cd(&self) -> CH0CD_R {
56        CH0CD_R::new((self.bits & 1) != 0)
57    }
58    #[doc = "Bit 1 - Channel 1 Conversion Done Interrupt Flag"]
59    #[inline(always)]
60    pub fn ch1cd(&self) -> CH1CD_R {
61        CH1CD_R::new(((self.bits >> 1) & 1) != 0)
62    }
63    #[doc = "Bit 2 - Channel 0 Data Overflow Interrupt Flag"]
64    #[inline(always)]
65    pub fn ch0of(&self) -> CH0OF_R {
66        CH0OF_R::new(((self.bits >> 2) & 1) != 0)
67    }
68    #[doc = "Bit 3 - Channel 1 Data Overflow Interrupt Flag"]
69    #[inline(always)]
70    pub fn ch1of(&self) -> CH1OF_R {
71        CH1OF_R::new(((self.bits >> 3) & 1) != 0)
72    }
73    #[doc = "Bit 4 - Channel 0 Data Underflow Interrupt Flag"]
74    #[inline(always)]
75    pub fn ch0uf(&self) -> CH0UF_R {
76        CH0UF_R::new(((self.bits >> 4) & 1) != 0)
77    }
78    #[doc = "Bit 5 - Channel 1 Data Underflow Interrupt Flag"]
79    #[inline(always)]
80    pub fn ch1uf(&self) -> CH1UF_R {
81        CH1UF_R::new(((self.bits >> 5) & 1) != 0)
82    }
83    #[doc = "Bit 6 - Channel 0 Buffer Level Interrupt Flag"]
84    #[inline(always)]
85    pub fn ch0bl(&self) -> CH0BL_R {
86        CH0BL_R::new(((self.bits >> 6) & 1) != 0)
87    }
88    #[doc = "Bit 7 - Channel 1 Buffer Level Interrupt Flag"]
89    #[inline(always)]
90    pub fn ch1bl(&self) -> CH1BL_R {
91        CH1BL_R::new(((self.bits >> 7) & 1) != 0)
92    }
93    #[doc = "Bit 15 - EM2/3 Entry Error Flag"]
94    #[inline(always)]
95    pub fn em23err(&self) -> EM23ERR_R {
96        EM23ERR_R::new(((self.bits >> 15) & 1) != 0)
97    }
98    #[doc = "Bit 16 - OPA0 Bus Conflict Output Interrupt Flag"]
99    #[inline(always)]
100    pub fn opa0aportconflict(&self) -> OPA0APORTCONFLICT_R {
101        OPA0APORTCONFLICT_R::new(((self.bits >> 16) & 1) != 0)
102    }
103    #[doc = "Bit 17 - OPA1 Bus Conflict Output Interrupt Flag"]
104    #[inline(always)]
105    pub fn opa1aportconflict(&self) -> OPA1APORTCONFLICT_R {
106        OPA1APORTCONFLICT_R::new(((self.bits >> 17) & 1) != 0)
107    }
108    #[doc = "Bit 18 - OPA2 Bus Conflict Output Interrupt Flag"]
109    #[inline(always)]
110    pub fn opa2aportconflict(&self) -> OPA2APORTCONFLICT_R {
111        OPA2APORTCONFLICT_R::new(((self.bits >> 18) & 1) != 0)
112    }
113    #[doc = "Bit 20 - OPA0 PRS Trigger Mode Error Interrupt Flag"]
114    #[inline(always)]
115    pub fn opa0prstimederr(&self) -> OPA0PRSTIMEDERR_R {
116        OPA0PRSTIMEDERR_R::new(((self.bits >> 20) & 1) != 0)
117    }
118    #[doc = "Bit 21 - OPA1 PRS Trigger Mode Error Interrupt Flag"]
119    #[inline(always)]
120    pub fn opa1prstimederr(&self) -> OPA1PRSTIMEDERR_R {
121        OPA1PRSTIMEDERR_R::new(((self.bits >> 21) & 1) != 0)
122    }
123    #[doc = "Bit 22 - OPA2 PRS Trigger Mode Error Interrupt Flag"]
124    #[inline(always)]
125    pub fn opa2prstimederr(&self) -> OPA2PRSTIMEDERR_R {
126        OPA2PRSTIMEDERR_R::new(((self.bits >> 22) & 1) != 0)
127    }
128    #[doc = "Bit 28 - OPA0 Output Valid Interrupt Flag"]
129    #[inline(always)]
130    pub fn opa0outvalid(&self) -> OPA0OUTVALID_R {
131        OPA0OUTVALID_R::new(((self.bits >> 28) & 1) != 0)
132    }
133    #[doc = "Bit 29 - OPA1 Output Valid Interrupt Flag"]
134    #[inline(always)]
135    pub fn opa1outvalid(&self) -> OPA1OUTVALID_R {
136        OPA1OUTVALID_R::new(((self.bits >> 29) & 1) != 0)
137    }
138    #[doc = "Bit 30 - OPA3 Output Valid Interrupt Flag"]
139    #[inline(always)]
140    pub fn opa2outvalid(&self) -> OPA2OUTVALID_R {
141        OPA2OUTVALID_R::new(((self.bits >> 30) & 1) != 0)
142    }
143}
144#[doc = "Interrupt Flag Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [if_](index.html) module"]
145pub struct IF_SPEC;
146impl crate::RegisterSpec for IF_SPEC {
147    type Ux = u32;
148}
149#[doc = "`read()` method returns [if_::R](R) reader structure"]
150impl crate::Readable for IF_SPEC {
151    type Reader = R;
152}
153#[doc = "`reset()` method sets IF to value 0xc0"]
154impl crate::Resettable for IF_SPEC {
155    #[inline(always)]
156    fn reset_value() -> Self::Ux {
157        0xc0
158    }
159}
efm32pg12b500_pac/vdac0/if_.rs

efm32pg12b500_pac/vdac0/
if_.rs
