efm32pg12b500_pac/smu/
ppupatd1.rs1#[doc = "Register `PPUPATD1` reader"]
2pub struct R(crate::R<PPUPATD1_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<PPUPATD1_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<PPUPATD1_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<PPUPATD1_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `PPUPATD1` writer"]
17pub struct W(crate::W<PPUPATD1_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<PPUPATD1_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<PPUPATD1_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<PPUPATD1_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `RMU` reader - Reset Management Unit access control bit"]
38pub type RMU_R = crate::BitReader<bool>;
39#[doc = "Field `RMU` writer - Reset Management Unit access control bit"]
40pub type RMU_W<'a> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, 1>;
41#[doc = "Field `RTCC` reader - Real-Time Counter and Calendar access control bit"]
42pub type RTCC_R = crate::BitReader<bool>;
43#[doc = "Field `RTCC` writer - Real-Time Counter and Calendar access control bit"]
44pub type RTCC_W<'a> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, 2>;
45#[doc = "Field `SMU` reader - Security Management Unit access control bit"]
46pub type SMU_R = crate::BitReader<bool>;
47#[doc = "Field `SMU` writer - Security Management Unit access control bit"]
48pub type SMU_W<'a> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, 3>;
49#[doc = "Field `TIMER0` reader - Timer 0 access control bit"]
50pub type TIMER0_R = crate::BitReader<bool>;
51#[doc = "Field `TIMER0` writer - Timer 0 access control bit"]
52pub type TIMER0_W<'a> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, 5>;
53#[doc = "Field `TIMER1` reader - Timer 1 access control bit"]
54pub type TIMER1_R = crate::BitReader<bool>;
55#[doc = "Field `TIMER1` writer - Timer 1 access control bit"]
56pub type TIMER1_W<'a> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, 6>;
57#[doc = "Field `TRNG0` reader - True Random Number Generator 0 access control bit"]
58pub type TRNG0_R = crate::BitReader<bool>;
59#[doc = "Field `TRNG0` writer - True Random Number Generator 0 access control bit"]
60pub type TRNG0_W<'a> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, 7>;
61#[doc = "Field `USART0` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit"]
62pub type USART0_R = crate::BitReader<bool>;
63#[doc = "Field `USART0` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit"]
64pub type USART0_W<'a> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, 8>;
65#[doc = "Field `USART1` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit"]
66pub type USART1_R = crate::BitReader<bool>;
67#[doc = "Field `USART1` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit"]
68pub type USART1_W<'a> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, 9>;
69#[doc = "Field `USART2` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit"]
70pub type USART2_R = crate::BitReader<bool>;
71#[doc = "Field `USART2` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit"]
72pub type USART2_W<'a> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, 10>;
73#[doc = "Field `USART3` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit"]
74pub type USART3_R = crate::BitReader<bool>;
75#[doc = "Field `USART3` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit"]
76pub type USART3_W<'a> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, 11>;
77#[doc = "Field `WDOG0` reader - Watchdog 0 access control bit"]
78pub type WDOG0_R = crate::BitReader<bool>;
79#[doc = "Field `WDOG0` writer - Watchdog 0 access control bit"]
80pub type WDOG0_W<'a> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, 12>;
81#[doc = "Field `WDOG1` reader - Watchdog 1 access control bit"]
82pub type WDOG1_R = crate::BitReader<bool>;
83#[doc = "Field `WDOG1` writer - Watchdog 1 access control bit"]
84pub type WDOG1_W<'a> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, 13>;
85#[doc = "Field `WTIMER0` reader - Wide Timer 0 access control bit"]
86pub type WTIMER0_R = crate::BitReader<bool>;
87#[doc = "Field `WTIMER0` writer - Wide Timer 0 access control bit"]
88pub type WTIMER0_W<'a> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, 14>;
89#[doc = "Field `WTIMER1` reader - Wide Timer 1 access control bit"]
90pub type WTIMER1_R = crate::BitReader<bool>;
91#[doc = "Field `WTIMER1` writer - Wide Timer 1 access control bit"]
92pub type WTIMER1_W<'a> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, 15>;
93impl R {
94 #[doc = "Bit 1 - Reset Management Unit access control bit"]
95 #[inline(always)]
96 pub fn rmu(&self) -> RMU_R {
97 RMU_R::new(((self.bits >> 1) & 1) != 0)
98 }
99 #[doc = "Bit 2 - Real-Time Counter and Calendar access control bit"]
100 #[inline(always)]
101 pub fn rtcc(&self) -> RTCC_R {
102 RTCC_R::new(((self.bits >> 2) & 1) != 0)
103 }
104 #[doc = "Bit 3 - Security Management Unit access control bit"]
105 #[inline(always)]
106 pub fn smu(&self) -> SMU_R {
107 SMU_R::new(((self.bits >> 3) & 1) != 0)
108 }
109 #[doc = "Bit 5 - Timer 0 access control bit"]
110 #[inline(always)]
111 pub fn timer0(&self) -> TIMER0_R {
112 TIMER0_R::new(((self.bits >> 5) & 1) != 0)
113 }
114 #[doc = "Bit 6 - Timer 1 access control bit"]
115 #[inline(always)]
116 pub fn timer1(&self) -> TIMER1_R {
117 TIMER1_R::new(((self.bits >> 6) & 1) != 0)
118 }
119 #[doc = "Bit 7 - True Random Number Generator 0 access control bit"]
120 #[inline(always)]
121 pub fn trng0(&self) -> TRNG0_R {
122 TRNG0_R::new(((self.bits >> 7) & 1) != 0)
123 }
124 #[doc = "Bit 8 - Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit"]
125 #[inline(always)]
126 pub fn usart0(&self) -> USART0_R {
127 USART0_R::new(((self.bits >> 8) & 1) != 0)
128 }
129 #[doc = "Bit 9 - Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit"]
130 #[inline(always)]
131 pub fn usart1(&self) -> USART1_R {
132 USART1_R::new(((self.bits >> 9) & 1) != 0)
133 }
134 #[doc = "Bit 10 - Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit"]
135 #[inline(always)]
136 pub fn usart2(&self) -> USART2_R {
137 USART2_R::new(((self.bits >> 10) & 1) != 0)
138 }
139 #[doc = "Bit 11 - Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit"]
140 #[inline(always)]
141 pub fn usart3(&self) -> USART3_R {
142 USART3_R::new(((self.bits >> 11) & 1) != 0)
143 }
144 #[doc = "Bit 12 - Watchdog 0 access control bit"]
145 #[inline(always)]
146 pub fn wdog0(&self) -> WDOG0_R {
147 WDOG0_R::new(((self.bits >> 12) & 1) != 0)
148 }
149 #[doc = "Bit 13 - Watchdog 1 access control bit"]
150 #[inline(always)]
151 pub fn wdog1(&self) -> WDOG1_R {
152 WDOG1_R::new(((self.bits >> 13) & 1) != 0)
153 }
154 #[doc = "Bit 14 - Wide Timer 0 access control bit"]
155 #[inline(always)]
156 pub fn wtimer0(&self) -> WTIMER0_R {
157 WTIMER0_R::new(((self.bits >> 14) & 1) != 0)
158 }
159 #[doc = "Bit 15 - Wide Timer 1 access control bit"]
160 #[inline(always)]
161 pub fn wtimer1(&self) -> WTIMER1_R {
162 WTIMER1_R::new(((self.bits >> 15) & 1) != 0)
163 }
164}
165impl W {
166 #[doc = "Bit 1 - Reset Management Unit access control bit"]
167 #[inline(always)]
168 pub fn rmu(&mut self) -> RMU_W {
169 RMU_W::new(self)
170 }
171 #[doc = "Bit 2 - Real-Time Counter and Calendar access control bit"]
172 #[inline(always)]
173 pub fn rtcc(&mut self) -> RTCC_W {
174 RTCC_W::new(self)
175 }
176 #[doc = "Bit 3 - Security Management Unit access control bit"]
177 #[inline(always)]
178 pub fn smu(&mut self) -> SMU_W {
179 SMU_W::new(self)
180 }
181 #[doc = "Bit 5 - Timer 0 access control bit"]
182 #[inline(always)]
183 pub fn timer0(&mut self) -> TIMER0_W {
184 TIMER0_W::new(self)
185 }
186 #[doc = "Bit 6 - Timer 1 access control bit"]
187 #[inline(always)]
188 pub fn timer1(&mut self) -> TIMER1_W {
189 TIMER1_W::new(self)
190 }
191 #[doc = "Bit 7 - True Random Number Generator 0 access control bit"]
192 #[inline(always)]
193 pub fn trng0(&mut self) -> TRNG0_W {
194 TRNG0_W::new(self)
195 }
196 #[doc = "Bit 8 - Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit"]
197 #[inline(always)]
198 pub fn usart0(&mut self) -> USART0_W {
199 USART0_W::new(self)
200 }
201 #[doc = "Bit 9 - Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit"]
202 #[inline(always)]
203 pub fn usart1(&mut self) -> USART1_W {
204 USART1_W::new(self)
205 }
206 #[doc = "Bit 10 - Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit"]
207 #[inline(always)]
208 pub fn usart2(&mut self) -> USART2_W {
209 USART2_W::new(self)
210 }
211 #[doc = "Bit 11 - Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit"]
212 #[inline(always)]
213 pub fn usart3(&mut self) -> USART3_W {
214 USART3_W::new(self)
215 }
216 #[doc = "Bit 12 - Watchdog 0 access control bit"]
217 #[inline(always)]
218 pub fn wdog0(&mut self) -> WDOG0_W {
219 WDOG0_W::new(self)
220 }
221 #[doc = "Bit 13 - Watchdog 1 access control bit"]
222 #[inline(always)]
223 pub fn wdog1(&mut self) -> WDOG1_W {
224 WDOG1_W::new(self)
225 }
226 #[doc = "Bit 14 - Wide Timer 0 access control bit"]
227 #[inline(always)]
228 pub fn wtimer0(&mut self) -> WTIMER0_W {
229 WTIMER0_W::new(self)
230 }
231 #[doc = "Bit 15 - Wide Timer 1 access control bit"]
232 #[inline(always)]
233 pub fn wtimer1(&mut self) -> WTIMER1_W {
234 WTIMER1_W::new(self)
235 }
236 #[doc = "Writes raw bits to the register."]
237 #[inline(always)]
238 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
239 self.0.bits(bits);
240 self
241 }
242}
243#[doc = "PPU Privilege Access Type Descriptor 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ppupatd1](index.html) module"]
244pub struct PPUPATD1_SPEC;
245impl crate::RegisterSpec for PPUPATD1_SPEC {
246 type Ux = u32;
247}
248#[doc = "`read()` method returns [ppupatd1::R](R) reader structure"]
249impl crate::Readable for PPUPATD1_SPEC {
250 type Reader = R;
251}
252#[doc = "`write(|w| ..)` method takes [ppupatd1::W](W) writer structure"]
253impl crate::Writable for PPUPATD1_SPEC {
254 type Writer = W;
255}
256#[doc = "`reset()` method sets PPUPATD1 to value 0"]
257impl crate::Resettable for PPUPATD1_SPEC {
258 #[inline(always)]
259 fn reset_value() -> Self::Ux {
260 0
261 }
262}