1#[doc = "Register `PPUPATD0` reader"]
2pub struct R(crate::R<PPUPATD0_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<PPUPATD0_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<PPUPATD0_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<PPUPATD0_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `PPUPATD0` writer"]
17pub struct W(crate::W<PPUPATD0_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<PPUPATD0_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<PPUPATD0_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<PPUPATD0_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `ACMP0` reader - Analog Comparator 0 access control bit"]
38pub type ACMP0_R = crate::BitReader<bool>;
39#[doc = "Field `ACMP0` writer - Analog Comparator 0 access control bit"]
40pub type ACMP0_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 0>;
41#[doc = "Field `ACMP1` reader - Analog Comparator 1 access control bit"]
42pub type ACMP1_R = crate::BitReader<bool>;
43#[doc = "Field `ACMP1` writer - Analog Comparator 1 access control bit"]
44pub type ACMP1_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 1>;
45#[doc = "Field `ADC0` reader - Analog to Digital Converter 0 access control bit"]
46pub type ADC0_R = crate::BitReader<bool>;
47#[doc = "Field `ADC0` writer - Analog to Digital Converter 0 access control bit"]
48pub type ADC0_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 2>;
49#[doc = "Field `CMU` reader - Clock Management Unit access control bit"]
50pub type CMU_R = crate::BitReader<bool>;
51#[doc = "Field `CMU` writer - Clock Management Unit access control bit"]
52pub type CMU_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 5>;
53#[doc = "Field `CRYOTIMER` reader - CRYOTIMER access control bit"]
54pub type CRYOTIMER_R = crate::BitReader<bool>;
55#[doc = "Field `CRYOTIMER` writer - CRYOTIMER access control bit"]
56pub type CRYOTIMER_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 7>;
57#[doc = "Field `CRYPTO0` reader - Advanced Encryption Standard Accelerator 0 access control bit"]
58pub type CRYPTO0_R = crate::BitReader<bool>;
59#[doc = "Field `CRYPTO0` writer - Advanced Encryption Standard Accelerator 0 access control bit"]
60pub type CRYPTO0_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 8>;
61#[doc = "Field `CRYPTO1` reader - Advanced Encryption Standard Accelerator 1 access control bit"]
62pub type CRYPTO1_R = crate::BitReader<bool>;
63#[doc = "Field `CRYPTO1` writer - Advanced Encryption Standard Accelerator 1 access control bit"]
64pub type CRYPTO1_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 9>;
65#[doc = "Field `CSEN` reader - Capacitive touch sense module access control bit"]
66pub type CSEN_R = crate::BitReader<bool>;
67#[doc = "Field `CSEN` writer - Capacitive touch sense module access control bit"]
68pub type CSEN_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 10>;
69#[doc = "Field `VDAC0` reader - Digital to Analog Converter 0 access control bit"]
70pub type VDAC0_R = crate::BitReader<bool>;
71#[doc = "Field `VDAC0` writer - Digital to Analog Converter 0 access control bit"]
72pub type VDAC0_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 11>;
73#[doc = "Field `PRS` reader - Peripheral Reflex System access control bit"]
74pub type PRS_R = crate::BitReader<bool>;
75#[doc = "Field `PRS` writer - Peripheral Reflex System access control bit"]
76pub type PRS_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 12>;
77#[doc = "Field `EMU` reader - Energy Management Unit access control bit"]
78pub type EMU_R = crate::BitReader<bool>;
79#[doc = "Field `EMU` writer - Energy Management Unit access control bit"]
80pub type EMU_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 13>;
81#[doc = "Field `FPUEH` reader - FPU Exception Handler access control bit"]
82pub type FPUEH_R = crate::BitReader<bool>;
83#[doc = "Field `FPUEH` writer - FPU Exception Handler access control bit"]
84pub type FPUEH_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 14>;
85#[doc = "Field `GPCRC` reader - General Purpose CRC access control bit"]
86pub type GPCRC_R = crate::BitReader<bool>;
87#[doc = "Field `GPCRC` writer - General Purpose CRC access control bit"]
88pub type GPCRC_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 16>;
89#[doc = "Field `GPIO` reader - General purpose Input/Output access control bit"]
90pub type GPIO_R = crate::BitReader<bool>;
91#[doc = "Field `GPIO` writer - General purpose Input/Output access control bit"]
92pub type GPIO_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 17>;
93#[doc = "Field `I2C0` reader - I2C 0 access control bit"]
94pub type I2C0_R = crate::BitReader<bool>;
95#[doc = "Field `I2C0` writer - I2C 0 access control bit"]
96pub type I2C0_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 18>;
97#[doc = "Field `I2C1` reader - I2C 1 access control bit"]
98pub type I2C1_R = crate::BitReader<bool>;
99#[doc = "Field `I2C1` writer - I2C 1 access control bit"]
100pub type I2C1_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 19>;
101#[doc = "Field `IDAC0` reader - Current Digital to Analog Converter 0 access control bit"]
102pub type IDAC0_R = crate::BitReader<bool>;
103#[doc = "Field `IDAC0` writer - Current Digital to Analog Converter 0 access control bit"]
104pub type IDAC0_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 20>;
105#[doc = "Field `MSC` reader - Memory System Controller access control bit"]
106pub type MSC_R = crate::BitReader<bool>;
107#[doc = "Field `MSC` writer - Memory System Controller access control bit"]
108pub type MSC_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 21>;
109#[doc = "Field `LDMA` reader - Linked Direct Memory Access Controller access control bit"]
110pub type LDMA_R = crate::BitReader<bool>;
111#[doc = "Field `LDMA` writer - Linked Direct Memory Access Controller access control bit"]
112pub type LDMA_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 22>;
113#[doc = "Field `LESENSE` reader - Low Energy Sensor Interface access control bit"]
114pub type LESENSE_R = crate::BitReader<bool>;
115#[doc = "Field `LESENSE` writer - Low Energy Sensor Interface access control bit"]
116pub type LESENSE_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 23>;
117#[doc = "Field `LETIMER0` reader - Low Energy Timer 0 access control bit"]
118pub type LETIMER0_R = crate::BitReader<bool>;
119#[doc = "Field `LETIMER0` writer - Low Energy Timer 0 access control bit"]
120pub type LETIMER0_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 24>;
121#[doc = "Field `LEUART0` reader - Low Energy UART 0 access control bit"]
122pub type LEUART0_R = crate::BitReader<bool>;
123#[doc = "Field `LEUART0` writer - Low Energy UART 0 access control bit"]
124pub type LEUART0_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 25>;
125#[doc = "Field `PCNT0` reader - Pulse Counter 0 access control bit"]
126pub type PCNT0_R = crate::BitReader<bool>;
127#[doc = "Field `PCNT0` writer - Pulse Counter 0 access control bit"]
128pub type PCNT0_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 27>;
129#[doc = "Field `PCNT1` reader - Pulse Counter 1 access control bit"]
130pub type PCNT1_R = crate::BitReader<bool>;
131#[doc = "Field `PCNT1` writer - Pulse Counter 1 access control bit"]
132pub type PCNT1_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 28>;
133#[doc = "Field `PCNT2` reader - Pulse Counter 2 access control bit"]
134pub type PCNT2_R = crate::BitReader<bool>;
135#[doc = "Field `PCNT2` writer - Pulse Counter 2 access control bit"]
136pub type PCNT2_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 29>;
137impl R {
138 #[doc = "Bit 0 - Analog Comparator 0 access control bit"]
139 #[inline(always)]
140 pub fn acmp0(&self) -> ACMP0_R {
141 ACMP0_R::new((self.bits & 1) != 0)
142 }
143 #[doc = "Bit 1 - Analog Comparator 1 access control bit"]
144 #[inline(always)]
145 pub fn acmp1(&self) -> ACMP1_R {
146 ACMP1_R::new(((self.bits >> 1) & 1) != 0)
147 }
148 #[doc = "Bit 2 - Analog to Digital Converter 0 access control bit"]
149 #[inline(always)]
150 pub fn adc0(&self) -> ADC0_R {
151 ADC0_R::new(((self.bits >> 2) & 1) != 0)
152 }
153 #[doc = "Bit 5 - Clock Management Unit access control bit"]
154 #[inline(always)]
155 pub fn cmu(&self) -> CMU_R {
156 CMU_R::new(((self.bits >> 5) & 1) != 0)
157 }
158 #[doc = "Bit 7 - CRYOTIMER access control bit"]
159 #[inline(always)]
160 pub fn cryotimer(&self) -> CRYOTIMER_R {
161 CRYOTIMER_R::new(((self.bits >> 7) & 1) != 0)
162 }
163 #[doc = "Bit 8 - Advanced Encryption Standard Accelerator 0 access control bit"]
164 #[inline(always)]
165 pub fn crypto0(&self) -> CRYPTO0_R {
166 CRYPTO0_R::new(((self.bits >> 8) & 1) != 0)
167 }
168 #[doc = "Bit 9 - Advanced Encryption Standard Accelerator 1 access control bit"]
169 #[inline(always)]
170 pub fn crypto1(&self) -> CRYPTO1_R {
171 CRYPTO1_R::new(((self.bits >> 9) & 1) != 0)
172 }
173 #[doc = "Bit 10 - Capacitive touch sense module access control bit"]
174 #[inline(always)]
175 pub fn csen(&self) -> CSEN_R {
176 CSEN_R::new(((self.bits >> 10) & 1) != 0)
177 }
178 #[doc = "Bit 11 - Digital to Analog Converter 0 access control bit"]
179 #[inline(always)]
180 pub fn vdac0(&self) -> VDAC0_R {
181 VDAC0_R::new(((self.bits >> 11) & 1) != 0)
182 }
183 #[doc = "Bit 12 - Peripheral Reflex System access control bit"]
184 #[inline(always)]
185 pub fn prs(&self) -> PRS_R {
186 PRS_R::new(((self.bits >> 12) & 1) != 0)
187 }
188 #[doc = "Bit 13 - Energy Management Unit access control bit"]
189 #[inline(always)]
190 pub fn emu(&self) -> EMU_R {
191 EMU_R::new(((self.bits >> 13) & 1) != 0)
192 }
193 #[doc = "Bit 14 - FPU Exception Handler access control bit"]
194 #[inline(always)]
195 pub fn fpueh(&self) -> FPUEH_R {
196 FPUEH_R::new(((self.bits >> 14) & 1) != 0)
197 }
198 #[doc = "Bit 16 - General Purpose CRC access control bit"]
199 #[inline(always)]
200 pub fn gpcrc(&self) -> GPCRC_R {
201 GPCRC_R::new(((self.bits >> 16) & 1) != 0)
202 }
203 #[doc = "Bit 17 - General purpose Input/Output access control bit"]
204 #[inline(always)]
205 pub fn gpio(&self) -> GPIO_R {
206 GPIO_R::new(((self.bits >> 17) & 1) != 0)
207 }
208 #[doc = "Bit 18 - I2C 0 access control bit"]
209 #[inline(always)]
210 pub fn i2c0(&self) -> I2C0_R {
211 I2C0_R::new(((self.bits >> 18) & 1) != 0)
212 }
213 #[doc = "Bit 19 - I2C 1 access control bit"]
214 #[inline(always)]
215 pub fn i2c1(&self) -> I2C1_R {
216 I2C1_R::new(((self.bits >> 19) & 1) != 0)
217 }
218 #[doc = "Bit 20 - Current Digital to Analog Converter 0 access control bit"]
219 #[inline(always)]
220 pub fn idac0(&self) -> IDAC0_R {
221 IDAC0_R::new(((self.bits >> 20) & 1) != 0)
222 }
223 #[doc = "Bit 21 - Memory System Controller access control bit"]
224 #[inline(always)]
225 pub fn msc(&self) -> MSC_R {
226 MSC_R::new(((self.bits >> 21) & 1) != 0)
227 }
228 #[doc = "Bit 22 - Linked Direct Memory Access Controller access control bit"]
229 #[inline(always)]
230 pub fn ldma(&self) -> LDMA_R {
231 LDMA_R::new(((self.bits >> 22) & 1) != 0)
232 }
233 #[doc = "Bit 23 - Low Energy Sensor Interface access control bit"]
234 #[inline(always)]
235 pub fn lesense(&self) -> LESENSE_R {
236 LESENSE_R::new(((self.bits >> 23) & 1) != 0)
237 }
238 #[doc = "Bit 24 - Low Energy Timer 0 access control bit"]
239 #[inline(always)]
240 pub fn letimer0(&self) -> LETIMER0_R {
241 LETIMER0_R::new(((self.bits >> 24) & 1) != 0)
242 }
243 #[doc = "Bit 25 - Low Energy UART 0 access control bit"]
244 #[inline(always)]
245 pub fn leuart0(&self) -> LEUART0_R {
246 LEUART0_R::new(((self.bits >> 25) & 1) != 0)
247 }
248 #[doc = "Bit 27 - Pulse Counter 0 access control bit"]
249 #[inline(always)]
250 pub fn pcnt0(&self) -> PCNT0_R {
251 PCNT0_R::new(((self.bits >> 27) & 1) != 0)
252 }
253 #[doc = "Bit 28 - Pulse Counter 1 access control bit"]
254 #[inline(always)]
255 pub fn pcnt1(&self) -> PCNT1_R {
256 PCNT1_R::new(((self.bits >> 28) & 1) != 0)
257 }
258 #[doc = "Bit 29 - Pulse Counter 2 access control bit"]
259 #[inline(always)]
260 pub fn pcnt2(&self) -> PCNT2_R {
261 PCNT2_R::new(((self.bits >> 29) & 1) != 0)
262 }
263}
264impl W {
265 #[doc = "Bit 0 - Analog Comparator 0 access control bit"]
266 #[inline(always)]
267 pub fn acmp0(&mut self) -> ACMP0_W {
268 ACMP0_W::new(self)
269 }
270 #[doc = "Bit 1 - Analog Comparator 1 access control bit"]
271 #[inline(always)]
272 pub fn acmp1(&mut self) -> ACMP1_W {
273 ACMP1_W::new(self)
274 }
275 #[doc = "Bit 2 - Analog to Digital Converter 0 access control bit"]
276 #[inline(always)]
277 pub fn adc0(&mut self) -> ADC0_W {
278 ADC0_W::new(self)
279 }
280 #[doc = "Bit 5 - Clock Management Unit access control bit"]
281 #[inline(always)]
282 pub fn cmu(&mut self) -> CMU_W {
283 CMU_W::new(self)
284 }
285 #[doc = "Bit 7 - CRYOTIMER access control bit"]
286 #[inline(always)]
287 pub fn cryotimer(&mut self) -> CRYOTIMER_W {
288 CRYOTIMER_W::new(self)
289 }
290 #[doc = "Bit 8 - Advanced Encryption Standard Accelerator 0 access control bit"]
291 #[inline(always)]
292 pub fn crypto0(&mut self) -> CRYPTO0_W {
293 CRYPTO0_W::new(self)
294 }
295 #[doc = "Bit 9 - Advanced Encryption Standard Accelerator 1 access control bit"]
296 #[inline(always)]
297 pub fn crypto1(&mut self) -> CRYPTO1_W {
298 CRYPTO1_W::new(self)
299 }
300 #[doc = "Bit 10 - Capacitive touch sense module access control bit"]
301 #[inline(always)]
302 pub fn csen(&mut self) -> CSEN_W {
303 CSEN_W::new(self)
304 }
305 #[doc = "Bit 11 - Digital to Analog Converter 0 access control bit"]
306 #[inline(always)]
307 pub fn vdac0(&mut self) -> VDAC0_W {
308 VDAC0_W::new(self)
309 }
310 #[doc = "Bit 12 - Peripheral Reflex System access control bit"]
311 #[inline(always)]
312 pub fn prs(&mut self) -> PRS_W {
313 PRS_W::new(self)
314 }
315 #[doc = "Bit 13 - Energy Management Unit access control bit"]
316 #[inline(always)]
317 pub fn emu(&mut self) -> EMU_W {
318 EMU_W::new(self)
319 }
320 #[doc = "Bit 14 - FPU Exception Handler access control bit"]
321 #[inline(always)]
322 pub fn fpueh(&mut self) -> FPUEH_W {
323 FPUEH_W::new(self)
324 }
325 #[doc = "Bit 16 - General Purpose CRC access control bit"]
326 #[inline(always)]
327 pub fn gpcrc(&mut self) -> GPCRC_W {
328 GPCRC_W::new(self)
329 }
330 #[doc = "Bit 17 - General purpose Input/Output access control bit"]
331 #[inline(always)]
332 pub fn gpio(&mut self) -> GPIO_W {
333 GPIO_W::new(self)
334 }
335 #[doc = "Bit 18 - I2C 0 access control bit"]
336 #[inline(always)]
337 pub fn i2c0(&mut self) -> I2C0_W {
338 I2C0_W::new(self)
339 }
340 #[doc = "Bit 19 - I2C 1 access control bit"]
341 #[inline(always)]
342 pub fn i2c1(&mut self) -> I2C1_W {
343 I2C1_W::new(self)
344 }
345 #[doc = "Bit 20 - Current Digital to Analog Converter 0 access control bit"]
346 #[inline(always)]
347 pub fn idac0(&mut self) -> IDAC0_W {
348 IDAC0_W::new(self)
349 }
350 #[doc = "Bit 21 - Memory System Controller access control bit"]
351 #[inline(always)]
352 pub fn msc(&mut self) -> MSC_W {
353 MSC_W::new(self)
354 }
355 #[doc = "Bit 22 - Linked Direct Memory Access Controller access control bit"]
356 #[inline(always)]
357 pub fn ldma(&mut self) -> LDMA_W {
358 LDMA_W::new(self)
359 }
360 #[doc = "Bit 23 - Low Energy Sensor Interface access control bit"]
361 #[inline(always)]
362 pub fn lesense(&mut self) -> LESENSE_W {
363 LESENSE_W::new(self)
364 }
365 #[doc = "Bit 24 - Low Energy Timer 0 access control bit"]
366 #[inline(always)]
367 pub fn letimer0(&mut self) -> LETIMER0_W {
368 LETIMER0_W::new(self)
369 }
370 #[doc = "Bit 25 - Low Energy UART 0 access control bit"]
371 #[inline(always)]
372 pub fn leuart0(&mut self) -> LEUART0_W {
373 LEUART0_W::new(self)
374 }
375 #[doc = "Bit 27 - Pulse Counter 0 access control bit"]
376 #[inline(always)]
377 pub fn pcnt0(&mut self) -> PCNT0_W {
378 PCNT0_W::new(self)
379 }
380 #[doc = "Bit 28 - Pulse Counter 1 access control bit"]
381 #[inline(always)]
382 pub fn pcnt1(&mut self) -> PCNT1_W {
383 PCNT1_W::new(self)
384 }
385 #[doc = "Bit 29 - Pulse Counter 2 access control bit"]
386 #[inline(always)]
387 pub fn pcnt2(&mut self) -> PCNT2_W {
388 PCNT2_W::new(self)
389 }
390 #[doc = "Writes raw bits to the register."]
391 #[inline(always)]
392 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
393 self.0.bits(bits);
394 self
395 }
396}
397#[doc = "PPU Privilege Access Type Descriptor 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ppupatd0](index.html) module"]
398pub struct PPUPATD0_SPEC;
399impl crate::RegisterSpec for PPUPATD0_SPEC {
400 type Ux = u32;
401}
402#[doc = "`read()` method returns [ppupatd0::R](R) reader structure"]
403impl crate::Readable for PPUPATD0_SPEC {
404 type Reader = R;
405}
406#[doc = "`write(|w| ..)` method takes [ppupatd0::W](W) writer structure"]
407impl crate::Writable for PPUPATD0_SPEC {
408 type Writer = W;
409}
410#[doc = "`reset()` method sets PPUPATD0 to value 0"]
411impl crate::Resettable for PPUPATD0_SPEC {
412 #[inline(always)]
413 fn reset_value() -> Self::Ux {
414 0
415 }
416}