efm32pg12b500_pac/msc/
ramctrl.rs

1#[doc = "Register `RAMCTRL` reader"]
2pub struct R(crate::R<RAMCTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<RAMCTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<RAMCTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<RAMCTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `RAMCTRL` writer"]
17pub struct W(crate::W<RAMCTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<RAMCTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<RAMCTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<RAMCTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `RAMCACHEEN` reader - RAM CACHE Enable"]
38pub type RAMCACHEEN_R = crate::BitReader<bool>;
39#[doc = "Field `RAMCACHEEN` writer - RAM CACHE Enable"]
40pub type RAMCACHEEN_W<'a> = crate::BitWriter<'a, u32, RAMCTRL_SPEC, bool, 0>;
41#[doc = "Field `RAM1CACHEEN` reader - RAM1 CACHE Enable"]
42pub type RAM1CACHEEN_R = crate::BitReader<bool>;
43#[doc = "Field `RAM1CACHEEN` writer - RAM1 CACHE Enable"]
44pub type RAM1CACHEEN_W<'a> = crate::BitWriter<'a, u32, RAMCTRL_SPEC, bool, 8>;
45impl R {
46    #[doc = "Bit 0 - RAM CACHE Enable"]
47    #[inline(always)]
48    pub fn ramcacheen(&self) -> RAMCACHEEN_R {
49        RAMCACHEEN_R::new((self.bits & 1) != 0)
50    }
51    #[doc = "Bit 8 - RAM1 CACHE Enable"]
52    #[inline(always)]
53    pub fn ram1cacheen(&self) -> RAM1CACHEEN_R {
54        RAM1CACHEEN_R::new(((self.bits >> 8) & 1) != 0)
55    }
56}
57impl W {
58    #[doc = "Bit 0 - RAM CACHE Enable"]
59    #[inline(always)]
60    pub fn ramcacheen(&mut self) -> RAMCACHEEN_W {
61        RAMCACHEEN_W::new(self)
62    }
63    #[doc = "Bit 8 - RAM1 CACHE Enable"]
64    #[inline(always)]
65    pub fn ram1cacheen(&mut self) -> RAM1CACHEEN_W {
66        RAM1CACHEEN_W::new(self)
67    }
68    #[doc = "Writes raw bits to the register."]
69    #[inline(always)]
70    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
71        self.0.bits(bits);
72        self
73    }
74}
75#[doc = "RAM Control Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ramctrl](index.html) module"]
76pub struct RAMCTRL_SPEC;
77impl crate::RegisterSpec for RAMCTRL_SPEC {
78    type Ux = u32;
79}
80#[doc = "`read()` method returns [ramctrl::R](R) reader structure"]
81impl crate::Readable for RAMCTRL_SPEC {
82    type Reader = R;
83}
84#[doc = "`write(|w| ..)` method takes [ramctrl::W](W) writer structure"]
85impl crate::Writable for RAMCTRL_SPEC {
86    type Writer = W;
87}
88#[doc = "`reset()` method sets RAMCTRL to value 0"]
89impl crate::Resettable for RAMCTRL_SPEC {
90    #[inline(always)]
91    fn reset_value() -> Self::Ux {
92        0
93    }
94}
efm32pg12b500_pac/msc/ramctrl.rs

efm32pg12b500_pac/msc/
ramctrl.rs
