efm32pg12b500_pac/crypto1/
ctrl.rs

1#[doc = "Register `CTRL` reader"]
2pub struct R(crate::R<CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CTRL` writer"]
17pub struct W(crate::W<CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `AES` reader - AES Mode"]
38pub type AES_R = crate::BitReader<bool>;
39#[doc = "Field `AES` writer - AES Mode"]
40pub type AES_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 0>;
41#[doc = "Field `KEYBUFDIS` reader - Key Buffer Disable"]
42pub type KEYBUFDIS_R = crate::BitReader<bool>;
43#[doc = "Field `KEYBUFDIS` writer - Key Buffer Disable"]
44pub type KEYBUFDIS_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 1>;
45#[doc = "Field `SHA` reader - SHA Mode"]
46pub type SHA_R = crate::BitReader<bool>;
47#[doc = "Field `SHA` writer - SHA Mode"]
48pub type SHA_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 2>;
49#[doc = "Field `NOBUSYSTALL` reader - No Stalling of Bus When Busy"]
50pub type NOBUSYSTALL_R = crate::BitReader<bool>;
51#[doc = "Field `NOBUSYSTALL` writer - No Stalling of Bus When Busy"]
52pub type NOBUSYSTALL_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 10>;
53#[doc = "Increment Width\n\nValue on reset: 0"]
54#[derive(Clone, Copy, Debug, PartialEq)]
55#[repr(u8)]
56pub enum INCWIDTH_A {
57    #[doc = "0: Byte 15 in DATA1 is used for the increment function."]
58    INCWIDTH1 = 0,
59    #[doc = "1: Bytes 14 and 15 in DATA1 are used for the increment function."]
60    INCWIDTH2 = 1,
61    #[doc = "2: Bytes 13 to 15 in DATA1 are used for the increment function."]
62    INCWIDTH3 = 2,
63    #[doc = "3: Bytes 12 to 15 in DATA1 are used for the increment function."]
64    INCWIDTH4 = 3,
65}
66impl From<INCWIDTH_A> for u8 {
67    #[inline(always)]
68    fn from(variant: INCWIDTH_A) -> Self {
69        variant as _
70    }
71}
72#[doc = "Field `INCWIDTH` reader - Increment Width"]
73pub type INCWIDTH_R = crate::FieldReader<u8, INCWIDTH_A>;
74impl INCWIDTH_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub fn variant(&self) -> INCWIDTH_A {
78        match self.bits {
79            0 => INCWIDTH_A::INCWIDTH1,
80            1 => INCWIDTH_A::INCWIDTH2,
81            2 => INCWIDTH_A::INCWIDTH3,
82            3 => INCWIDTH_A::INCWIDTH4,
83            _ => unreachable!(),
84        }
85    }
86    #[doc = "Checks if the value of the field is `INCWIDTH1`"]
87    #[inline(always)]
88    pub fn is_incwidth1(&self) -> bool {
89        *self == INCWIDTH_A::INCWIDTH1
90    }
91    #[doc = "Checks if the value of the field is `INCWIDTH2`"]
92    #[inline(always)]
93    pub fn is_incwidth2(&self) -> bool {
94        *self == INCWIDTH_A::INCWIDTH2
95    }
96    #[doc = "Checks if the value of the field is `INCWIDTH3`"]
97    #[inline(always)]
98    pub fn is_incwidth3(&self) -> bool {
99        *self == INCWIDTH_A::INCWIDTH3
100    }
101    #[doc = "Checks if the value of the field is `INCWIDTH4`"]
102    #[inline(always)]
103    pub fn is_incwidth4(&self) -> bool {
104        *self == INCWIDTH_A::INCWIDTH4
105    }
106}
107#[doc = "Field `INCWIDTH` writer - Increment Width"]
108pub type INCWIDTH_W<'a> = crate::FieldWriterSafe<'a, u32, CTRL_SPEC, u8, INCWIDTH_A, 2, 14>;
109impl<'a> INCWIDTH_W<'a> {
110    #[doc = "Byte 15 in DATA1 is used for the increment function."]
111    #[inline(always)]
112    pub fn incwidth1(self) -> &'a mut W {
113        self.variant(INCWIDTH_A::INCWIDTH1)
114    }
115    #[doc = "Bytes 14 and 15 in DATA1 are used for the increment function."]
116    #[inline(always)]
117    pub fn incwidth2(self) -> &'a mut W {
118        self.variant(INCWIDTH_A::INCWIDTH2)
119    }
120    #[doc = "Bytes 13 to 15 in DATA1 are used for the increment function."]
121    #[inline(always)]
122    pub fn incwidth3(self) -> &'a mut W {
123        self.variant(INCWIDTH_A::INCWIDTH3)
124    }
125    #[doc = "Bytes 12 to 15 in DATA1 are used for the increment function."]
126    #[inline(always)]
127    pub fn incwidth4(self) -> &'a mut W {
128        self.variant(INCWIDTH_A::INCWIDTH4)
129    }
130}
131#[doc = "DMA0 Read Mode\n\nValue on reset: 0"]
132#[derive(Clone, Copy, Debug, PartialEq)]
133#[repr(u8)]
134pub enum DMA0MODE_A {
135    #[doc = "0: Target register is fully read/written during every DMA transaction"]
136    FULL = 0,
137    #[doc = "1: Length Limited. When the current length, i.e. LENGTHA or LENGTHB indicates that there are less bytes available than the register size, only length + necessary zero padding is read. Zero padding is automatically added when writing."]
138    LENLIMIT = 1,
139    #[doc = "2: Target register is fully read/written during every DMA transaction. Bytewise DMA."]
140    FULLBYTE = 2,
141    #[doc = "3: Length Limited. When the current length, i.e. LENGTHA or LENGTHB indicates that there are less bytes available than the register size, only length + necessary zero padding is read. Bytewise DMA. Zero padding is automatically added when writing."]
142    LENLIMITBYTE = 3,
143}
144impl From<DMA0MODE_A> for u8 {
145    #[inline(always)]
146    fn from(variant: DMA0MODE_A) -> Self {
147        variant as _
148    }
149}
150#[doc = "Field `DMA0MODE` reader - DMA0 Read Mode"]
151pub type DMA0MODE_R = crate::FieldReader<u8, DMA0MODE_A>;
152impl DMA0MODE_R {
153    #[doc = "Get enumerated values variant"]
154    #[inline(always)]
155    pub fn variant(&self) -> DMA0MODE_A {
156        match self.bits {
157            0 => DMA0MODE_A::FULL,
158            1 => DMA0MODE_A::LENLIMIT,
159            2 => DMA0MODE_A::FULLBYTE,
160            3 => DMA0MODE_A::LENLIMITBYTE,
161            _ => unreachable!(),
162        }
163    }
164    #[doc = "Checks if the value of the field is `FULL`"]
165    #[inline(always)]
166    pub fn is_full(&self) -> bool {
167        *self == DMA0MODE_A::FULL
168    }
169    #[doc = "Checks if the value of the field is `LENLIMIT`"]
170    #[inline(always)]
171    pub fn is_lenlimit(&self) -> bool {
172        *self == DMA0MODE_A::LENLIMIT
173    }
174    #[doc = "Checks if the value of the field is `FULLBYTE`"]
175    #[inline(always)]
176    pub fn is_fullbyte(&self) -> bool {
177        *self == DMA0MODE_A::FULLBYTE
178    }
179    #[doc = "Checks if the value of the field is `LENLIMITBYTE`"]
180    #[inline(always)]
181    pub fn is_lenlimitbyte(&self) -> bool {
182        *self == DMA0MODE_A::LENLIMITBYTE
183    }
184}
185#[doc = "Field `DMA0MODE` writer - DMA0 Read Mode"]
186pub type DMA0MODE_W<'a> = crate::FieldWriterSafe<'a, u32, CTRL_SPEC, u8, DMA0MODE_A, 2, 16>;
187impl<'a> DMA0MODE_W<'a> {
188    #[doc = "Target register is fully read/written during every DMA transaction"]
189    #[inline(always)]
190    pub fn full(self) -> &'a mut W {
191        self.variant(DMA0MODE_A::FULL)
192    }
193    #[doc = "Length Limited. When the current length, i.e. LENGTHA or LENGTHB indicates that there are less bytes available than the register size, only length + necessary zero padding is read. Zero padding is automatically added when writing."]
194    #[inline(always)]
195    pub fn lenlimit(self) -> &'a mut W {
196        self.variant(DMA0MODE_A::LENLIMIT)
197    }
198    #[doc = "Target register is fully read/written during every DMA transaction. Bytewise DMA."]
199    #[inline(always)]
200    pub fn fullbyte(self) -> &'a mut W {
201        self.variant(DMA0MODE_A::FULLBYTE)
202    }
203    #[doc = "Length Limited. When the current length, i.e. LENGTHA or LENGTHB indicates that there are less bytes available than the register size, only length + necessary zero padding is read. Bytewise DMA. Zero padding is automatically added when writing."]
204    #[inline(always)]
205    pub fn lenlimitbyte(self) -> &'a mut W {
206        self.variant(DMA0MODE_A::LENLIMITBYTE)
207    }
208}
209#[doc = "DMA0 Read Register Select\n\nValue on reset: 0"]
210#[derive(Clone, Copy, Debug, PartialEq)]
211#[repr(u8)]
212pub enum DMA0RSEL_A {
213    #[doc = "0: `0`"]
214    DATA0 = 0,
215    #[doc = "1: `1`"]
216    DDATA0 = 1,
217    #[doc = "2: `10`"]
218    DDATA0BIG = 2,
219    #[doc = "3: `11`"]
220    QDATA0 = 3,
221}
222impl From<DMA0RSEL_A> for u8 {
223    #[inline(always)]
224    fn from(variant: DMA0RSEL_A) -> Self {
225        variant as _
226    }
227}
228#[doc = "Field `DMA0RSEL` reader - DMA0 Read Register Select"]
229pub type DMA0RSEL_R = crate::FieldReader<u8, DMA0RSEL_A>;
230impl DMA0RSEL_R {
231    #[doc = "Get enumerated values variant"]
232    #[inline(always)]
233    pub fn variant(&self) -> DMA0RSEL_A {
234        match self.bits {
235            0 => DMA0RSEL_A::DATA0,
236            1 => DMA0RSEL_A::DDATA0,
237            2 => DMA0RSEL_A::DDATA0BIG,
238            3 => DMA0RSEL_A::QDATA0,
239            _ => unreachable!(),
240        }
241    }
242    #[doc = "Checks if the value of the field is `DATA0`"]
243    #[inline(always)]
244    pub fn is_data0(&self) -> bool {
245        *self == DMA0RSEL_A::DATA0
246    }
247    #[doc = "Checks if the value of the field is `DDATA0`"]
248    #[inline(always)]
249    pub fn is_ddata0(&self) -> bool {
250        *self == DMA0RSEL_A::DDATA0
251    }
252    #[doc = "Checks if the value of the field is `DDATA0BIG`"]
253    #[inline(always)]
254    pub fn is_ddata0big(&self) -> bool {
255        *self == DMA0RSEL_A::DDATA0BIG
256    }
257    #[doc = "Checks if the value of the field is `QDATA0`"]
258    #[inline(always)]
259    pub fn is_qdata0(&self) -> bool {
260        *self == DMA0RSEL_A::QDATA0
261    }
262}
263#[doc = "Field `DMA0RSEL` writer - DMA0 Read Register Select"]
264pub type DMA0RSEL_W<'a> = crate::FieldWriterSafe<'a, u32, CTRL_SPEC, u8, DMA0RSEL_A, 2, 20>;
265impl<'a> DMA0RSEL_W<'a> {
266    #[doc = "`0`"]
267    #[inline(always)]
268    pub fn data0(self) -> &'a mut W {
269        self.variant(DMA0RSEL_A::DATA0)
270    }
271    #[doc = "`1`"]
272    #[inline(always)]
273    pub fn ddata0(self) -> &'a mut W {
274        self.variant(DMA0RSEL_A::DDATA0)
275    }
276    #[doc = "`10`"]
277    #[inline(always)]
278    pub fn ddata0big(self) -> &'a mut W {
279        self.variant(DMA0RSEL_A::DDATA0BIG)
280    }
281    #[doc = "`11`"]
282    #[inline(always)]
283    pub fn qdata0(self) -> &'a mut W {
284        self.variant(DMA0RSEL_A::QDATA0)
285    }
286}
287#[doc = "DMA1 Read Mode\n\nValue on reset: 0"]
288#[derive(Clone, Copy, Debug, PartialEq)]
289#[repr(u8)]
290pub enum DMA1MODE_A {
291    #[doc = "0: Target register is fully read/written during every DMA transaction"]
292    FULL = 0,
293    #[doc = "1: Length Limited. When the current length, i.e. LENGTHA or LENGTHB indicates that there are less bytes available than the register size, only length + 1 bytes + necessary zero padding is read. Zero padding is automatically added when writing."]
294    LENLIMIT = 1,
295    #[doc = "2: Target register is fully read/written during every DMA transaction. Bytewise DMA."]
296    FULLBYTE = 2,
297    #[doc = "3: Length Limited. When the current length, i.e. LENGTHA or LENGTHB indicates that there are less bytes available than the register size, only length + 1 bytes + necessary zero padding is read. Bytewise DMA. Zero padding is automatically added when writing."]
298    LENLIMITBYTE = 3,
299}
300impl From<DMA1MODE_A> for u8 {
301    #[inline(always)]
302    fn from(variant: DMA1MODE_A) -> Self {
303        variant as _
304    }
305}
306#[doc = "Field `DMA1MODE` reader - DMA1 Read Mode"]
307pub type DMA1MODE_R = crate::FieldReader<u8, DMA1MODE_A>;
308impl DMA1MODE_R {
309    #[doc = "Get enumerated values variant"]
310    #[inline(always)]
311    pub fn variant(&self) -> DMA1MODE_A {
312        match self.bits {
313            0 => DMA1MODE_A::FULL,
314            1 => DMA1MODE_A::LENLIMIT,
315            2 => DMA1MODE_A::FULLBYTE,
316            3 => DMA1MODE_A::LENLIMITBYTE,
317            _ => unreachable!(),
318        }
319    }
320    #[doc = "Checks if the value of the field is `FULL`"]
321    #[inline(always)]
322    pub fn is_full(&self) -> bool {
323        *self == DMA1MODE_A::FULL
324    }
325    #[doc = "Checks if the value of the field is `LENLIMIT`"]
326    #[inline(always)]
327    pub fn is_lenlimit(&self) -> bool {
328        *self == DMA1MODE_A::LENLIMIT
329    }
330    #[doc = "Checks if the value of the field is `FULLBYTE`"]
331    #[inline(always)]
332    pub fn is_fullbyte(&self) -> bool {
333        *self == DMA1MODE_A::FULLBYTE
334    }
335    #[doc = "Checks if the value of the field is `LENLIMITBYTE`"]
336    #[inline(always)]
337    pub fn is_lenlimitbyte(&self) -> bool {
338        *self == DMA1MODE_A::LENLIMITBYTE
339    }
340}
341#[doc = "Field `DMA1MODE` writer - DMA1 Read Mode"]
342pub type DMA1MODE_W<'a> = crate::FieldWriterSafe<'a, u32, CTRL_SPEC, u8, DMA1MODE_A, 2, 24>;
343impl<'a> DMA1MODE_W<'a> {
344    #[doc = "Target register is fully read/written during every DMA transaction"]
345    #[inline(always)]
346    pub fn full(self) -> &'a mut W {
347        self.variant(DMA1MODE_A::FULL)
348    }
349    #[doc = "Length Limited. When the current length, i.e. LENGTHA or LENGTHB indicates that there are less bytes available than the register size, only length + 1 bytes + necessary zero padding is read. Zero padding is automatically added when writing."]
350    #[inline(always)]
351    pub fn lenlimit(self) -> &'a mut W {
352        self.variant(DMA1MODE_A::LENLIMIT)
353    }
354    #[doc = "Target register is fully read/written during every DMA transaction. Bytewise DMA."]
355    #[inline(always)]
356    pub fn fullbyte(self) -> &'a mut W {
357        self.variant(DMA1MODE_A::FULLBYTE)
358    }
359    #[doc = "Length Limited. When the current length, i.e. LENGTHA or LENGTHB indicates that there are less bytes available than the register size, only length + 1 bytes + necessary zero padding is read. Bytewise DMA. Zero padding is automatically added when writing."]
360    #[inline(always)]
361    pub fn lenlimitbyte(self) -> &'a mut W {
362        self.variant(DMA1MODE_A::LENLIMITBYTE)
363    }
364}
365#[doc = "DATA0 DMA Unaligned Read Register Select\n\nValue on reset: 0"]
366#[derive(Clone, Copy, Debug, PartialEq)]
367#[repr(u8)]
368pub enum DMA1RSEL_A {
369    #[doc = "0: `0`"]
370    DATA1 = 0,
371    #[doc = "1: `1`"]
372    DDATA1 = 1,
373    #[doc = "2: `10`"]
374    QDATA1 = 2,
375    #[doc = "3: `11`"]
376    QDATA1BIG = 3,
377}
378impl From<DMA1RSEL_A> for u8 {
379    #[inline(always)]
380    fn from(variant: DMA1RSEL_A) -> Self {
381        variant as _
382    }
383}
384#[doc = "Field `DMA1RSEL` reader - DATA0 DMA Unaligned Read Register Select"]
385pub type DMA1RSEL_R = crate::FieldReader<u8, DMA1RSEL_A>;
386impl DMA1RSEL_R {
387    #[doc = "Get enumerated values variant"]
388    #[inline(always)]
389    pub fn variant(&self) -> DMA1RSEL_A {
390        match self.bits {
391            0 => DMA1RSEL_A::DATA1,
392            1 => DMA1RSEL_A::DDATA1,
393            2 => DMA1RSEL_A::QDATA1,
394            3 => DMA1RSEL_A::QDATA1BIG,
395            _ => unreachable!(),
396        }
397    }
398    #[doc = "Checks if the value of the field is `DATA1`"]
399    #[inline(always)]
400    pub fn is_data1(&self) -> bool {
401        *self == DMA1RSEL_A::DATA1
402    }
403    #[doc = "Checks if the value of the field is `DDATA1`"]
404    #[inline(always)]
405    pub fn is_ddata1(&self) -> bool {
406        *self == DMA1RSEL_A::DDATA1
407    }
408    #[doc = "Checks if the value of the field is `QDATA1`"]
409    #[inline(always)]
410    pub fn is_qdata1(&self) -> bool {
411        *self == DMA1RSEL_A::QDATA1
412    }
413    #[doc = "Checks if the value of the field is `QDATA1BIG`"]
414    #[inline(always)]
415    pub fn is_qdata1big(&self) -> bool {
416        *self == DMA1RSEL_A::QDATA1BIG
417    }
418}
419#[doc = "Field `DMA1RSEL` writer - DATA0 DMA Unaligned Read Register Select"]
420pub type DMA1RSEL_W<'a> = crate::FieldWriterSafe<'a, u32, CTRL_SPEC, u8, DMA1RSEL_A, 2, 28>;
421impl<'a> DMA1RSEL_W<'a> {
422    #[doc = "`0`"]
423    #[inline(always)]
424    pub fn data1(self) -> &'a mut W {
425        self.variant(DMA1RSEL_A::DATA1)
426    }
427    #[doc = "`1`"]
428    #[inline(always)]
429    pub fn ddata1(self) -> &'a mut W {
430        self.variant(DMA1RSEL_A::DDATA1)
431    }
432    #[doc = "`10`"]
433    #[inline(always)]
434    pub fn qdata1(self) -> &'a mut W {
435        self.variant(DMA1RSEL_A::QDATA1)
436    }
437    #[doc = "`11`"]
438    #[inline(always)]
439    pub fn qdata1big(self) -> &'a mut W {
440        self.variant(DMA1RSEL_A::QDATA1BIG)
441    }
442}
443#[doc = "Field `COMBDMA0WEREQ` reader - Combined Data0 Write DMA Request"]
444pub type COMBDMA0WEREQ_R = crate::BitReader<bool>;
445#[doc = "Field `COMBDMA0WEREQ` writer - Combined Data0 Write DMA Request"]
446pub type COMBDMA0WEREQ_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 31>;
447impl R {
448    #[doc = "Bit 0 - AES Mode"]
449    #[inline(always)]
450    pub fn aes(&self) -> AES_R {
451        AES_R::new((self.bits & 1) != 0)
452    }
453    #[doc = "Bit 1 - Key Buffer Disable"]
454    #[inline(always)]
455    pub fn keybufdis(&self) -> KEYBUFDIS_R {
456        KEYBUFDIS_R::new(((self.bits >> 1) & 1) != 0)
457    }
458    #[doc = "Bit 2 - SHA Mode"]
459    #[inline(always)]
460    pub fn sha(&self) -> SHA_R {
461        SHA_R::new(((self.bits >> 2) & 1) != 0)
462    }
463    #[doc = "Bit 10 - No Stalling of Bus When Busy"]
464    #[inline(always)]
465    pub fn nobusystall(&self) -> NOBUSYSTALL_R {
466        NOBUSYSTALL_R::new(((self.bits >> 10) & 1) != 0)
467    }
468    #[doc = "Bits 14:15 - Increment Width"]
469    #[inline(always)]
470    pub fn incwidth(&self) -> INCWIDTH_R {
471        INCWIDTH_R::new(((self.bits >> 14) & 3) as u8)
472    }
473    #[doc = "Bits 16:17 - DMA0 Read Mode"]
474    #[inline(always)]
475    pub fn dma0mode(&self) -> DMA0MODE_R {
476        DMA0MODE_R::new(((self.bits >> 16) & 3) as u8)
477    }
478    #[doc = "Bits 20:21 - DMA0 Read Register Select"]
479    #[inline(always)]
480    pub fn dma0rsel(&self) -> DMA0RSEL_R {
481        DMA0RSEL_R::new(((self.bits >> 20) & 3) as u8)
482    }
483    #[doc = "Bits 24:25 - DMA1 Read Mode"]
484    #[inline(always)]
485    pub fn dma1mode(&self) -> DMA1MODE_R {
486        DMA1MODE_R::new(((self.bits >> 24) & 3) as u8)
487    }
488    #[doc = "Bits 28:29 - DATA0 DMA Unaligned Read Register Select"]
489    #[inline(always)]
490    pub fn dma1rsel(&self) -> DMA1RSEL_R {
491        DMA1RSEL_R::new(((self.bits >> 28) & 3) as u8)
492    }
493    #[doc = "Bit 31 - Combined Data0 Write DMA Request"]
494    #[inline(always)]
495    pub fn combdma0wereq(&self) -> COMBDMA0WEREQ_R {
496        COMBDMA0WEREQ_R::new(((self.bits >> 31) & 1) != 0)
497    }
498}
499impl W {
500    #[doc = "Bit 0 - AES Mode"]
501    #[inline(always)]
502    pub fn aes(&mut self) -> AES_W {
503        AES_W::new(self)
504    }
505    #[doc = "Bit 1 - Key Buffer Disable"]
506    #[inline(always)]
507    pub fn keybufdis(&mut self) -> KEYBUFDIS_W {
508        KEYBUFDIS_W::new(self)
509    }
510    #[doc = "Bit 2 - SHA Mode"]
511    #[inline(always)]
512    pub fn sha(&mut self) -> SHA_W {
513        SHA_W::new(self)
514    }
515    #[doc = "Bit 10 - No Stalling of Bus When Busy"]
516    #[inline(always)]
517    pub fn nobusystall(&mut self) -> NOBUSYSTALL_W {
518        NOBUSYSTALL_W::new(self)
519    }
520    #[doc = "Bits 14:15 - Increment Width"]
521    #[inline(always)]
522    pub fn incwidth(&mut self) -> INCWIDTH_W {
523        INCWIDTH_W::new(self)
524    }
525    #[doc = "Bits 16:17 - DMA0 Read Mode"]
526    #[inline(always)]
527    pub fn dma0mode(&mut self) -> DMA0MODE_W {
528        DMA0MODE_W::new(self)
529    }
530    #[doc = "Bits 20:21 - DMA0 Read Register Select"]
531    #[inline(always)]
532    pub fn dma0rsel(&mut self) -> DMA0RSEL_W {
533        DMA0RSEL_W::new(self)
534    }
535    #[doc = "Bits 24:25 - DMA1 Read Mode"]
536    #[inline(always)]
537    pub fn dma1mode(&mut self) -> DMA1MODE_W {
538        DMA1MODE_W::new(self)
539    }
540    #[doc = "Bits 28:29 - DATA0 DMA Unaligned Read Register Select"]
541    #[inline(always)]
542    pub fn dma1rsel(&mut self) -> DMA1RSEL_W {
543        DMA1RSEL_W::new(self)
544    }
545    #[doc = "Bit 31 - Combined Data0 Write DMA Request"]
546    #[inline(always)]
547    pub fn combdma0wereq(&mut self) -> COMBDMA0WEREQ_W {
548        COMBDMA0WEREQ_W::new(self)
549    }
550    #[doc = "Writes raw bits to the register."]
551    #[inline(always)]
552    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
553        self.0.bits(bits);
554        self
555    }
556}
557#[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
558pub struct CTRL_SPEC;
559impl crate::RegisterSpec for CTRL_SPEC {
560    type Ux = u32;
561}
562#[doc = "`read()` method returns [ctrl::R](R) reader structure"]
563impl crate::Readable for CTRL_SPEC {
564    type Reader = R;
565}
566#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
567impl crate::Writable for CTRL_SPEC {
568    type Writer = W;
569}
570#[doc = "`reset()` method sets CTRL to value 0"]
571impl crate::Resettable for CTRL_SPEC {
572    #[inline(always)]
573    fn reset_value() -> Self::Ux {
574        0
575    }
576}
efm32pg12b500_pac/crypto1/ctrl.rs

efm32pg12b500_pac/crypto1/
ctrl.rs
