[][src]Type Definition efm32pg12_pac::usart0::status::R

type R = R<u32, STATUS>;

Reader of register STATUS

Methods

impl R[src]

pub fn rxens(&self) -> RXENS_R[src]

Bit 0 - Receiver Enable Status

pub fn txens(&self) -> TXENS_R[src]

Bit 1 - Transmitter Enable Status

pub fn master(&self) -> MASTER_R[src]

Bit 2 - SPI Master Mode

pub fn rxblock(&self) -> RXBLOCK_R[src]

Bit 3 - Block Incoming Data

pub fn txtri(&self) -> TXTRI_R[src]

Bit 4 - Transmitter Tristated

pub fn txc(&self) -> TXC_R[src]

Bit 5 - TX Complete

pub fn txbl(&self) -> TXBL_R[src]

Bit 6 - TX Buffer Level

pub fn rxdatav(&self) -> RXDATAV_R[src]

Bit 7 - RX Data Valid

pub fn rxfull(&self) -> RXFULL_R[src]

Bit 8 - RX FIFO Full

pub fn txbdright(&self) -> TXBDRIGHT_R[src]

Bit 9 - TX Buffer Expects Double Right Data

pub fn txbsright(&self) -> TXBSRIGHT_R[src]

Bit 10 - TX Buffer Expects Single Right Data

pub fn rxdatavright(&self) -> RXDATAVRIGHT_R[src]

Bit 11 - RX Data Right

pub fn rxfullright(&self) -> RXFULLRIGHT_R[src]

Bit 12 - RX Full of Right Data

pub fn txidle(&self) -> TXIDLE_R[src]

Bit 13 - TX Idle

pub fn timerrestarted(&self) -> TIMERRESTARTED_R[src]

Bit 14 - The USART Timer Restarted Itself

pub fn txbufcnt(&self) -> TXBUFCNT_R[src]

Bits 16:17 - TX Buffer Count