[][src]Type Definition efm32pg12_pac::lesense::decctrl::W

type W = W<u32, DECCTRL>;

Writer for register DECCTRL

Methods

impl W[src]

pub fn disable(&mut self) -> DISABLE_W[src]

Bit 0 - Disable the Decoder

pub fn errchk(&mut self) -> ERRCHK_W[src]

Bit 1 - Enable Check of Current State

pub fn intmap(&mut self) -> INTMAP_W[src]

Bit 2 - Enable Decoder to Channel Interrupt Mapping

pub fn hystprs0(&mut self) -> HYSTPRS0_W[src]

Bit 3 - Enable Decoder Hysteresis on PRS0 Output

pub fn hystprs1(&mut self) -> HYSTPRS1_W[src]

Bit 4 - Enable Decoder Hysteresis on PRS1 Output

pub fn hystprs2(&mut self) -> HYSTPRS2_W[src]

Bit 5 - Enable Decoder Hysteresis on PRS2 Output

pub fn hystirq(&mut self) -> HYSTIRQ_W[src]

Bit 6 - Enable Decoder Hysteresis on Interrupt Requests

pub fn prscnt(&mut self) -> PRSCNT_W[src]

Bit 7 - Enable Count Mode on Decoder PRS Channels 0 and 1

pub fn input(&mut self) -> INPUT_W[src]

Bit 8 - LESENSE Decoder Input Configuration

pub fn prssel0(&mut self) -> PRSSEL0_W[src]

Bits 10:13 - LESENSE Decoder PRS Input 0 Configuration

pub fn prssel1(&mut self) -> PRSSEL1_W[src]

Bits 15:18 - LESENSE Decoder PRS Input 1 Configuration

pub fn prssel2(&mut self) -> PRSSEL2_W[src]

Bits 20:23 - LESENSE Decoder PRS Input 2 Configuration

pub fn prssel3(&mut self) -> PRSSEL3_W[src]

Bits 25:28 - LESENSE Decoder PRS Input 3 Configuration