#[doc = "Reader of register CH0_CTRL"]
pub type R = crate::R<u32, super::CH0_CTRL>;
#[doc = "Writer for register CH0_CTRL"]
pub type W = crate::W<u32, super::CH0_CTRL>;
#[doc = "Register CH0_CTRL `reset()`'s with value 0"]
impl crate::ResetValue for super::CH0_CTRL {
type Type = u32;
#[inline(always)]
fn reset_value() -> Self::Type {
0
}
}
#[doc = "Reader of field `SIGSEL`"]
pub type SIGSEL_R = crate::R<u8, u8>;
#[doc = "Write proxy for field `SIGSEL`"]
pub struct SIGSEL_W<'a> {
w: &'a mut W,
}
impl<'a> SIGSEL_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07);
self.w
}
}
#[doc = "Source Select\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SOURCESEL_A {
#[doc = "0: No source selected"]
NONE,
#[doc = "1: Peripheral Reflex System"]
PRSL,
#[doc = "2: Peripheral Reflex System"]
PRSH,
#[doc = "3: Analog Comparator 0"]
ACMP0,
#[doc = "4: Analog Comparator 1"]
ACMP1,
#[doc = "5: Analog to Digital Converter 0"]
ADC0,
#[doc = "7: Low Energy Sensor Interface"]
LESENSEL,
#[doc = "8: Low Energy Sensor Interface"]
LESENSEH,
#[doc = "9: Low Energy Sensor Interface"]
LESENSED,
#[doc = "10: Low Energy Sensor Interface"]
LESENSE,
#[doc = "11: Real-Time Counter and Calendar"]
RTCC,
#[doc = "12: General purpose Input/Output"]
GPIOL,
#[doc = "13: General purpose Input/Output"]
GPIOH,
#[doc = "14: Low Energy Timer 0"]
LETIMER0,
#[doc = "15: Pulse Counter 0"]
PCNT0,
#[doc = "16: Pulse Counter 1"]
PCNT1,
#[doc = "17: Pulse Counter 2"]
PCNT2,
#[doc = "18: Clock Management Unit"]
CMU,
#[doc = "24: Digital to Analog Converter 0"]
VDAC0,
#[doc = "26: CRYOTIMER"]
CRYOTIMER,
#[doc = "48: Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
USART0,
#[doc = "49: Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
USART1,
#[doc = "50: Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
USART2,
#[doc = "51: Universal Synchronous/Asynchronous Receiver/Transmitter 3"]
USART3,
#[doc = "60: Timer 0"]
TIMER0,
#[doc = "61: Timer 1"]
TIMER1,
#[doc = "62: Wide Timer 0"]
WTIMER0,
#[doc = "63: Wide Timer 1"]
WTIMER1,
#[doc = "67: `1000011`"]
CM4,
}
impl From<SOURCESEL_A> for u8 {
#[inline(always)]
fn from(variant: SOURCESEL_A) -> Self {
match variant {
SOURCESEL_A::NONE => 0,
SOURCESEL_A::PRSL => 1,
SOURCESEL_A::PRSH => 2,
SOURCESEL_A::ACMP0 => 3,
SOURCESEL_A::ACMP1 => 4,
SOURCESEL_A::ADC0 => 5,
SOURCESEL_A::LESENSEL => 7,
SOURCESEL_A::LESENSEH => 8,
SOURCESEL_A::LESENSED => 9,
SOURCESEL_A::LESENSE => 10,
SOURCESEL_A::RTCC => 11,
SOURCESEL_A::GPIOL => 12,
SOURCESEL_A::GPIOH => 13,
SOURCESEL_A::LETIMER0 => 14,
SOURCESEL_A::PCNT0 => 15,
SOURCESEL_A::PCNT1 => 16,
SOURCESEL_A::PCNT2 => 17,
SOURCESEL_A::CMU => 18,
SOURCESEL_A::VDAC0 => 24,
SOURCESEL_A::CRYOTIMER => 26,
SOURCESEL_A::USART0 => 48,
SOURCESEL_A::USART1 => 49,
SOURCESEL_A::USART2 => 50,
SOURCESEL_A::USART3 => 51,
SOURCESEL_A::TIMER0 => 60,
SOURCESEL_A::TIMER1 => 61,
SOURCESEL_A::WTIMER0 => 62,
SOURCESEL_A::WTIMER1 => 63,
SOURCESEL_A::CM4 => 67,
}
}
}
#[doc = "Reader of field `SOURCESEL`"]
pub type SOURCESEL_R = crate::R<u8, SOURCESEL_A>;
impl SOURCESEL_R {
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> crate::Variant<u8, SOURCESEL_A> {
use crate::Variant::*;
match self.bits {
0 => Val(SOURCESEL_A::NONE),
1 => Val(SOURCESEL_A::PRSL),
2 => Val(SOURCESEL_A::PRSH),
3 => Val(SOURCESEL_A::ACMP0),
4 => Val(SOURCESEL_A::ACMP1),
5 => Val(SOURCESEL_A::ADC0),
7 => Val(SOURCESEL_A::LESENSEL),
8 => Val(SOURCESEL_A::LESENSEH),
9 => Val(SOURCESEL_A::LESENSED),
10 => Val(SOURCESEL_A::LESENSE),
11 => Val(SOURCESEL_A::RTCC),
12 => Val(SOURCESEL_A::GPIOL),
13 => Val(SOURCESEL_A::GPIOH),
14 => Val(SOURCESEL_A::LETIMER0),
15 => Val(SOURCESEL_A::PCNT0),
16 => Val(SOURCESEL_A::PCNT1),
17 => Val(SOURCESEL_A::PCNT2),
18 => Val(SOURCESEL_A::CMU),
24 => Val(SOURCESEL_A::VDAC0),
26 => Val(SOURCESEL_A::CRYOTIMER),
48 => Val(SOURCESEL_A::USART0),
49 => Val(SOURCESEL_A::USART1),
50 => Val(SOURCESEL_A::USART2),
51 => Val(SOURCESEL_A::USART3),
60 => Val(SOURCESEL_A::TIMER0),
61 => Val(SOURCESEL_A::TIMER1),
62 => Val(SOURCESEL_A::WTIMER0),
63 => Val(SOURCESEL_A::WTIMER1),
67 => Val(SOURCESEL_A::CM4),
i => Res(i),
}
}
#[doc = "Checks if the value of the field is `NONE`"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == SOURCESEL_A::NONE
}
#[doc = "Checks if the value of the field is `PRSL`"]
#[inline(always)]
pub fn is_prsl(&self) -> bool {
*self == SOURCESEL_A::PRSL
}
#[doc = "Checks if the value of the field is `PRSH`"]
#[inline(always)]
pub fn is_prsh(&self) -> bool {
*self == SOURCESEL_A::PRSH
}
#[doc = "Checks if the value of the field is `ACMP0`"]
#[inline(always)]
pub fn is_acmp0(&self) -> bool {
*self == SOURCESEL_A::ACMP0
}
#[doc = "Checks if the value of the field is `ACMP1`"]
#[inline(always)]
pub fn is_acmp1(&self) -> bool {
*self == SOURCESEL_A::ACMP1
}
#[doc = "Checks if the value of the field is `ADC0`"]
#[inline(always)]
pub fn is_adc0(&self) -> bool {
*self == SOURCESEL_A::ADC0
}
#[doc = "Checks if the value of the field is `LESENSEL`"]
#[inline(always)]
pub fn is_lesensel(&self) -> bool {
*self == SOURCESEL_A::LESENSEL
}
#[doc = "Checks if the value of the field is `LESENSEH`"]
#[inline(always)]
pub fn is_lesenseh(&self) -> bool {
*self == SOURCESEL_A::LESENSEH
}
#[doc = "Checks if the value of the field is `LESENSED`"]
#[inline(always)]
pub fn is_lesensed(&self) -> bool {
*self == SOURCESEL_A::LESENSED
}
#[doc = "Checks if the value of the field is `LESENSE`"]
#[inline(always)]
pub fn is_lesense(&self) -> bool {
*self == SOURCESEL_A::LESENSE
}
#[doc = "Checks if the value of the field is `RTCC`"]
#[inline(always)]
pub fn is_rtcc(&self) -> bool {
*self == SOURCESEL_A::RTCC
}
#[doc = "Checks if the value of the field is `GPIOL`"]
#[inline(always)]
pub fn is_gpiol(&self) -> bool {
*self == SOURCESEL_A::GPIOL
}
#[doc = "Checks if the value of the field is `GPIOH`"]
#[inline(always)]
pub fn is_gpioh(&self) -> bool {
*self == SOURCESEL_A::GPIOH
}
#[doc = "Checks if the value of the field is `LETIMER0`"]
#[inline(always)]
pub fn is_letimer0(&self) -> bool {
*self == SOURCESEL_A::LETIMER0
}
#[doc = "Checks if the value of the field is `PCNT0`"]
#[inline(always)]
pub fn is_pcnt0(&self) -> bool {
*self == SOURCESEL_A::PCNT0
}
#[doc = "Checks if the value of the field is `PCNT1`"]
#[inline(always)]
pub fn is_pcnt1(&self) -> bool {
*self == SOURCESEL_A::PCNT1
}
#[doc = "Checks if the value of the field is `PCNT2`"]
#[inline(always)]
pub fn is_pcnt2(&self) -> bool {
*self == SOURCESEL_A::PCNT2
}
#[doc = "Checks if the value of the field is `CMU`"]
#[inline(always)]
pub fn is_cmu(&self) -> bool {
*self == SOURCESEL_A::CMU
}
#[doc = "Checks if the value of the field is `VDAC0`"]
#[inline(always)]
pub fn is_vdac0(&self) -> bool {
*self == SOURCESEL_A::VDAC0
}
#[doc = "Checks if the value of the field is `CRYOTIMER`"]
#[inline(always)]
pub fn is_cryotimer(&self) -> bool {
*self == SOURCESEL_A::CRYOTIMER
}
#[doc = "Checks if the value of the field is `USART0`"]
#[inline(always)]
pub fn is_usart0(&self) -> bool {
*self == SOURCESEL_A::USART0
}
#[doc = "Checks if the value of the field is `USART1`"]
#[inline(always)]
pub fn is_usart1(&self) -> bool {
*self == SOURCESEL_A::USART1
}
#[doc = "Checks if the value of the field is `USART2`"]
#[inline(always)]
pub fn is_usart2(&self) -> bool {
*self == SOURCESEL_A::USART2
}
#[doc = "Checks if the value of the field is `USART3`"]
#[inline(always)]
pub fn is_usart3(&self) -> bool {
*self == SOURCESEL_A::USART3
}
#[doc = "Checks if the value of the field is `TIMER0`"]
#[inline(always)]
pub fn is_timer0(&self) -> bool {
*self == SOURCESEL_A::TIMER0
}
#[doc = "Checks if the value of the field is `TIMER1`"]
#[inline(always)]
pub fn is_timer1(&self) -> bool {
*self == SOURCESEL_A::TIMER1
}
#[doc = "Checks if the value of the field is `WTIMER0`"]
#[inline(always)]
pub fn is_wtimer0(&self) -> bool {
*self == SOURCESEL_A::WTIMER0
}
#[doc = "Checks if the value of the field is `WTIMER1`"]
#[inline(always)]
pub fn is_wtimer1(&self) -> bool {
*self == SOURCESEL_A::WTIMER1
}
#[doc = "Checks if the value of the field is `CM4`"]
#[inline(always)]
pub fn is_cm4(&self) -> bool {
*self == SOURCESEL_A::CM4
}
}
#[doc = "Write proxy for field `SOURCESEL`"]
pub struct SOURCESEL_W<'a> {
w: &'a mut W,
}
impl<'a> SOURCESEL_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SOURCESEL_A) -> &'a mut W {
unsafe { self.bits(variant.into()) }
}
#[doc = "No source selected"]
#[inline(always)]
pub fn none(self) -> &'a mut W {
self.variant(SOURCESEL_A::NONE)
}
#[doc = "Peripheral Reflex System"]
#[inline(always)]
pub fn prsl(self) -> &'a mut W {
self.variant(SOURCESEL_A::PRSL)
}
#[doc = "Peripheral Reflex System"]
#[inline(always)]
pub fn prsh(self) -> &'a mut W {
self.variant(SOURCESEL_A::PRSH)
}
#[doc = "Analog Comparator 0"]
#[inline(always)]
pub fn acmp0(self) -> &'a mut W {
self.variant(SOURCESEL_A::ACMP0)
}
#[doc = "Analog Comparator 1"]
#[inline(always)]
pub fn acmp1(self) -> &'a mut W {
self.variant(SOURCESEL_A::ACMP1)
}
#[doc = "Analog to Digital Converter 0"]
#[inline(always)]
pub fn adc0(self) -> &'a mut W {
self.variant(SOURCESEL_A::ADC0)
}
#[doc = "Low Energy Sensor Interface"]
#[inline(always)]
pub fn lesensel(self) -> &'a mut W {
self.variant(SOURCESEL_A::LESENSEL)
}
#[doc = "Low Energy Sensor Interface"]
#[inline(always)]
pub fn lesenseh(self) -> &'a mut W {
self.variant(SOURCESEL_A::LESENSEH)
}
#[doc = "Low Energy Sensor Interface"]
#[inline(always)]
pub fn lesensed(self) -> &'a mut W {
self.variant(SOURCESEL_A::LESENSED)
}
#[doc = "Low Energy Sensor Interface"]
#[inline(always)]
pub fn lesense(self) -> &'a mut W {
self.variant(SOURCESEL_A::LESENSE)
}
#[doc = "Real-Time Counter and Calendar"]
#[inline(always)]
pub fn rtcc(self) -> &'a mut W {
self.variant(SOURCESEL_A::RTCC)
}
#[doc = "General purpose Input/Output"]
#[inline(always)]
pub fn gpiol(self) -> &'a mut W {
self.variant(SOURCESEL_A::GPIOL)
}
#[doc = "General purpose Input/Output"]
#[inline(always)]
pub fn gpioh(self) -> &'a mut W {
self.variant(SOURCESEL_A::GPIOH)
}
#[doc = "Low Energy Timer 0"]
#[inline(always)]
pub fn letimer0(self) -> &'a mut W {
self.variant(SOURCESEL_A::LETIMER0)
}
#[doc = "Pulse Counter 0"]
#[inline(always)]
pub fn pcnt0(self) -> &'a mut W {
self.variant(SOURCESEL_A::PCNT0)
}
#[doc = "Pulse Counter 1"]
#[inline(always)]
pub fn pcnt1(self) -> &'a mut W {
self.variant(SOURCESEL_A::PCNT1)
}
#[doc = "Pulse Counter 2"]
#[inline(always)]
pub fn pcnt2(self) -> &'a mut W {
self.variant(SOURCESEL_A::PCNT2)
}
#[doc = "Clock Management Unit"]
#[inline(always)]
pub fn cmu(self) -> &'a mut W {
self.variant(SOURCESEL_A::CMU)
}
#[doc = "Digital to Analog Converter 0"]
#[inline(always)]
pub fn vdac0(self) -> &'a mut W {
self.variant(SOURCESEL_A::VDAC0)
}
#[doc = "CRYOTIMER"]
#[inline(always)]
pub fn cryotimer(self) -> &'a mut W {
self.variant(SOURCESEL_A::CRYOTIMER)
}
#[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
#[inline(always)]
pub fn usart0(self) -> &'a mut W {
self.variant(SOURCESEL_A::USART0)
}
#[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
#[inline(always)]
pub fn usart1(self) -> &'a mut W {
self.variant(SOURCESEL_A::USART1)
}
#[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
#[inline(always)]
pub fn usart2(self) -> &'a mut W {
self.variant(SOURCESEL_A::USART2)
}
#[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 3"]
#[inline(always)]
pub fn usart3(self) -> &'a mut W {
self.variant(SOURCESEL_A::USART3)
}
#[doc = "Timer 0"]
#[inline(always)]
pub fn timer0(self) -> &'a mut W {
self.variant(SOURCESEL_A::TIMER0)
}
#[doc = "Timer 1"]
#[inline(always)]
pub fn timer1(self) -> &'a mut W {
self.variant(SOURCESEL_A::TIMER1)
}
#[doc = "Wide Timer 0"]
#[inline(always)]
pub fn wtimer0(self) -> &'a mut W {
self.variant(SOURCESEL_A::WTIMER0)
}
#[doc = "Wide Timer 1"]
#[inline(always)]
pub fn wtimer1(self) -> &'a mut W {
self.variant(SOURCESEL_A::WTIMER1)
}
#[doc = "`1000011`"]
#[inline(always)]
pub fn cm4(self) -> &'a mut W {
self.variant(SOURCESEL_A::CM4)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x7f << 8)) | (((value as u32) & 0x7f) << 8);
self.w
}
}
#[doc = "Edge Detect Select\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EDSEL_A {
#[doc = "0: Signal is left as it is"]
OFF,
#[doc = "1: A one HFCLK cycle pulse is generated for every positive edge of the incoming signal"]
POSEDGE,
#[doc = "2: A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
NEGEDGE,
#[doc = "3: A one HFCLK clock cycle pulse is generated for every edge of the incoming signal"]
BOTHEDGES,
}
impl From<EDSEL_A> for u8 {
#[inline(always)]
fn from(variant: EDSEL_A) -> Self {
match variant {
EDSEL_A::OFF => 0,
EDSEL_A::POSEDGE => 1,
EDSEL_A::NEGEDGE => 2,
EDSEL_A::BOTHEDGES => 3,
}
}
}
#[doc = "Reader of field `EDSEL`"]
pub type EDSEL_R = crate::R<u8, EDSEL_A>;
impl EDSEL_R {
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> EDSEL_A {
match self.bits {
0 => EDSEL_A::OFF,
1 => EDSEL_A::POSEDGE,
2 => EDSEL_A::NEGEDGE,
3 => EDSEL_A::BOTHEDGES,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `OFF`"]
#[inline(always)]
pub fn is_off(&self) -> bool {
*self == EDSEL_A::OFF
}
#[doc = "Checks if the value of the field is `POSEDGE`"]
#[inline(always)]
pub fn is_posedge(&self) -> bool {
*self == EDSEL_A::POSEDGE
}
#[doc = "Checks if the value of the field is `NEGEDGE`"]
#[inline(always)]
pub fn is_negedge(&self) -> bool {
*self == EDSEL_A::NEGEDGE
}
#[doc = "Checks if the value of the field is `BOTHEDGES`"]
#[inline(always)]
pub fn is_bothedges(&self) -> bool {
*self == EDSEL_A::BOTHEDGES
}
}
#[doc = "Write proxy for field `EDSEL`"]
pub struct EDSEL_W<'a> {
w: &'a mut W,
}
impl<'a> EDSEL_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: EDSEL_A) -> &'a mut W {
{
self.bits(variant.into())
}
}
#[doc = "Signal is left as it is"]
#[inline(always)]
pub fn off(self) -> &'a mut W {
self.variant(EDSEL_A::OFF)
}
#[doc = "A one HFCLK cycle pulse is generated for every positive edge of the incoming signal"]
#[inline(always)]
pub fn posedge(self) -> &'a mut W {
self.variant(EDSEL_A::POSEDGE)
}
#[doc = "A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
#[inline(always)]
pub fn negedge(self) -> &'a mut W {
self.variant(EDSEL_A::NEGEDGE)
}
#[doc = "A one HFCLK clock cycle pulse is generated for every edge of the incoming signal"]
#[inline(always)]
pub fn bothedges(self) -> &'a mut W {
self.variant(EDSEL_A::BOTHEDGES)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 20)) | (((value as u32) & 0x03) << 20);
self.w
}
}
#[doc = "Reader of field `STRETCH`"]
pub type STRETCH_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `STRETCH`"]
pub struct STRETCH_W<'a> {
w: &'a mut W,
}
impl<'a> STRETCH_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
self.w
}
}
#[doc = "Reader of field `INV`"]
pub type INV_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `INV`"]
pub struct INV_W<'a> {
w: &'a mut W,
}
impl<'a> INV_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
self.w
}
}
#[doc = "Reader of field `ORPREV`"]
pub type ORPREV_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `ORPREV`"]
pub struct ORPREV_W<'a> {
w: &'a mut W,
}
impl<'a> ORPREV_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27);
self.w
}
}
#[doc = "Reader of field `ANDNEXT`"]
pub type ANDNEXT_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `ANDNEXT`"]
pub struct ANDNEXT_W<'a> {
w: &'a mut W,
}
impl<'a> ANDNEXT_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
self.w
}
}
#[doc = "Reader of field `ASYNC`"]
pub type ASYNC_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `ASYNC`"]
pub struct ASYNC_W<'a> {
w: &'a mut W,
}
impl<'a> ASYNC_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
self.w
}
}
impl R {
#[doc = "Bits 0:2 - Signal Select"]
#[inline(always)]
pub fn sigsel(&self) -> SIGSEL_R {
SIGSEL_R::new((self.bits & 0x07) as u8)
}
#[doc = "Bits 8:14 - Source Select"]
#[inline(always)]
pub fn sourcesel(&self) -> SOURCESEL_R {
SOURCESEL_R::new(((self.bits >> 8) & 0x7f) as u8)
}
#[doc = "Bits 20:21 - Edge Detect Select"]
#[inline(always)]
pub fn edsel(&self) -> EDSEL_R {
EDSEL_R::new(((self.bits >> 20) & 0x03) as u8)
}
#[doc = "Bit 25 - Stretch Channel Output"]
#[inline(always)]
pub fn stretch(&self) -> STRETCH_R {
STRETCH_R::new(((self.bits >> 25) & 0x01) != 0)
}
#[doc = "Bit 26 - Invert Channel"]
#[inline(always)]
pub fn inv(&self) -> INV_R {
INV_R::new(((self.bits >> 26) & 0x01) != 0)
}
#[doc = "Bit 27 - Or Previous"]
#[inline(always)]
pub fn orprev(&self) -> ORPREV_R {
ORPREV_R::new(((self.bits >> 27) & 0x01) != 0)
}
#[doc = "Bit 28 - And Next"]
#[inline(always)]
pub fn andnext(&self) -> ANDNEXT_R {
ANDNEXT_R::new(((self.bits >> 28) & 0x01) != 0)
}
#[doc = "Bit 30 - Asynchronous Reflex"]
#[inline(always)]
pub fn async_(&self) -> ASYNC_R {
ASYNC_R::new(((self.bits >> 30) & 0x01) != 0)
}
}
impl W {
#[doc = "Bits 0:2 - Signal Select"]
#[inline(always)]
pub fn sigsel(&mut self) -> SIGSEL_W {
SIGSEL_W { w: self }
}
#[doc = "Bits 8:14 - Source Select"]
#[inline(always)]
pub fn sourcesel(&mut self) -> SOURCESEL_W {
SOURCESEL_W { w: self }
}
#[doc = "Bits 20:21 - Edge Detect Select"]
#[inline(always)]
pub fn edsel(&mut self) -> EDSEL_W {
EDSEL_W { w: self }
}
#[doc = "Bit 25 - Stretch Channel Output"]
#[inline(always)]
pub fn stretch(&mut self) -> STRETCH_W {
STRETCH_W { w: self }
}
#[doc = "Bit 26 - Invert Channel"]
#[inline(always)]
pub fn inv(&mut self) -> INV_W {
INV_W { w: self }
}
#[doc = "Bit 27 - Or Previous"]
#[inline(always)]
pub fn orprev(&mut self) -> ORPREV_W {
ORPREV_W { w: self }
}
#[doc = "Bit 28 - And Next"]
#[inline(always)]
pub fn andnext(&mut self) -> ANDNEXT_W {
ANDNEXT_W { w: self }
}
#[doc = "Bit 30 - Asynchronous Reflex"]
#[inline(always)]
pub fn async_(&mut self) -> ASYNC_W {
ASYNC_W { w: self }
}
}