Enum efm32pg12_pac::prs::ch1_ctrl::EDSEL_A

pub enum EDSEL_A {
    OFF,
    POSEDGE,
    NEGEDGE,
    BOTHEDGES,
}

Edge Detect Select

Value on reset: 0

Variants

OFF

0: Signal is left as it is

POSEDGE

1: A one HFCLK cycle pulse is generated for every positive edge of the incoming signal

NEGEDGE

2: A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal

BOTHEDGES

3: A one HFCLK clock cycle pulse is generated for every edge of the incoming signal

Trait Implementations

impl From<EDSEL_A> for u8

fn from(variant: EDSEL_A) -> Self

Performs the conversion.

impl Debug for EDSEL_A

fn fmt(&self, f: &mut Formatter) -> Result

Formats the value using the given formatter.

impl PartialEq<EDSEL_A> for EDSEL_A

fn eq(&self, other: &EDSEL_A) -> bool

This method tests for self and other values to be equal, and is used by ==.

#[must_use] fn ne(&self, other: &Rhs) -> bool

This method tests for !=.

impl Copy for EDSEL_A

impl StructuralPartialEq for EDSEL_A

impl Clone for EDSEL_A

fn clone(&self) -> EDSEL_A

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.