efm32lg940_pac/usb/
hprt.rs

1#[doc = "Register `HPRT` reader"]
2pub struct R(crate::R<HPRT_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<HPRT_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<HPRT_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<HPRT_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `HPRT` writer"]
17pub struct W(crate::W<HPRT_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<HPRT_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<HPRT_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<HPRT_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `PRTCONNSTS` reader - Port Connect Status"]
38pub type PRTCONNSTS_R = crate::BitReader<bool>;
39#[doc = "Field `PRTCONNDET` reader - Port Connect Detected"]
40pub type PRTCONNDET_R = crate::BitReader<bool>;
41#[doc = "Field `PRTCONNDET` writer - Port Connect Detected"]
42pub type PRTCONNDET_W<'a> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, 1>;
43#[doc = "Field `PRTENA` reader - Port Enable"]
44pub type PRTENA_R = crate::BitReader<bool>;
45#[doc = "Field `PRTENA` writer - Port Enable"]
46pub type PRTENA_W<'a> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, 2>;
47#[doc = "Field `PRTENCHNG` reader - Port Enable/Disable Change"]
48pub type PRTENCHNG_R = crate::BitReader<bool>;
49#[doc = "Field `PRTENCHNG` writer - Port Enable/Disable Change"]
50pub type PRTENCHNG_W<'a> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, 3>;
51#[doc = "Field `PRTOVRCURRACT` reader - Port Overcurrent Active"]
52pub type PRTOVRCURRACT_R = crate::BitReader<bool>;
53#[doc = "Field `PRTOVRCURRCHNG` reader - Port Overcurrent Change"]
54pub type PRTOVRCURRCHNG_R = crate::BitReader<bool>;
55#[doc = "Field `PRTOVRCURRCHNG` writer - Port Overcurrent Change"]
56pub type PRTOVRCURRCHNG_W<'a> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, 5>;
57#[doc = "Field `PRTRES` reader - Port Resume"]
58pub type PRTRES_R = crate::BitReader<bool>;
59#[doc = "Field `PRTRES` writer - Port Resume"]
60pub type PRTRES_W<'a> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, 6>;
61#[doc = "Field `PRTSUSP` reader - Port Suspend"]
62pub type PRTSUSP_R = crate::BitReader<bool>;
63#[doc = "Field `PRTSUSP` writer - Port Suspend"]
64pub type PRTSUSP_W<'a> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, 7>;
65#[doc = "Field `PRTRST` reader - Port Reset"]
66pub type PRTRST_R = crate::BitReader<bool>;
67#[doc = "Field `PRTRST` writer - Port Reset"]
68pub type PRTRST_W<'a> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, 8>;
69#[doc = "Field `PRTLNSTS` reader - Port Line Status"]
70pub type PRTLNSTS_R = crate::FieldReader<u8, u8>;
71#[doc = "Field `PRTPWR` reader - Port Power"]
72pub type PRTPWR_R = crate::BitReader<bool>;
73#[doc = "Field `PRTPWR` writer - Port Power"]
74pub type PRTPWR_W<'a> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, 12>;
75#[doc = "Port Test Control\n\nValue on reset: 0"]
76#[derive(Clone, Copy, Debug, PartialEq)]
77#[repr(u8)]
78pub enum PRTTSTCTL_A {
79    #[doc = "0: Test mode disabled."]
80    DISABLE = 0,
81    #[doc = "1: Test_J mode."]
82    J = 1,
83    #[doc = "2: Test_K mode."]
84    K = 2,
85    #[doc = "3: Test_SE0_NAK mode."]
86    SE0NAK = 3,
87    #[doc = "4: Test_Packet mode."]
88    PACKET = 4,
89    #[doc = "5: Test_Force_Enable."]
90    FORCE = 5,
91}
92impl From<PRTTSTCTL_A> for u8 {
93    #[inline(always)]
94    fn from(variant: PRTTSTCTL_A) -> Self {
95        variant as _
96    }
97}
98#[doc = "Field `PRTTSTCTL` reader - Port Test Control"]
99pub type PRTTSTCTL_R = crate::FieldReader<u8, PRTTSTCTL_A>;
100impl PRTTSTCTL_R {
101    #[doc = "Get enumerated values variant"]
102    #[inline(always)]
103    pub fn variant(&self) -> Option<PRTTSTCTL_A> {
104        match self.bits {
105            0 => Some(PRTTSTCTL_A::DISABLE),
106            1 => Some(PRTTSTCTL_A::J),
107            2 => Some(PRTTSTCTL_A::K),
108            3 => Some(PRTTSTCTL_A::SE0NAK),
109            4 => Some(PRTTSTCTL_A::PACKET),
110            5 => Some(PRTTSTCTL_A::FORCE),
111            _ => None,
112        }
113    }
114    #[doc = "Checks if the value of the field is `DISABLE`"]
115    #[inline(always)]
116    pub fn is_disable(&self) -> bool {
117        *self == PRTTSTCTL_A::DISABLE
118    }
119    #[doc = "Checks if the value of the field is `J`"]
120    #[inline(always)]
121    pub fn is_j(&self) -> bool {
122        *self == PRTTSTCTL_A::J
123    }
124    #[doc = "Checks if the value of the field is `K`"]
125    #[inline(always)]
126    pub fn is_k(&self) -> bool {
127        *self == PRTTSTCTL_A::K
128    }
129    #[doc = "Checks if the value of the field is `SE0NAK`"]
130    #[inline(always)]
131    pub fn is_se0nak(&self) -> bool {
132        *self == PRTTSTCTL_A::SE0NAK
133    }
134    #[doc = "Checks if the value of the field is `PACKET`"]
135    #[inline(always)]
136    pub fn is_packet(&self) -> bool {
137        *self == PRTTSTCTL_A::PACKET
138    }
139    #[doc = "Checks if the value of the field is `FORCE`"]
140    #[inline(always)]
141    pub fn is_force(&self) -> bool {
142        *self == PRTTSTCTL_A::FORCE
143    }
144}
145#[doc = "Field `PRTTSTCTL` writer - Port Test Control"]
146pub type PRTTSTCTL_W<'a> = crate::FieldWriter<'a, u32, HPRT_SPEC, u8, PRTTSTCTL_A, 4, 13>;
147impl<'a> PRTTSTCTL_W<'a> {
148    #[doc = "Test mode disabled."]
149    #[inline(always)]
150    pub fn disable(self) -> &'a mut W {
151        self.variant(PRTTSTCTL_A::DISABLE)
152    }
153    #[doc = "Test_J mode."]
154    #[inline(always)]
155    pub fn j(self) -> &'a mut W {
156        self.variant(PRTTSTCTL_A::J)
157    }
158    #[doc = "Test_K mode."]
159    #[inline(always)]
160    pub fn k(self) -> &'a mut W {
161        self.variant(PRTTSTCTL_A::K)
162    }
163    #[doc = "Test_SE0_NAK mode."]
164    #[inline(always)]
165    pub fn se0nak(self) -> &'a mut W {
166        self.variant(PRTTSTCTL_A::SE0NAK)
167    }
168    #[doc = "Test_Packet mode."]
169    #[inline(always)]
170    pub fn packet(self) -> &'a mut W {
171        self.variant(PRTTSTCTL_A::PACKET)
172    }
173    #[doc = "Test_Force_Enable."]
174    #[inline(always)]
175    pub fn force(self) -> &'a mut W {
176        self.variant(PRTTSTCTL_A::FORCE)
177    }
178}
179#[doc = "Port Speed\n\nValue on reset: 0"]
180#[derive(Clone, Copy, Debug, PartialEq)]
181#[repr(u8)]
182pub enum PRTSPD_A {
183    #[doc = "0: High speed."]
184    HS = 0,
185    #[doc = "1: Full speed."]
186    FS = 1,
187    #[doc = "2: Low speed."]
188    LS = 2,
189}
190impl From<PRTSPD_A> for u8 {
191    #[inline(always)]
192    fn from(variant: PRTSPD_A) -> Self {
193        variant as _
194    }
195}
196#[doc = "Field `PRTSPD` reader - Port Speed"]
197pub type PRTSPD_R = crate::FieldReader<u8, PRTSPD_A>;
198impl PRTSPD_R {
199    #[doc = "Get enumerated values variant"]
200    #[inline(always)]
201    pub fn variant(&self) -> Option<PRTSPD_A> {
202        match self.bits {
203            0 => Some(PRTSPD_A::HS),
204            1 => Some(PRTSPD_A::FS),
205            2 => Some(PRTSPD_A::LS),
206            _ => None,
207        }
208    }
209    #[doc = "Checks if the value of the field is `HS`"]
210    #[inline(always)]
211    pub fn is_hs(&self) -> bool {
212        *self == PRTSPD_A::HS
213    }
214    #[doc = "Checks if the value of the field is `FS`"]
215    #[inline(always)]
216    pub fn is_fs(&self) -> bool {
217        *self == PRTSPD_A::FS
218    }
219    #[doc = "Checks if the value of the field is `LS`"]
220    #[inline(always)]
221    pub fn is_ls(&self) -> bool {
222        *self == PRTSPD_A::LS
223    }
224}
225impl R {
226    #[doc = "Bit 0 - Port Connect Status"]
227    #[inline(always)]
228    pub fn prtconnsts(&self) -> PRTCONNSTS_R {
229        PRTCONNSTS_R::new((self.bits & 1) != 0)
230    }
231    #[doc = "Bit 1 - Port Connect Detected"]
232    #[inline(always)]
233    pub fn prtconndet(&self) -> PRTCONNDET_R {
234        PRTCONNDET_R::new(((self.bits >> 1) & 1) != 0)
235    }
236    #[doc = "Bit 2 - Port Enable"]
237    #[inline(always)]
238    pub fn prtena(&self) -> PRTENA_R {
239        PRTENA_R::new(((self.bits >> 2) & 1) != 0)
240    }
241    #[doc = "Bit 3 - Port Enable/Disable Change"]
242    #[inline(always)]
243    pub fn prtenchng(&self) -> PRTENCHNG_R {
244        PRTENCHNG_R::new(((self.bits >> 3) & 1) != 0)
245    }
246    #[doc = "Bit 4 - Port Overcurrent Active"]
247    #[inline(always)]
248    pub fn prtovrcurract(&self) -> PRTOVRCURRACT_R {
249        PRTOVRCURRACT_R::new(((self.bits >> 4) & 1) != 0)
250    }
251    #[doc = "Bit 5 - Port Overcurrent Change"]
252    #[inline(always)]
253    pub fn prtovrcurrchng(&self) -> PRTOVRCURRCHNG_R {
254        PRTOVRCURRCHNG_R::new(((self.bits >> 5) & 1) != 0)
255    }
256    #[doc = "Bit 6 - Port Resume"]
257    #[inline(always)]
258    pub fn prtres(&self) -> PRTRES_R {
259        PRTRES_R::new(((self.bits >> 6) & 1) != 0)
260    }
261    #[doc = "Bit 7 - Port Suspend"]
262    #[inline(always)]
263    pub fn prtsusp(&self) -> PRTSUSP_R {
264        PRTSUSP_R::new(((self.bits >> 7) & 1) != 0)
265    }
266    #[doc = "Bit 8 - Port Reset"]
267    #[inline(always)]
268    pub fn prtrst(&self) -> PRTRST_R {
269        PRTRST_R::new(((self.bits >> 8) & 1) != 0)
270    }
271    #[doc = "Bits 10:11 - Port Line Status"]
272    #[inline(always)]
273    pub fn prtlnsts(&self) -> PRTLNSTS_R {
274        PRTLNSTS_R::new(((self.bits >> 10) & 3) as u8)
275    }
276    #[doc = "Bit 12 - Port Power"]
277    #[inline(always)]
278    pub fn prtpwr(&self) -> PRTPWR_R {
279        PRTPWR_R::new(((self.bits >> 12) & 1) != 0)
280    }
281    #[doc = "Bits 13:16 - Port Test Control"]
282    #[inline(always)]
283    pub fn prttstctl(&self) -> PRTTSTCTL_R {
284        PRTTSTCTL_R::new(((self.bits >> 13) & 0x0f) as u8)
285    }
286    #[doc = "Bits 17:18 - Port Speed"]
287    #[inline(always)]
288    pub fn prtspd(&self) -> PRTSPD_R {
289        PRTSPD_R::new(((self.bits >> 17) & 3) as u8)
290    }
291}
292impl W {
293    #[doc = "Bit 1 - Port Connect Detected"]
294    #[inline(always)]
295    pub fn prtconndet(&mut self) -> PRTCONNDET_W {
296        PRTCONNDET_W::new(self)
297    }
298    #[doc = "Bit 2 - Port Enable"]
299    #[inline(always)]
300    pub fn prtena(&mut self) -> PRTENA_W {
301        PRTENA_W::new(self)
302    }
303    #[doc = "Bit 3 - Port Enable/Disable Change"]
304    #[inline(always)]
305    pub fn prtenchng(&mut self) -> PRTENCHNG_W {
306        PRTENCHNG_W::new(self)
307    }
308    #[doc = "Bit 5 - Port Overcurrent Change"]
309    #[inline(always)]
310    pub fn prtovrcurrchng(&mut self) -> PRTOVRCURRCHNG_W {
311        PRTOVRCURRCHNG_W::new(self)
312    }
313    #[doc = "Bit 6 - Port Resume"]
314    #[inline(always)]
315    pub fn prtres(&mut self) -> PRTRES_W {
316        PRTRES_W::new(self)
317    }
318    #[doc = "Bit 7 - Port Suspend"]
319    #[inline(always)]
320    pub fn prtsusp(&mut self) -> PRTSUSP_W {
321        PRTSUSP_W::new(self)
322    }
323    #[doc = "Bit 8 - Port Reset"]
324    #[inline(always)]
325    pub fn prtrst(&mut self) -> PRTRST_W {
326        PRTRST_W::new(self)
327    }
328    #[doc = "Bit 12 - Port Power"]
329    #[inline(always)]
330    pub fn prtpwr(&mut self) -> PRTPWR_W {
331        PRTPWR_W::new(self)
332    }
333    #[doc = "Bits 13:16 - Port Test Control"]
334    #[inline(always)]
335    pub fn prttstctl(&mut self) -> PRTTSTCTL_W {
336        PRTTSTCTL_W::new(self)
337    }
338    #[doc = "Writes raw bits to the register."]
339    #[inline(always)]
340    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
341        self.0.bits(bits);
342        self
343    }
344}
345#[doc = "Host Port Control and Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hprt](index.html) module"]
346pub struct HPRT_SPEC;
347impl crate::RegisterSpec for HPRT_SPEC {
348    type Ux = u32;
349}
350#[doc = "`read()` method returns [hprt::R](R) reader structure"]
351impl crate::Readable for HPRT_SPEC {
352    type Reader = R;
353}
354#[doc = "`write(|w| ..)` method takes [hprt::W](W) writer structure"]
355impl crate::Writable for HPRT_SPEC {
356    type Writer = W;
357}
358#[doc = "`reset()` method sets HPRT to value 0"]
359impl crate::Resettable for HPRT_SPEC {
360    #[inline(always)]
361    fn reset_value() -> Self::Ux {
362        0
363    }
364}
efm32lg940_pac/usb/hprt.rs

efm32lg940_pac/usb/
hprt.rs
