efm32lg880_pac/lcd/
ctrl.rs

1#[doc = "Register `CTRL` reader"]
2pub struct R(crate::R<CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CTRL` writer"]
17pub struct W(crate::W<CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `EN` reader - LCD Enable"]
38pub type EN_R = crate::BitReader<bool>;
39#[doc = "Field `EN` writer - LCD Enable"]
40pub type EN_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 0>;
41#[doc = "Update Data Control\n\nValue on reset: 0"]
42#[derive(Clone, Copy, Debug, PartialEq)]
43#[repr(u8)]
44pub enum UDCTRL_A {
45    #[doc = "0: The data transfer is controlled by SW. Transfer is performed as soon as possible"]
46    REGULAR = 0,
47    #[doc = "1: The data transfer is done at the next event triggered by the Frame Counter"]
48    FCEVENT = 1,
49    #[doc = "2: The data transfer is done continuously at every LCD frame start"]
50    FRAMESTART = 2,
51}
52impl From<UDCTRL_A> for u8 {
53    #[inline(always)]
54    fn from(variant: UDCTRL_A) -> Self {
55        variant as _
56    }
57}
58#[doc = "Field `UDCTRL` reader - Update Data Control"]
59pub type UDCTRL_R = crate::FieldReader<u8, UDCTRL_A>;
60impl UDCTRL_R {
61    #[doc = "Get enumerated values variant"]
62    #[inline(always)]
63    pub fn variant(&self) -> Option<UDCTRL_A> {
64        match self.bits {
65            0 => Some(UDCTRL_A::REGULAR),
66            1 => Some(UDCTRL_A::FCEVENT),
67            2 => Some(UDCTRL_A::FRAMESTART),
68            _ => None,
69        }
70    }
71    #[doc = "Checks if the value of the field is `REGULAR`"]
72    #[inline(always)]
73    pub fn is_regular(&self) -> bool {
74        *self == UDCTRL_A::REGULAR
75    }
76    #[doc = "Checks if the value of the field is `FCEVENT`"]
77    #[inline(always)]
78    pub fn is_fcevent(&self) -> bool {
79        *self == UDCTRL_A::FCEVENT
80    }
81    #[doc = "Checks if the value of the field is `FRAMESTART`"]
82    #[inline(always)]
83    pub fn is_framestart(&self) -> bool {
84        *self == UDCTRL_A::FRAMESTART
85    }
86}
87#[doc = "Field `UDCTRL` writer - Update Data Control"]
88pub type UDCTRL_W<'a> = crate::FieldWriter<'a, u32, CTRL_SPEC, u8, UDCTRL_A, 2, 1>;
89impl<'a> UDCTRL_W<'a> {
90    #[doc = "The data transfer is controlled by SW. Transfer is performed as soon as possible"]
91    #[inline(always)]
92    pub fn regular(self) -> &'a mut W {
93        self.variant(UDCTRL_A::REGULAR)
94    }
95    #[doc = "The data transfer is done at the next event triggered by the Frame Counter"]
96    #[inline(always)]
97    pub fn fcevent(self) -> &'a mut W {
98        self.variant(UDCTRL_A::FCEVENT)
99    }
100    #[doc = "The data transfer is done continuously at every LCD frame start"]
101    #[inline(always)]
102    pub fn framestart(self) -> &'a mut W {
103        self.variant(UDCTRL_A::FRAMESTART)
104    }
105}
106#[doc = "Field `DSC` reader - Direct Segment Control"]
107pub type DSC_R = crate::BitReader<bool>;
108#[doc = "Field `DSC` writer - Direct Segment Control"]
109pub type DSC_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 23>;
110impl R {
111    #[doc = "Bit 0 - LCD Enable"]
112    #[inline(always)]
113    pub fn en(&self) -> EN_R {
114        EN_R::new((self.bits & 1) != 0)
115    }
116    #[doc = "Bits 1:2 - Update Data Control"]
117    #[inline(always)]
118    pub fn udctrl(&self) -> UDCTRL_R {
119        UDCTRL_R::new(((self.bits >> 1) & 3) as u8)
120    }
121    #[doc = "Bit 23 - Direct Segment Control"]
122    #[inline(always)]
123    pub fn dsc(&self) -> DSC_R {
124        DSC_R::new(((self.bits >> 23) & 1) != 0)
125    }
126}
127impl W {
128    #[doc = "Bit 0 - LCD Enable"]
129    #[inline(always)]
130    pub fn en(&mut self) -> EN_W {
131        EN_W::new(self)
132    }
133    #[doc = "Bits 1:2 - Update Data Control"]
134    #[inline(always)]
135    pub fn udctrl(&mut self) -> UDCTRL_W {
136        UDCTRL_W::new(self)
137    }
138    #[doc = "Bit 23 - Direct Segment Control"]
139    #[inline(always)]
140    pub fn dsc(&mut self) -> DSC_W {
141        DSC_W::new(self)
142    }
143    #[doc = "Writes raw bits to the register."]
144    #[inline(always)]
145    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
146        self.0.bits(bits);
147        self
148    }
149}
150#[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
151pub struct CTRL_SPEC;
152impl crate::RegisterSpec for CTRL_SPEC {
153    type Ux = u32;
154}
155#[doc = "`read()` method returns [ctrl::R](R) reader structure"]
156impl crate::Readable for CTRL_SPEC {
157    type Reader = R;
158}
159#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
160impl crate::Writable for CTRL_SPEC {
161    type Writer = W;
162}
163#[doc = "`reset()` method sets CTRL to value 0"]
164impl crate::Resettable for CTRL_SPEC {
165    #[inline(always)]
166    fn reset_value() -> Self::Ux {
167        0
168    }
169}
efm32lg880_pac/lcd/ctrl.rs

efm32lg880_pac/lcd/
ctrl.rs
