efm32lg395_pac/usb/
doep1_int.rs

1#[doc = "Register `DOEP1_INT` reader"]
2pub struct R(crate::R<DOEP1_INT_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DOEP1_INT_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DOEP1_INT_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DOEP1_INT_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `DOEP1_INT` writer"]
17pub struct W(crate::W<DOEP1_INT_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DOEP1_INT_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DOEP1_INT_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DOEP1_INT_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `XFERCOMPL` reader - Transfer Completed Interrupt"]
38pub type XFERCOMPL_R = crate::BitReader<bool>;
39#[doc = "Field `XFERCOMPL` writer - Transfer Completed Interrupt"]
40pub type XFERCOMPL_W<'a> = crate::BitWriter<'a, u32, DOEP1_INT_SPEC, bool, 0>;
41#[doc = "Field `EPDISBLD` reader - Endpoint Disabled Interrupt"]
42pub type EPDISBLD_R = crate::BitReader<bool>;
43#[doc = "Field `EPDISBLD` writer - Endpoint Disabled Interrupt"]
44pub type EPDISBLD_W<'a> = crate::BitWriter<'a, u32, DOEP1_INT_SPEC, bool, 1>;
45#[doc = "Field `AHBERR` reader - AHB Error"]
46pub type AHBERR_R = crate::BitReader<bool>;
47#[doc = "Field `AHBERR` writer - AHB Error"]
48pub type AHBERR_W<'a> = crate::BitWriter<'a, u32, DOEP1_INT_SPEC, bool, 2>;
49#[doc = "Field `SETUP` reader - Setup Phase Done"]
50pub type SETUP_R = crate::BitReader<bool>;
51#[doc = "Field `SETUP` writer - Setup Phase Done"]
52pub type SETUP_W<'a> = crate::BitWriter<'a, u32, DOEP1_INT_SPEC, bool, 3>;
53#[doc = "Field `OUTTKNEPDIS` reader - OUT Token Received When Endpoint Disabled"]
54pub type OUTTKNEPDIS_R = crate::BitReader<bool>;
55#[doc = "Field `OUTTKNEPDIS` writer - OUT Token Received When Endpoint Disabled"]
56pub type OUTTKNEPDIS_W<'a> = crate::BitWriter<'a, u32, DOEP1_INT_SPEC, bool, 4>;
57#[doc = "Field `BACK2BACKSETUP` reader - Back-to-Back SETUP Packets Received"]
58pub type BACK2BACKSETUP_R = crate::BitReader<bool>;
59#[doc = "Field `BACK2BACKSETUP` writer - Back-to-Back SETUP Packets Received"]
60pub type BACK2BACKSETUP_W<'a> = crate::BitWriter<'a, u32, DOEP1_INT_SPEC, bool, 6>;
61#[doc = "Field `PKTDRPSTS` reader - Packet Drop Status"]
62pub type PKTDRPSTS_R = crate::BitReader<bool>;
63#[doc = "Field `PKTDRPSTS` writer - Packet Drop Status"]
64pub type PKTDRPSTS_W<'a> = crate::BitWriter<'a, u32, DOEP1_INT_SPEC, bool, 11>;
65#[doc = "Field `BBLEERR` reader - Babble Error"]
66pub type BBLEERR_R = crate::BitReader<bool>;
67#[doc = "Field `BBLEERR` writer - Babble Error"]
68pub type BBLEERR_W<'a> = crate::BitWriter<'a, u32, DOEP1_INT_SPEC, bool, 12>;
69#[doc = "Field `NAKINTRPT` reader - NAK Interrupt"]
70pub type NAKINTRPT_R = crate::BitReader<bool>;
71#[doc = "Field `NAKINTRPT` writer - NAK Interrupt"]
72pub type NAKINTRPT_W<'a> = crate::BitWriter<'a, u32, DOEP1_INT_SPEC, bool, 13>;
73impl R {
74    #[doc = "Bit 0 - Transfer Completed Interrupt"]
75    #[inline(always)]
76    pub fn xfercompl(&self) -> XFERCOMPL_R {
77        XFERCOMPL_R::new((self.bits & 1) != 0)
78    }
79    #[doc = "Bit 1 - Endpoint Disabled Interrupt"]
80    #[inline(always)]
81    pub fn epdisbld(&self) -> EPDISBLD_R {
82        EPDISBLD_R::new(((self.bits >> 1) & 1) != 0)
83    }
84    #[doc = "Bit 2 - AHB Error"]
85    #[inline(always)]
86    pub fn ahberr(&self) -> AHBERR_R {
87        AHBERR_R::new(((self.bits >> 2) & 1) != 0)
88    }
89    #[doc = "Bit 3 - Setup Phase Done"]
90    #[inline(always)]
91    pub fn setup(&self) -> SETUP_R {
92        SETUP_R::new(((self.bits >> 3) & 1) != 0)
93    }
94    #[doc = "Bit 4 - OUT Token Received When Endpoint Disabled"]
95    #[inline(always)]
96    pub fn outtknepdis(&self) -> OUTTKNEPDIS_R {
97        OUTTKNEPDIS_R::new(((self.bits >> 4) & 1) != 0)
98    }
99    #[doc = "Bit 6 - Back-to-Back SETUP Packets Received"]
100    #[inline(always)]
101    pub fn back2backsetup(&self) -> BACK2BACKSETUP_R {
102        BACK2BACKSETUP_R::new(((self.bits >> 6) & 1) != 0)
103    }
104    #[doc = "Bit 11 - Packet Drop Status"]
105    #[inline(always)]
106    pub fn pktdrpsts(&self) -> PKTDRPSTS_R {
107        PKTDRPSTS_R::new(((self.bits >> 11) & 1) != 0)
108    }
109    #[doc = "Bit 12 - Babble Error"]
110    #[inline(always)]
111    pub fn bbleerr(&self) -> BBLEERR_R {
112        BBLEERR_R::new(((self.bits >> 12) & 1) != 0)
113    }
114    #[doc = "Bit 13 - NAK Interrupt"]
115    #[inline(always)]
116    pub fn nakintrpt(&self) -> NAKINTRPT_R {
117        NAKINTRPT_R::new(((self.bits >> 13) & 1) != 0)
118    }
119}
120impl W {
121    #[doc = "Bit 0 - Transfer Completed Interrupt"]
122    #[inline(always)]
123    pub fn xfercompl(&mut self) -> XFERCOMPL_W {
124        XFERCOMPL_W::new(self)
125    }
126    #[doc = "Bit 1 - Endpoint Disabled Interrupt"]
127    #[inline(always)]
128    pub fn epdisbld(&mut self) -> EPDISBLD_W {
129        EPDISBLD_W::new(self)
130    }
131    #[doc = "Bit 2 - AHB Error"]
132    #[inline(always)]
133    pub fn ahberr(&mut self) -> AHBERR_W {
134        AHBERR_W::new(self)
135    }
136    #[doc = "Bit 3 - Setup Phase Done"]
137    #[inline(always)]
138    pub fn setup(&mut self) -> SETUP_W {
139        SETUP_W::new(self)
140    }
141    #[doc = "Bit 4 - OUT Token Received When Endpoint Disabled"]
142    #[inline(always)]
143    pub fn outtknepdis(&mut self) -> OUTTKNEPDIS_W {
144        OUTTKNEPDIS_W::new(self)
145    }
146    #[doc = "Bit 6 - Back-to-Back SETUP Packets Received"]
147    #[inline(always)]
148    pub fn back2backsetup(&mut self) -> BACK2BACKSETUP_W {
149        BACK2BACKSETUP_W::new(self)
150    }
151    #[doc = "Bit 11 - Packet Drop Status"]
152    #[inline(always)]
153    pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W {
154        PKTDRPSTS_W::new(self)
155    }
156    #[doc = "Bit 12 - Babble Error"]
157    #[inline(always)]
158    pub fn bbleerr(&mut self) -> BBLEERR_W {
159        BBLEERR_W::new(self)
160    }
161    #[doc = "Bit 13 - NAK Interrupt"]
162    #[inline(always)]
163    pub fn nakintrpt(&mut self) -> NAKINTRPT_W {
164        NAKINTRPT_W::new(self)
165    }
166    #[doc = "Writes raw bits to the register."]
167    #[inline(always)]
168    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
169        self.0.bits(bits);
170        self
171    }
172}
173#[doc = "Device OUT Endpoint x+1 Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doep1_int](index.html) module"]
174pub struct DOEP1_INT_SPEC;
175impl crate::RegisterSpec for DOEP1_INT_SPEC {
176    type Ux = u32;
177}
178#[doc = "`read()` method returns [doep1_int::R](R) reader structure"]
179impl crate::Readable for DOEP1_INT_SPEC {
180    type Reader = R;
181}
182#[doc = "`write(|w| ..)` method takes [doep1_int::W](W) writer structure"]
183impl crate::Writable for DOEP1_INT_SPEC {
184    type Writer = W;
185}
186#[doc = "`reset()` method sets DOEP1_INT to value 0"]
187impl crate::Resettable for DOEP1_INT_SPEC {
188    #[inline(always)]
189    fn reset_value() -> Self::Ux {
190        0
191    }
192}
efm32lg395_pac/usb/doep1_int.rs

efm32lg395_pac/usb/
doep1_int.rs
