Struct efm32lg390_pac::usb::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {

    pub ctrl: Reg<CTRL_SPEC>,
    pub status: Reg<STATUS_SPEC>,
    pub if_: Reg<IF_SPEC>,
    pub ifs: Reg<IFS_SPEC>,
    pub ifc: Reg<IFC_SPEC>,
    pub ien: Reg<IEN_SPEC>,
    pub route: Reg<ROUTE_SPEC>,
    pub gotgctl: Reg<GOTGCTL_SPEC>,
    pub gotgint: Reg<GOTGINT_SPEC>,
    pub gahbcfg: Reg<GAHBCFG_SPEC>,
    pub gusbcfg: Reg<GUSBCFG_SPEC>,
    pub grstctl: Reg<GRSTCTL_SPEC>,
    pub gintsts: Reg<GINTSTS_SPEC>,
    pub gintmsk: Reg<GINTMSK_SPEC>,
    pub grxstsr: Reg<GRXSTSR_SPEC>,
    pub grxstsp: Reg<GRXSTSP_SPEC>,
    pub grxfsiz: Reg<GRXFSIZ_SPEC>,
    pub gnptxfsiz: Reg<GNPTXFSIZ_SPEC>,
    pub gnptxsts: Reg<GNPTXSTS_SPEC>,
    pub gdfifocfg: Reg<GDFIFOCFG_SPEC>,
    pub hptxfsiz: Reg<HPTXFSIZ_SPEC>,
    pub dieptxf1: Reg<DIEPTXF1_SPEC>,
    pub dieptxf2: Reg<DIEPTXF2_SPEC>,
    pub dieptxf3: Reg<DIEPTXF3_SPEC>,
    pub dieptxf4: Reg<DIEPTXF4_SPEC>,
    pub dieptxf5: Reg<DIEPTXF5_SPEC>,
    pub dieptxf6: Reg<DIEPTXF6_SPEC>,
    pub hcfg: Reg<HCFG_SPEC>,
    pub hfir: Reg<HFIR_SPEC>,
    pub hfnum: Reg<HFNUM_SPEC>,
    pub hptxsts: Reg<HPTXSTS_SPEC>,
    pub haint: Reg<HAINT_SPEC>,
    pub haintmsk: Reg<HAINTMSK_SPEC>,
    pub hprt: Reg<HPRT_SPEC>,
    pub hc0_char: Reg<HC0_CHAR_SPEC>,
    pub hc0_int: Reg<HC0_INT_SPEC>,
    pub hc0_intmsk: Reg<HC0_INTMSK_SPEC>,
    pub hc0_tsiz: Reg<HC0_TSIZ_SPEC>,
    pub hc0_dmaaddr: Reg<HC0_DMAADDR_SPEC>,
    pub hc1_char: Reg<HC1_CHAR_SPEC>,
    pub hc1_int: Reg<HC1_INT_SPEC>,
    pub hc1_intmsk: Reg<HC1_INTMSK_SPEC>,
    pub hc1_tsiz: Reg<HC1_TSIZ_SPEC>,
    pub hc1_dmaaddr: Reg<HC1_DMAADDR_SPEC>,
    pub hc2_char: Reg<HC2_CHAR_SPEC>,
    pub hc2_int: Reg<HC2_INT_SPEC>,
    pub hc2_intmsk: Reg<HC2_INTMSK_SPEC>,
    pub hc2_tsiz: Reg<HC2_TSIZ_SPEC>,
    pub hc2_dmaaddr: Reg<HC2_DMAADDR_SPEC>,
    pub hc3_char: Reg<HC3_CHAR_SPEC>,
    pub hc3_int: Reg<HC3_INT_SPEC>,
    pub hc3_intmsk: Reg<HC3_INTMSK_SPEC>,
    pub hc3_tsiz: Reg<HC3_TSIZ_SPEC>,
    pub hc3_dmaaddr: Reg<HC3_DMAADDR_SPEC>,
    pub hc4_char: Reg<HC4_CHAR_SPEC>,
    pub hc4_int: Reg<HC4_INT_SPEC>,
    pub hc4_intmsk: Reg<HC4_INTMSK_SPEC>,
    pub hc4_tsiz: Reg<HC4_TSIZ_SPEC>,
    pub hc4_dmaaddr: Reg<HC4_DMAADDR_SPEC>,
    pub hc5_char: Reg<HC5_CHAR_SPEC>,
    pub hc5_int: Reg<HC5_INT_SPEC>,
    pub hc5_intmsk: Reg<HC5_INTMSK_SPEC>,
    pub hc5_tsiz: Reg<HC5_TSIZ_SPEC>,
    pub hc5_dmaaddr: Reg<HC5_DMAADDR_SPEC>,
    pub hc6_char: Reg<HC6_CHAR_SPEC>,
    pub hc6_int: Reg<HC6_INT_SPEC>,
    pub hc6_intmsk: Reg<HC6_INTMSK_SPEC>,
    pub hc6_tsiz: Reg<HC6_TSIZ_SPEC>,
    pub hc6_dmaaddr: Reg<HC6_DMAADDR_SPEC>,
    pub hc7_char: Reg<HC7_CHAR_SPEC>,
    pub hc7_int: Reg<HC7_INT_SPEC>,
    pub hc7_intmsk: Reg<HC7_INTMSK_SPEC>,
    pub hc7_tsiz: Reg<HC7_TSIZ_SPEC>,
    pub hc7_dmaaddr: Reg<HC7_DMAADDR_SPEC>,
    pub hc8_char: Reg<HC8_CHAR_SPEC>,
    pub hc8_int: Reg<HC8_INT_SPEC>,
    pub hc8_intmsk: Reg<HC8_INTMSK_SPEC>,
    pub hc8_tsiz: Reg<HC8_TSIZ_SPEC>,
    pub hc8_dmaaddr: Reg<HC8_DMAADDR_SPEC>,
    pub hc9_char: Reg<HC9_CHAR_SPEC>,
    pub hc9_int: Reg<HC9_INT_SPEC>,
    pub hc9_intmsk: Reg<HC9_INTMSK_SPEC>,
    pub hc9_tsiz: Reg<HC9_TSIZ_SPEC>,
    pub hc9_dmaaddr: Reg<HC9_DMAADDR_SPEC>,
    pub hc10_char: Reg<HC10_CHAR_SPEC>,
    pub hc10_int: Reg<HC10_INT_SPEC>,
    pub hc10_intmsk: Reg<HC10_INTMSK_SPEC>,
    pub hc10_tsiz: Reg<HC10_TSIZ_SPEC>,
    pub hc10_dmaaddr: Reg<HC10_DMAADDR_SPEC>,
    pub hc11_char: Reg<HC11_CHAR_SPEC>,
    pub hc11_int: Reg<HC11_INT_SPEC>,
    pub hc11_intmsk: Reg<HC11_INTMSK_SPEC>,
    pub hc11_tsiz: Reg<HC11_TSIZ_SPEC>,
    pub hc11_dmaaddr: Reg<HC11_DMAADDR_SPEC>,
    pub hc12_char: Reg<HC12_CHAR_SPEC>,
    pub hc12_int: Reg<HC12_INT_SPEC>,
    pub hc12_intmsk: Reg<HC12_INTMSK_SPEC>,
    pub hc12_tsiz: Reg<HC12_TSIZ_SPEC>,
    pub hc12_dmaaddr: Reg<HC12_DMAADDR_SPEC>,
    pub hc13_char: Reg<HC13_CHAR_SPEC>,
    pub hc13_int: Reg<HC13_INT_SPEC>,
    pub hc13_intmsk: Reg<HC13_INTMSK_SPEC>,
    pub hc13_tsiz: Reg<HC13_TSIZ_SPEC>,
    pub hc13_dmaaddr: Reg<HC13_DMAADDR_SPEC>,
    pub dcfg: Reg<DCFG_SPEC>,
    pub dctl: Reg<DCTL_SPEC>,
    pub dsts: Reg<DSTS_SPEC>,
    pub diepmsk: Reg<DIEPMSK_SPEC>,
    pub doepmsk: Reg<DOEPMSK_SPEC>,
    pub daint: Reg<DAINT_SPEC>,
    pub daintmsk: Reg<DAINTMSK_SPEC>,
    pub dvbusdis: Reg<DVBUSDIS_SPEC>,
    pub dvbuspulse: Reg<DVBUSPULSE_SPEC>,
    pub diepempmsk: Reg<DIEPEMPMSK_SPEC>,
    pub diep0ctl: Reg<DIEP0CTL_SPEC>,
    pub diep0int: Reg<DIEP0INT_SPEC>,
    pub diep0tsiz: Reg<DIEP0TSIZ_SPEC>,
    pub diep0dmaaddr: Reg<DIEP0DMAADDR_SPEC>,
    pub diep0txfsts: Reg<DIEP0TXFSTS_SPEC>,
    pub diep0_ctl: Reg<DIEP0_CTL_SPEC>,
    pub diep0_int: Reg<DIEP0_INT_SPEC>,
    pub diep0_tsiz: Reg<DIEP0_TSIZ_SPEC>,
    pub diep0_dmaaddr: Reg<DIEP0_DMAADDR_SPEC>,
    pub diep0_txfsts: Reg<DIEP0_TXFSTS_SPEC>,
    pub diep1_ctl: Reg<DIEP1_CTL_SPEC>,
    pub diep1_int: Reg<DIEP1_INT_SPEC>,
    pub diep1_tsiz: Reg<DIEP1_TSIZ_SPEC>,
    pub diep1_dmaaddr: Reg<DIEP1_DMAADDR_SPEC>,
    pub diep1_txfsts: Reg<DIEP1_TXFSTS_SPEC>,
    pub diep2_ctl: Reg<DIEP2_CTL_SPEC>,
    pub diep2_int: Reg<DIEP2_INT_SPEC>,
    pub diep2_tsiz: Reg<DIEP2_TSIZ_SPEC>,
    pub diep2_dmaaddr: Reg<DIEP2_DMAADDR_SPEC>,
    pub diep2_txfsts: Reg<DIEP2_TXFSTS_SPEC>,
    pub diep3_ctl: Reg<DIEP3_CTL_SPEC>,
    pub diep3_int: Reg<DIEP3_INT_SPEC>,
    pub diep3_tsiz: Reg<DIEP3_TSIZ_SPEC>,
    pub diep3_dmaaddr: Reg<DIEP3_DMAADDR_SPEC>,
    pub diep3_txfsts: Reg<DIEP3_TXFSTS_SPEC>,
    pub diep4_ctl: Reg<DIEP4_CTL_SPEC>,
    pub diep4_int: Reg<DIEP4_INT_SPEC>,
    pub diep4_tsiz: Reg<DIEP4_TSIZ_SPEC>,
    pub diep4_dmaaddr: Reg<DIEP4_DMAADDR_SPEC>,
    pub diep4_txfsts: Reg<DIEP4_TXFSTS_SPEC>,
    pub diep5_ctl: Reg<DIEP5_CTL_SPEC>,
    pub diep5_int: Reg<DIEP5_INT_SPEC>,
    pub diep5_tsiz: Reg<DIEP5_TSIZ_SPEC>,
    pub diep5_dmaaddr: Reg<DIEP5_DMAADDR_SPEC>,
    pub diep5_txfsts: Reg<DIEP5_TXFSTS_SPEC>,
    pub doep0ctl: Reg<DOEP0CTL_SPEC>,
    pub doep0int: Reg<DOEP0INT_SPEC>,
    pub doep0tsiz: Reg<DOEP0TSIZ_SPEC>,
    pub doep0dmaaddr: Reg<DOEP0DMAADDR_SPEC>,
    pub doep0_ctl: Reg<DOEP0_CTL_SPEC>,
    pub doep0_int: Reg<DOEP0_INT_SPEC>,
    pub doep0_tsiz: Reg<DOEP0_TSIZ_SPEC>,
    pub doep0_dmaaddr: Reg<DOEP0_DMAADDR_SPEC>,
    pub doep1_ctl: Reg<DOEP1_CTL_SPEC>,
    pub doep1_int: Reg<DOEP1_INT_SPEC>,
    pub doep1_tsiz: Reg<DOEP1_TSIZ_SPEC>,
    pub doep1_dmaaddr: Reg<DOEP1_DMAADDR_SPEC>,
    pub doep2_ctl: Reg<DOEP2_CTL_SPEC>,
    pub doep2_int: Reg<DOEP2_INT_SPEC>,
    pub doep2_tsiz: Reg<DOEP2_TSIZ_SPEC>,
    pub doep2_dmaaddr: Reg<DOEP2_DMAADDR_SPEC>,
    pub doep3_ctl: Reg<DOEP3_CTL_SPEC>,
    pub doep3_int: Reg<DOEP3_INT_SPEC>,
    pub doep3_tsiz: Reg<DOEP3_TSIZ_SPEC>,
    pub doep3_dmaaddr: Reg<DOEP3_DMAADDR_SPEC>,
    pub doep4_ctl: Reg<DOEP4_CTL_SPEC>,
    pub doep4_int: Reg<DOEP4_INT_SPEC>,
    pub doep4_tsiz: Reg<DOEP4_TSIZ_SPEC>,
    pub doep4_dmaaddr: Reg<DOEP4_DMAADDR_SPEC>,
    pub doep5_ctl: Reg<DOEP5_CTL_SPEC>,
    pub doep5_int: Reg<DOEP5_INT_SPEC>,
    pub doep5_tsiz: Reg<DOEP5_TSIZ_SPEC>,
    pub doep5_dmaaddr: Reg<DOEP5_DMAADDR_SPEC>,
    pub pcgcctl: Reg<PCGCCTL_SPEC>,
    /* private fields */
}

Register block

Fields

ctrl: Reg<CTRL_SPEC>

0x00 - System Control Register

status: Reg<STATUS_SPEC>

0x04 - System Status Register

if_: Reg<IF_SPEC>

0x08 - Interrupt Flag Register

ifs: Reg<IFS_SPEC>

0x0c - Interrupt Flag Set Register

ifc: Reg<IFC_SPEC>

0x10 - Interrupt Flag Clear Register

ien: Reg<IEN_SPEC>

0x14 - Interrupt Enable Register

route: Reg<ROUTE_SPEC>

0x18 - I/O Routing Register

gotgctl: Reg<GOTGCTL_SPEC>

0x3c000 - OTG Control and Status Register

gotgint: Reg<GOTGINT_SPEC>

0x3c004 - OTG Interrupt Register

gahbcfg: Reg<GAHBCFG_SPEC>

0x3c008 - AHB Configuration Register

gusbcfg: Reg<GUSBCFG_SPEC>

0x3c00c - USB Configuration Register

grstctl: Reg<GRSTCTL_SPEC>

0x3c010 - Reset Register

gintsts: Reg<GINTSTS_SPEC>

0x3c014 - Interrupt Register

gintmsk: Reg<GINTMSK_SPEC>

0x3c018 - Interrupt Mask Register

grxstsr: Reg<GRXSTSR_SPEC>

0x3c01c - Receive Status Debug Read Register

grxstsp: Reg<GRXSTSP_SPEC>

0x3c020 - Receive Status Read and Pop Register

grxfsiz: Reg<GRXFSIZ_SPEC>

0x3c024 - Receive FIFO Size Register

gnptxfsiz: Reg<GNPTXFSIZ_SPEC>

0x3c028 - Non-periodic Transmit FIFO Size Register

gnptxsts: Reg<GNPTXSTS_SPEC>

0x3c02c - Non-periodic Transmit FIFO/Queue Status Register

gdfifocfg: Reg<GDFIFOCFG_SPEC>

0x3c05c - Global DFIFO Configuration Register

hptxfsiz: Reg<HPTXFSIZ_SPEC>

0x3c100 - Host Periodic Transmit FIFO Size Register

dieptxf1: Reg<DIEPTXF1_SPEC>

0x3c104 - Device IN Endpoint Transmit FIFO 1 Size Register

dieptxf2: Reg<DIEPTXF2_SPEC>

0x3c108 - Device IN Endpoint Transmit FIFO 2 Size Register

dieptxf3: Reg<DIEPTXF3_SPEC>

0x3c10c - Device IN Endpoint Transmit FIFO 3 Size Register

dieptxf4: Reg<DIEPTXF4_SPEC>

0x3c110 - Device IN Endpoint Transmit FIFO 4 Size Register

dieptxf5: Reg<DIEPTXF5_SPEC>

0x3c114 - Device IN Endpoint Transmit FIFO 5 Size Register

dieptxf6: Reg<DIEPTXF6_SPEC>

0x3c118 - Device IN Endpoint Transmit FIFO 6 Size Register

hcfg: Reg<HCFG_SPEC>

0x3c400 - Host Configuration Register

hfir: Reg<HFIR_SPEC>

0x3c404 - Host Frame Interval Register

hfnum: Reg<HFNUM_SPEC>

0x3c408 - Host Frame Number/Frame Time Remaining Register

hptxsts: Reg<HPTXSTS_SPEC>

0x3c410 - Host Periodic Transmit FIFO/Queue Status Register

haint: Reg<HAINT_SPEC>

0x3c414 - Host All Channels Interrupt Register

haintmsk: Reg<HAINTMSK_SPEC>

0x3c418 - Host All Channels Interrupt Mask Register

hprt: Reg<HPRT_SPEC>

0x3c440 - Host Port Control and Status Register

hc0_char: Reg<HC0_CHAR_SPEC>

0x3c500 - Host Channel x Characteristics Register

hc0_int: Reg<HC0_INT_SPEC>

0x3c508 - Host Channel x Interrupt Register

hc0_intmsk: Reg<HC0_INTMSK_SPEC>

0x3c50c - Host Channel x Interrupt Mask Register

hc0_tsiz: Reg<HC0_TSIZ_SPEC>

0x3c510 - Host Channel x Transfer Size Register

hc0_dmaaddr: Reg<HC0_DMAADDR_SPEC>

0x3c514 - Host Channel x DMA Address Register

hc1_char: Reg<HC1_CHAR_SPEC>

0x3c520 - Host Channel x Characteristics Register

hc1_int: Reg<HC1_INT_SPEC>

0x3c528 - Host Channel x Interrupt Register

hc1_intmsk: Reg<HC1_INTMSK_SPEC>

0x3c52c - Host Channel x Interrupt Mask Register

hc1_tsiz: Reg<HC1_TSIZ_SPEC>

0x3c530 - Host Channel x Transfer Size Register

hc1_dmaaddr: Reg<HC1_DMAADDR_SPEC>

0x3c534 - Host Channel x DMA Address Register

hc2_char: Reg<HC2_CHAR_SPEC>

0x3c540 - Host Channel x Characteristics Register

hc2_int: Reg<HC2_INT_SPEC>

0x3c548 - Host Channel x Interrupt Register

hc2_intmsk: Reg<HC2_INTMSK_SPEC>

0x3c54c - Host Channel x Interrupt Mask Register

hc2_tsiz: Reg<HC2_TSIZ_SPEC>

0x3c550 - Host Channel x Transfer Size Register

hc2_dmaaddr: Reg<HC2_DMAADDR_SPEC>

0x3c554 - Host Channel x DMA Address Register

hc3_char: Reg<HC3_CHAR_SPEC>

0x3c560 - Host Channel x Characteristics Register

hc3_int: Reg<HC3_INT_SPEC>

0x3c568 - Host Channel x Interrupt Register

hc3_intmsk: Reg<HC3_INTMSK_SPEC>

0x3c56c - Host Channel x Interrupt Mask Register

hc3_tsiz: Reg<HC3_TSIZ_SPEC>

0x3c570 - Host Channel x Transfer Size Register

hc3_dmaaddr: Reg<HC3_DMAADDR_SPEC>

0x3c574 - Host Channel x DMA Address Register

hc4_char: Reg<HC4_CHAR_SPEC>

0x3c580 - Host Channel x Characteristics Register

hc4_int: Reg<HC4_INT_SPEC>

0x3c588 - Host Channel x Interrupt Register

hc4_intmsk: Reg<HC4_INTMSK_SPEC>

0x3c58c - Host Channel x Interrupt Mask Register

hc4_tsiz: Reg<HC4_TSIZ_SPEC>

0x3c590 - Host Channel x Transfer Size Register

hc4_dmaaddr: Reg<HC4_DMAADDR_SPEC>

0x3c594 - Host Channel x DMA Address Register

hc5_char: Reg<HC5_CHAR_SPEC>

0x3c5a0 - Host Channel x Characteristics Register

hc5_int: Reg<HC5_INT_SPEC>

0x3c5a8 - Host Channel x Interrupt Register

hc5_intmsk: Reg<HC5_INTMSK_SPEC>

0x3c5ac - Host Channel x Interrupt Mask Register

hc5_tsiz: Reg<HC5_TSIZ_SPEC>

0x3c5b0 - Host Channel x Transfer Size Register

hc5_dmaaddr: Reg<HC5_DMAADDR_SPEC>

0x3c5b4 - Host Channel x DMA Address Register

hc6_char: Reg<HC6_CHAR_SPEC>

0x3c5c0 - Host Channel x Characteristics Register

hc6_int: Reg<HC6_INT_SPEC>

0x3c5c8 - Host Channel x Interrupt Register

hc6_intmsk: Reg<HC6_INTMSK_SPEC>

0x3c5cc - Host Channel x Interrupt Mask Register

hc6_tsiz: Reg<HC6_TSIZ_SPEC>

0x3c5d0 - Host Channel x Transfer Size Register

hc6_dmaaddr: Reg<HC6_DMAADDR_SPEC>

0x3c5d4 - Host Channel x DMA Address Register

hc7_char: Reg<HC7_CHAR_SPEC>

0x3c5e0 - Host Channel x Characteristics Register

hc7_int: Reg<HC7_INT_SPEC>

0x3c5e8 - Host Channel x Interrupt Register

hc7_intmsk: Reg<HC7_INTMSK_SPEC>

0x3c5ec - Host Channel x Interrupt Mask Register

hc7_tsiz: Reg<HC7_TSIZ_SPEC>

0x3c5f0 - Host Channel x Transfer Size Register

hc7_dmaaddr: Reg<HC7_DMAADDR_SPEC>

0x3c5f4 - Host Channel x DMA Address Register

hc8_char: Reg<HC8_CHAR_SPEC>

0x3c600 - Host Channel x Characteristics Register

hc8_int: Reg<HC8_INT_SPEC>

0x3c608 - Host Channel x Interrupt Register

hc8_intmsk: Reg<HC8_INTMSK_SPEC>

0x3c60c - Host Channel x Interrupt Mask Register

hc8_tsiz: Reg<HC8_TSIZ_SPEC>

0x3c610 - Host Channel x Transfer Size Register

hc8_dmaaddr: Reg<HC8_DMAADDR_SPEC>

0x3c614 - Host Channel x DMA Address Register

hc9_char: Reg<HC9_CHAR_SPEC>

0x3c620 - Host Channel x Characteristics Register

hc9_int: Reg<HC9_INT_SPEC>

0x3c628 - Host Channel x Interrupt Register

hc9_intmsk: Reg<HC9_INTMSK_SPEC>

0x3c62c - Host Channel x Interrupt Mask Register

hc9_tsiz: Reg<HC9_TSIZ_SPEC>

0x3c630 - Host Channel x Transfer Size Register

hc9_dmaaddr: Reg<HC9_DMAADDR_SPEC>

0x3c634 - Host Channel x DMA Address Register

hc10_char: Reg<HC10_CHAR_SPEC>

0x3c640 - Host Channel x Characteristics Register

hc10_int: Reg<HC10_INT_SPEC>

0x3c648 - Host Channel x Interrupt Register

hc10_intmsk: Reg<HC10_INTMSK_SPEC>

0x3c64c - Host Channel x Interrupt Mask Register

hc10_tsiz: Reg<HC10_TSIZ_SPEC>

0x3c650 - Host Channel x Transfer Size Register

hc10_dmaaddr: Reg<HC10_DMAADDR_SPEC>

0x3c654 - Host Channel x DMA Address Register

hc11_char: Reg<HC11_CHAR_SPEC>

0x3c660 - Host Channel x Characteristics Register

hc11_int: Reg<HC11_INT_SPEC>

0x3c668 - Host Channel x Interrupt Register

hc11_intmsk: Reg<HC11_INTMSK_SPEC>

0x3c66c - Host Channel x Interrupt Mask Register

hc11_tsiz: Reg<HC11_TSIZ_SPEC>

0x3c670 - Host Channel x Transfer Size Register

hc11_dmaaddr: Reg<HC11_DMAADDR_SPEC>

0x3c674 - Host Channel x DMA Address Register

hc12_char: Reg<HC12_CHAR_SPEC>

0x3c680 - Host Channel x Characteristics Register

hc12_int: Reg<HC12_INT_SPEC>

0x3c688 - Host Channel x Interrupt Register

hc12_intmsk: Reg<HC12_INTMSK_SPEC>

0x3c68c - Host Channel x Interrupt Mask Register

hc12_tsiz: Reg<HC12_TSIZ_SPEC>

0x3c690 - Host Channel x Transfer Size Register

hc12_dmaaddr: Reg<HC12_DMAADDR_SPEC>

0x3c694 - Host Channel x DMA Address Register

hc13_char: Reg<HC13_CHAR_SPEC>

0x3c6a0 - Host Channel x Characteristics Register

hc13_int: Reg<HC13_INT_SPEC>

0x3c6a8 - Host Channel x Interrupt Register

hc13_intmsk: Reg<HC13_INTMSK_SPEC>

0x3c6ac - Host Channel x Interrupt Mask Register

hc13_tsiz: Reg<HC13_TSIZ_SPEC>

0x3c6b0 - Host Channel x Transfer Size Register

hc13_dmaaddr: Reg<HC13_DMAADDR_SPEC>

0x3c6b4 - Host Channel x DMA Address Register

dcfg: Reg<DCFG_SPEC>

0x3c800 - Device Configuration Register

dctl: Reg<DCTL_SPEC>

0x3c804 - Device Control Register

dsts: Reg<DSTS_SPEC>

0x3c808 - Device Status Register

diepmsk: Reg<DIEPMSK_SPEC>

0x3c810 - Device IN Endpoint Common Interrupt Mask Register

doepmsk: Reg<DOEPMSK_SPEC>

0x3c814 - Device OUT Endpoint Common Interrupt Mask Register

daint: Reg<DAINT_SPEC>

0x3c818 - Device All Endpoints Interrupt Register

daintmsk: Reg<DAINTMSK_SPEC>

0x3c81c - Device All Endpoints Interrupt Mask Register

dvbusdis: Reg<DVBUSDIS_SPEC>

0x3c828 - Device VBUS Discharge Time Register

dvbuspulse: Reg<DVBUSPULSE_SPEC>

0x3c82c - Device VBUS Pulsing Time Register

diepempmsk: Reg<DIEPEMPMSK_SPEC>

0x3c834 - Device IN Endpoint FIFO Empty Interrupt Mask Register

diep0ctl: Reg<DIEP0CTL_SPEC>

0x3c900 - Device IN Endpoint 0 Control Register

diep0int: Reg<DIEP0INT_SPEC>

0x3c908 - Device IN Endpoint 0 Interrupt Register

diep0tsiz: Reg<DIEP0TSIZ_SPEC>

0x3c910 - Device IN Endpoint 0 Transfer Size Register

diep0dmaaddr: Reg<DIEP0DMAADDR_SPEC>

0x3c914 - Device IN Endpoint 0 DMA Address Register

diep0txfsts: Reg<DIEP0TXFSTS_SPEC>

0x3c918 - Device IN Endpoint 0 Transmit FIFO Status Register

diep0_ctl: Reg<DIEP0_CTL_SPEC>

0x3c920 - Device IN Endpoint x+1 Control Register

diep0_int: Reg<DIEP0_INT_SPEC>

0x3c928 - Device IN Endpoint x+1 Interrupt Register

diep0_tsiz: Reg<DIEP0_TSIZ_SPEC>

0x3c930 - Device IN Endpoint x+1 Transfer Size Register

diep0_dmaaddr: Reg<DIEP0_DMAADDR_SPEC>

0x3c934 - Device IN Endpoint x+1 DMA Address Register

diep0_txfsts: Reg<DIEP0_TXFSTS_SPEC>

0x3c938 - Device IN Endpoint x+1 Transmit FIFO Status Register

diep1_ctl: Reg<DIEP1_CTL_SPEC>

0x3c940 - Device IN Endpoint x+1 Control Register

diep1_int: Reg<DIEP1_INT_SPEC>

0x3c948 - Device IN Endpoint x+1 Interrupt Register

diep1_tsiz: Reg<DIEP1_TSIZ_SPEC>

0x3c950 - Device IN Endpoint x+1 Transfer Size Register

diep1_dmaaddr: Reg<DIEP1_DMAADDR_SPEC>

0x3c954 - Device IN Endpoint x+1 DMA Address Register

diep1_txfsts: Reg<DIEP1_TXFSTS_SPEC>

0x3c958 - Device IN Endpoint x+1 Transmit FIFO Status Register

diep2_ctl: Reg<DIEP2_CTL_SPEC>

0x3c960 - Device IN Endpoint x+1 Control Register

diep2_int: Reg<DIEP2_INT_SPEC>

0x3c968 - Device IN Endpoint x+1 Interrupt Register

diep2_tsiz: Reg<DIEP2_TSIZ_SPEC>

0x3c970 - Device IN Endpoint x+1 Transfer Size Register

diep2_dmaaddr: Reg<DIEP2_DMAADDR_SPEC>

0x3c974 - Device IN Endpoint x+1 DMA Address Register

diep2_txfsts: Reg<DIEP2_TXFSTS_SPEC>

0x3c978 - Device IN Endpoint x+1 Transmit FIFO Status Register

diep3_ctl: Reg<DIEP3_CTL_SPEC>

0x3c980 - Device IN Endpoint x+1 Control Register

diep3_int: Reg<DIEP3_INT_SPEC>

0x3c988 - Device IN Endpoint x+1 Interrupt Register

diep3_tsiz: Reg<DIEP3_TSIZ_SPEC>

0x3c990 - Device IN Endpoint x+1 Transfer Size Register

diep3_dmaaddr: Reg<DIEP3_DMAADDR_SPEC>

0x3c994 - Device IN Endpoint x+1 DMA Address Register

diep3_txfsts: Reg<DIEP3_TXFSTS_SPEC>

0x3c998 - Device IN Endpoint x+1 Transmit FIFO Status Register

diep4_ctl: Reg<DIEP4_CTL_SPEC>

0x3c9a0 - Device IN Endpoint x+1 Control Register

diep4_int: Reg<DIEP4_INT_SPEC>

0x3c9a8 - Device IN Endpoint x+1 Interrupt Register

diep4_tsiz: Reg<DIEP4_TSIZ_SPEC>

0x3c9b0 - Device IN Endpoint x+1 Transfer Size Register

diep4_dmaaddr: Reg<DIEP4_DMAADDR_SPEC>

0x3c9b4 - Device IN Endpoint x+1 DMA Address Register

diep4_txfsts: Reg<DIEP4_TXFSTS_SPEC>

0x3c9b8 - Device IN Endpoint x+1 Transmit FIFO Status Register

diep5_ctl: Reg<DIEP5_CTL_SPEC>

0x3c9c0 - Device IN Endpoint x+1 Control Register

diep5_int: Reg<DIEP5_INT_SPEC>

0x3c9c8 - Device IN Endpoint x+1 Interrupt Register

diep5_tsiz: Reg<DIEP5_TSIZ_SPEC>

0x3c9d0 - Device IN Endpoint x+1 Transfer Size Register

diep5_dmaaddr: Reg<DIEP5_DMAADDR_SPEC>

0x3c9d4 - Device IN Endpoint x+1 DMA Address Register

diep5_txfsts: Reg<DIEP5_TXFSTS_SPEC>

0x3c9d8 - Device IN Endpoint x+1 Transmit FIFO Status Register

doep0ctl: Reg<DOEP0CTL_SPEC>

0x3cb00 - Device OUT Endpoint 0 Control Register

doep0int: Reg<DOEP0INT_SPEC>

0x3cb08 - Device OUT Endpoint 0 Interrupt Register

doep0tsiz: Reg<DOEP0TSIZ_SPEC>

0x3cb10 - Device OUT Endpoint 0 Transfer Size Register

doep0dmaaddr: Reg<DOEP0DMAADDR_SPEC>

0x3cb14 - Device OUT Endpoint 0 DMA Address Register

doep0_ctl: Reg<DOEP0_CTL_SPEC>

0x3cb20 - Device OUT Endpoint x+1 Control Register

doep0_int: Reg<DOEP0_INT_SPEC>

0x3cb28 - Device OUT Endpoint x+1 Interrupt Register

doep0_tsiz: Reg<DOEP0_TSIZ_SPEC>

0x3cb30 - Device OUT Endpoint x+1 Transfer Size Register

doep0_dmaaddr: Reg<DOEP0_DMAADDR_SPEC>

0x3cb34 - Device OUT Endpoint x+1 DMA Address Register

doep1_ctl: Reg<DOEP1_CTL_SPEC>

0x3cb40 - Device OUT Endpoint x+1 Control Register

doep1_int: Reg<DOEP1_INT_SPEC>

0x3cb48 - Device OUT Endpoint x+1 Interrupt Register

doep1_tsiz: Reg<DOEP1_TSIZ_SPEC>

0x3cb50 - Device OUT Endpoint x+1 Transfer Size Register

doep1_dmaaddr: Reg<DOEP1_DMAADDR_SPEC>

0x3cb54 - Device OUT Endpoint x+1 DMA Address Register

doep2_ctl: Reg<DOEP2_CTL_SPEC>

0x3cb60 - Device OUT Endpoint x+1 Control Register

doep2_int: Reg<DOEP2_INT_SPEC>

0x3cb68 - Device OUT Endpoint x+1 Interrupt Register

doep2_tsiz: Reg<DOEP2_TSIZ_SPEC>

0x3cb70 - Device OUT Endpoint x+1 Transfer Size Register

doep2_dmaaddr: Reg<DOEP2_DMAADDR_SPEC>

0x3cb74 - Device OUT Endpoint x+1 DMA Address Register

doep3_ctl: Reg<DOEP3_CTL_SPEC>

0x3cb80 - Device OUT Endpoint x+1 Control Register

doep3_int: Reg<DOEP3_INT_SPEC>

0x3cb88 - Device OUT Endpoint x+1 Interrupt Register

doep3_tsiz: Reg<DOEP3_TSIZ_SPEC>

0x3cb90 - Device OUT Endpoint x+1 Transfer Size Register

doep3_dmaaddr: Reg<DOEP3_DMAADDR_SPEC>

0x3cb94 - Device OUT Endpoint x+1 DMA Address Register

doep4_ctl: Reg<DOEP4_CTL_SPEC>

0x3cba0 - Device OUT Endpoint x+1 Control Register

doep4_int: Reg<DOEP4_INT_SPEC>

0x3cba8 - Device OUT Endpoint x+1 Interrupt Register

doep4_tsiz: Reg<DOEP4_TSIZ_SPEC>

0x3cbb0 - Device OUT Endpoint x+1 Transfer Size Register

doep4_dmaaddr: Reg<DOEP4_DMAADDR_SPEC>

0x3cbb4 - Device OUT Endpoint x+1 DMA Address Register

doep5_ctl: Reg<DOEP5_CTL_SPEC>

0x3cbc0 - Device OUT Endpoint x+1 Control Register

doep5_int: Reg<DOEP5_INT_SPEC>

0x3cbc8 - Device OUT Endpoint x+1 Interrupt Register

doep5_tsiz: Reg<DOEP5_TSIZ_SPEC>

0x3cbd0 - Device OUT Endpoint x+1 Transfer Size Register

doep5_dmaaddr: Reg<DOEP5_DMAADDR_SPEC>

0x3cbd4 - Device OUT Endpoint x+1 DMA Address Register

pcgcctl: Reg<PCGCCTL_SPEC>

0x3ce00 - Power and Clock Gating Control Register