pub type EDSEL_W<'a> = FieldWriterSafe<'a, u32, CH11_CTRL_SPEC, u8, EDSEL_A, 2, 24>;
Expand description

Field EDSEL writer - Edge Detect Select

Implementations

Signal is left as it is

A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal

A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal

A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal