#[repr(u8)]
pub enum MODE_A {
WS0,
WS1,
WS0SCBTP,
WS1SCBTP,
WS2,
WS2SCBTP,
}
Expand description
Read Mode
Value on reset: 1
Variants
WS0
0: Zero wait-states inserted in fetch or read transfers.
WS1
1: One wait-state inserted for each fetch or read transfer. This mode is required for a core frequency above 16 MHz.
WS0SCBTP
2: Zero wait-states inserted with the Suppressed Conditional Branch Target Prefetch (SCBTP) function enabled. SCBTP saves energy by delaying the Cortex’ conditional branch target prefetches until the conditional branch instruction is in the execute stage. When the instruction reaches this stage, the evaluation of the branch condition is completed and the core does not perform a speculative prefetch of both the branch target address and the next sequential address. With the SCBTP function enabled, one instruction fetch is saved for each branch not taken, with a negligible performance penalty.
WS1SCBTP
3: One wait-state access with SCBTP enabled.
WS2
4: Two wait-states inserted for each fetch or read transfer. This mode is required for a core frequency above 32 MHz.
WS2SCBTP
5: Two wait-state access with SCBTP enabled.
Trait Implementations
impl Copy for MODE_A
impl StructuralPartialEq for MODE_A
Auto Trait Implementations
impl RefUnwindSafe for MODE_A
impl Send for MODE_A
impl Sync for MODE_A
impl Unpin for MODE_A
impl UnwindSafe for MODE_A
Blanket Implementations
sourceimpl<T> BorrowMut<T> for T where
T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized,
const: unstable · sourcefn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more