efm32lg360_pac/prs/
ch8_ctrl.rs

1#[doc = "Register `CH8_CTRL` reader"]
2pub struct R(crate::R<CH8_CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CH8_CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CH8_CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CH8_CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CH8_CTRL` writer"]
17pub struct W(crate::W<CH8_CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CH8_CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CH8_CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CH8_CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SIGSEL` reader - Signal Select"]
38pub type SIGSEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `SIGSEL` writer - Signal Select"]
40pub type SIGSEL_W<'a> = crate::FieldWriter<'a, u32, CH8_CTRL_SPEC, u8, u8, 3, 0>;
41#[doc = "Source Select\n\nValue on reset: 0"]
42#[derive(Clone, Copy, Debug, PartialEq)]
43#[repr(u8)]
44pub enum SOURCESEL_A {
45    #[doc = "0: No source selected"]
46    NONE = 0,
47    #[doc = "1: Voltage Comparator"]
48    VCMP = 1,
49    #[doc = "2: Analog Comparator 0"]
50    ACMP0 = 2,
51    #[doc = "3: Analog Comparator 1"]
52    ACMP1 = 3,
53    #[doc = "6: Digital to Analog Converter 0"]
54    DAC0 = 6,
55    #[doc = "8: Analog to Digital Converter 0"]
56    ADC0 = 8,
57    #[doc = "16: Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
58    USART0 = 16,
59    #[doc = "17: Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
60    USART1 = 17,
61    #[doc = "18: Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
62    USART2 = 18,
63    #[doc = "28: Timer 0"]
64    TIMER0 = 28,
65    #[doc = "29: Timer 1"]
66    TIMER1 = 29,
67    #[doc = "30: Timer 2"]
68    TIMER2 = 30,
69    #[doc = "31: Timer 3"]
70    TIMER3 = 31,
71    #[doc = "36: Universal Serial Bus Interface"]
72    USB = 36,
73    #[doc = "40: Real-Time Counter"]
74    RTC = 40,
75    #[doc = "41: Universal Asynchronous Receiver/Transmitter 0"]
76    UART0 = 41,
77    #[doc = "42: Universal Asynchronous Receiver/Transmitter 1"]
78    UART1 = 42,
79    #[doc = "48: General purpose Input/Output"]
80    GPIOL = 48,
81    #[doc = "49: General purpose Input/Output"]
82    GPIOH = 49,
83    #[doc = "52: Low Energy Timer 0"]
84    LETIMER0 = 52,
85    #[doc = "55: Backup RTC"]
86    BURTC = 55,
87    #[doc = "57: Low Energy Sensor Interface"]
88    LESENSEL = 57,
89    #[doc = "58: Low Energy Sensor Interface"]
90    LESENSEH = 58,
91    #[doc = "59: Low Energy Sensor Interface"]
92    LESENSED = 59,
93}
94impl From<SOURCESEL_A> for u8 {
95    #[inline(always)]
96    fn from(variant: SOURCESEL_A) -> Self {
97        variant as _
98    }
99}
100#[doc = "Field `SOURCESEL` reader - Source Select"]
101pub type SOURCESEL_R = crate::FieldReader<u8, SOURCESEL_A>;
102impl SOURCESEL_R {
103    #[doc = "Get enumerated values variant"]
104    #[inline(always)]
105    pub fn variant(&self) -> Option<SOURCESEL_A> {
106        match self.bits {
107            0 => Some(SOURCESEL_A::NONE),
108            1 => Some(SOURCESEL_A::VCMP),
109            2 => Some(SOURCESEL_A::ACMP0),
110            3 => Some(SOURCESEL_A::ACMP1),
111            6 => Some(SOURCESEL_A::DAC0),
112            8 => Some(SOURCESEL_A::ADC0),
113            16 => Some(SOURCESEL_A::USART0),
114            17 => Some(SOURCESEL_A::USART1),
115            18 => Some(SOURCESEL_A::USART2),
116            28 => Some(SOURCESEL_A::TIMER0),
117            29 => Some(SOURCESEL_A::TIMER1),
118            30 => Some(SOURCESEL_A::TIMER2),
119            31 => Some(SOURCESEL_A::TIMER3),
120            36 => Some(SOURCESEL_A::USB),
121            40 => Some(SOURCESEL_A::RTC),
122            41 => Some(SOURCESEL_A::UART0),
123            42 => Some(SOURCESEL_A::UART1),
124            48 => Some(SOURCESEL_A::GPIOL),
125            49 => Some(SOURCESEL_A::GPIOH),
126            52 => Some(SOURCESEL_A::LETIMER0),
127            55 => Some(SOURCESEL_A::BURTC),
128            57 => Some(SOURCESEL_A::LESENSEL),
129            58 => Some(SOURCESEL_A::LESENSEH),
130            59 => Some(SOURCESEL_A::LESENSED),
131            _ => None,
132        }
133    }
134    #[doc = "Checks if the value of the field is `NONE`"]
135    #[inline(always)]
136    pub fn is_none(&self) -> bool {
137        *self == SOURCESEL_A::NONE
138    }
139    #[doc = "Checks if the value of the field is `VCMP`"]
140    #[inline(always)]
141    pub fn is_vcmp(&self) -> bool {
142        *self == SOURCESEL_A::VCMP
143    }
144    #[doc = "Checks if the value of the field is `ACMP0`"]
145    #[inline(always)]
146    pub fn is_acmp0(&self) -> bool {
147        *self == SOURCESEL_A::ACMP0
148    }
149    #[doc = "Checks if the value of the field is `ACMP1`"]
150    #[inline(always)]
151    pub fn is_acmp1(&self) -> bool {
152        *self == SOURCESEL_A::ACMP1
153    }
154    #[doc = "Checks if the value of the field is `DAC0`"]
155    #[inline(always)]
156    pub fn is_dac0(&self) -> bool {
157        *self == SOURCESEL_A::DAC0
158    }
159    #[doc = "Checks if the value of the field is `ADC0`"]
160    #[inline(always)]
161    pub fn is_adc0(&self) -> bool {
162        *self == SOURCESEL_A::ADC0
163    }
164    #[doc = "Checks if the value of the field is `USART0`"]
165    #[inline(always)]
166    pub fn is_usart0(&self) -> bool {
167        *self == SOURCESEL_A::USART0
168    }
169    #[doc = "Checks if the value of the field is `USART1`"]
170    #[inline(always)]
171    pub fn is_usart1(&self) -> bool {
172        *self == SOURCESEL_A::USART1
173    }
174    #[doc = "Checks if the value of the field is `USART2`"]
175    #[inline(always)]
176    pub fn is_usart2(&self) -> bool {
177        *self == SOURCESEL_A::USART2
178    }
179    #[doc = "Checks if the value of the field is `TIMER0`"]
180    #[inline(always)]
181    pub fn is_timer0(&self) -> bool {
182        *self == SOURCESEL_A::TIMER0
183    }
184    #[doc = "Checks if the value of the field is `TIMER1`"]
185    #[inline(always)]
186    pub fn is_timer1(&self) -> bool {
187        *self == SOURCESEL_A::TIMER1
188    }
189    #[doc = "Checks if the value of the field is `TIMER2`"]
190    #[inline(always)]
191    pub fn is_timer2(&self) -> bool {
192        *self == SOURCESEL_A::TIMER2
193    }
194    #[doc = "Checks if the value of the field is `TIMER3`"]
195    #[inline(always)]
196    pub fn is_timer3(&self) -> bool {
197        *self == SOURCESEL_A::TIMER3
198    }
199    #[doc = "Checks if the value of the field is `USB`"]
200    #[inline(always)]
201    pub fn is_usb(&self) -> bool {
202        *self == SOURCESEL_A::USB
203    }
204    #[doc = "Checks if the value of the field is `RTC`"]
205    #[inline(always)]
206    pub fn is_rtc(&self) -> bool {
207        *self == SOURCESEL_A::RTC
208    }
209    #[doc = "Checks if the value of the field is `UART0`"]
210    #[inline(always)]
211    pub fn is_uart0(&self) -> bool {
212        *self == SOURCESEL_A::UART0
213    }
214    #[doc = "Checks if the value of the field is `UART1`"]
215    #[inline(always)]
216    pub fn is_uart1(&self) -> bool {
217        *self == SOURCESEL_A::UART1
218    }
219    #[doc = "Checks if the value of the field is `GPIOL`"]
220    #[inline(always)]
221    pub fn is_gpiol(&self) -> bool {
222        *self == SOURCESEL_A::GPIOL
223    }
224    #[doc = "Checks if the value of the field is `GPIOH`"]
225    #[inline(always)]
226    pub fn is_gpioh(&self) -> bool {
227        *self == SOURCESEL_A::GPIOH
228    }
229    #[doc = "Checks if the value of the field is `LETIMER0`"]
230    #[inline(always)]
231    pub fn is_letimer0(&self) -> bool {
232        *self == SOURCESEL_A::LETIMER0
233    }
234    #[doc = "Checks if the value of the field is `BURTC`"]
235    #[inline(always)]
236    pub fn is_burtc(&self) -> bool {
237        *self == SOURCESEL_A::BURTC
238    }
239    #[doc = "Checks if the value of the field is `LESENSEL`"]
240    #[inline(always)]
241    pub fn is_lesensel(&self) -> bool {
242        *self == SOURCESEL_A::LESENSEL
243    }
244    #[doc = "Checks if the value of the field is `LESENSEH`"]
245    #[inline(always)]
246    pub fn is_lesenseh(&self) -> bool {
247        *self == SOURCESEL_A::LESENSEH
248    }
249    #[doc = "Checks if the value of the field is `LESENSED`"]
250    #[inline(always)]
251    pub fn is_lesensed(&self) -> bool {
252        *self == SOURCESEL_A::LESENSED
253    }
254}
255#[doc = "Field `SOURCESEL` writer - Source Select"]
256pub type SOURCESEL_W<'a> = crate::FieldWriter<'a, u32, CH8_CTRL_SPEC, u8, SOURCESEL_A, 6, 16>;
257impl<'a> SOURCESEL_W<'a> {
258    #[doc = "No source selected"]
259    #[inline(always)]
260    pub fn none(self) -> &'a mut W {
261        self.variant(SOURCESEL_A::NONE)
262    }
263    #[doc = "Voltage Comparator"]
264    #[inline(always)]
265    pub fn vcmp(self) -> &'a mut W {
266        self.variant(SOURCESEL_A::VCMP)
267    }
268    #[doc = "Analog Comparator 0"]
269    #[inline(always)]
270    pub fn acmp0(self) -> &'a mut W {
271        self.variant(SOURCESEL_A::ACMP0)
272    }
273    #[doc = "Analog Comparator 1"]
274    #[inline(always)]
275    pub fn acmp1(self) -> &'a mut W {
276        self.variant(SOURCESEL_A::ACMP1)
277    }
278    #[doc = "Digital to Analog Converter 0"]
279    #[inline(always)]
280    pub fn dac0(self) -> &'a mut W {
281        self.variant(SOURCESEL_A::DAC0)
282    }
283    #[doc = "Analog to Digital Converter 0"]
284    #[inline(always)]
285    pub fn adc0(self) -> &'a mut W {
286        self.variant(SOURCESEL_A::ADC0)
287    }
288    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
289    #[inline(always)]
290    pub fn usart0(self) -> &'a mut W {
291        self.variant(SOURCESEL_A::USART0)
292    }
293    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
294    #[inline(always)]
295    pub fn usart1(self) -> &'a mut W {
296        self.variant(SOURCESEL_A::USART1)
297    }
298    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
299    #[inline(always)]
300    pub fn usart2(self) -> &'a mut W {
301        self.variant(SOURCESEL_A::USART2)
302    }
303    #[doc = "Timer 0"]
304    #[inline(always)]
305    pub fn timer0(self) -> &'a mut W {
306        self.variant(SOURCESEL_A::TIMER0)
307    }
308    #[doc = "Timer 1"]
309    #[inline(always)]
310    pub fn timer1(self) -> &'a mut W {
311        self.variant(SOURCESEL_A::TIMER1)
312    }
313    #[doc = "Timer 2"]
314    #[inline(always)]
315    pub fn timer2(self) -> &'a mut W {
316        self.variant(SOURCESEL_A::TIMER2)
317    }
318    #[doc = "Timer 3"]
319    #[inline(always)]
320    pub fn timer3(self) -> &'a mut W {
321        self.variant(SOURCESEL_A::TIMER3)
322    }
323    #[doc = "Universal Serial Bus Interface"]
324    #[inline(always)]
325    pub fn usb(self) -> &'a mut W {
326        self.variant(SOURCESEL_A::USB)
327    }
328    #[doc = "Real-Time Counter"]
329    #[inline(always)]
330    pub fn rtc(self) -> &'a mut W {
331        self.variant(SOURCESEL_A::RTC)
332    }
333    #[doc = "Universal Asynchronous Receiver/Transmitter 0"]
334    #[inline(always)]
335    pub fn uart0(self) -> &'a mut W {
336        self.variant(SOURCESEL_A::UART0)
337    }
338    #[doc = "Universal Asynchronous Receiver/Transmitter 1"]
339    #[inline(always)]
340    pub fn uart1(self) -> &'a mut W {
341        self.variant(SOURCESEL_A::UART1)
342    }
343    #[doc = "General purpose Input/Output"]
344    #[inline(always)]
345    pub fn gpiol(self) -> &'a mut W {
346        self.variant(SOURCESEL_A::GPIOL)
347    }
348    #[doc = "General purpose Input/Output"]
349    #[inline(always)]
350    pub fn gpioh(self) -> &'a mut W {
351        self.variant(SOURCESEL_A::GPIOH)
352    }
353    #[doc = "Low Energy Timer 0"]
354    #[inline(always)]
355    pub fn letimer0(self) -> &'a mut W {
356        self.variant(SOURCESEL_A::LETIMER0)
357    }
358    #[doc = "Backup RTC"]
359    #[inline(always)]
360    pub fn burtc(self) -> &'a mut W {
361        self.variant(SOURCESEL_A::BURTC)
362    }
363    #[doc = "Low Energy Sensor Interface"]
364    #[inline(always)]
365    pub fn lesensel(self) -> &'a mut W {
366        self.variant(SOURCESEL_A::LESENSEL)
367    }
368    #[doc = "Low Energy Sensor Interface"]
369    #[inline(always)]
370    pub fn lesenseh(self) -> &'a mut W {
371        self.variant(SOURCESEL_A::LESENSEH)
372    }
373    #[doc = "Low Energy Sensor Interface"]
374    #[inline(always)]
375    pub fn lesensed(self) -> &'a mut W {
376        self.variant(SOURCESEL_A::LESENSED)
377    }
378}
379#[doc = "Edge Detect Select\n\nValue on reset: 0"]
380#[derive(Clone, Copy, Debug, PartialEq)]
381#[repr(u8)]
382pub enum EDSEL_A {
383    #[doc = "0: Signal is left as it is"]
384    OFF = 0,
385    #[doc = "1: A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal"]
386    POSEDGE = 1,
387    #[doc = "2: A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
388    NEGEDGE = 2,
389    #[doc = "3: A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal"]
390    BOTHEDGES = 3,
391}
392impl From<EDSEL_A> for u8 {
393    #[inline(always)]
394    fn from(variant: EDSEL_A) -> Self {
395        variant as _
396    }
397}
398#[doc = "Field `EDSEL` reader - Edge Detect Select"]
399pub type EDSEL_R = crate::FieldReader<u8, EDSEL_A>;
400impl EDSEL_R {
401    #[doc = "Get enumerated values variant"]
402    #[inline(always)]
403    pub fn variant(&self) -> EDSEL_A {
404        match self.bits {
405            0 => EDSEL_A::OFF,
406            1 => EDSEL_A::POSEDGE,
407            2 => EDSEL_A::NEGEDGE,
408            3 => EDSEL_A::BOTHEDGES,
409            _ => unreachable!(),
410        }
411    }
412    #[doc = "Checks if the value of the field is `OFF`"]
413    #[inline(always)]
414    pub fn is_off(&self) -> bool {
415        *self == EDSEL_A::OFF
416    }
417    #[doc = "Checks if the value of the field is `POSEDGE`"]
418    #[inline(always)]
419    pub fn is_posedge(&self) -> bool {
420        *self == EDSEL_A::POSEDGE
421    }
422    #[doc = "Checks if the value of the field is `NEGEDGE`"]
423    #[inline(always)]
424    pub fn is_negedge(&self) -> bool {
425        *self == EDSEL_A::NEGEDGE
426    }
427    #[doc = "Checks if the value of the field is `BOTHEDGES`"]
428    #[inline(always)]
429    pub fn is_bothedges(&self) -> bool {
430        *self == EDSEL_A::BOTHEDGES
431    }
432}
433#[doc = "Field `EDSEL` writer - Edge Detect Select"]
434pub type EDSEL_W<'a> = crate::FieldWriterSafe<'a, u32, CH8_CTRL_SPEC, u8, EDSEL_A, 2, 24>;
435impl<'a> EDSEL_W<'a> {
436    #[doc = "Signal is left as it is"]
437    #[inline(always)]
438    pub fn off(self) -> &'a mut W {
439        self.variant(EDSEL_A::OFF)
440    }
441    #[doc = "A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal"]
442    #[inline(always)]
443    pub fn posedge(self) -> &'a mut W {
444        self.variant(EDSEL_A::POSEDGE)
445    }
446    #[doc = "A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
447    #[inline(always)]
448    pub fn negedge(self) -> &'a mut W {
449        self.variant(EDSEL_A::NEGEDGE)
450    }
451    #[doc = "A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal"]
452    #[inline(always)]
453    pub fn bothedges(self) -> &'a mut W {
454        self.variant(EDSEL_A::BOTHEDGES)
455    }
456}
457#[doc = "Field `ASYNC` reader - Asynchronous reflex"]
458pub type ASYNC_R = crate::BitReader<bool>;
459#[doc = "Field `ASYNC` writer - Asynchronous reflex"]
460pub type ASYNC_W<'a> = crate::BitWriter<'a, u32, CH8_CTRL_SPEC, bool, 28>;
461impl R {
462    #[doc = "Bits 0:2 - Signal Select"]
463    #[inline(always)]
464    pub fn sigsel(&self) -> SIGSEL_R {
465        SIGSEL_R::new((self.bits & 7) as u8)
466    }
467    #[doc = "Bits 16:21 - Source Select"]
468    #[inline(always)]
469    pub fn sourcesel(&self) -> SOURCESEL_R {
470        SOURCESEL_R::new(((self.bits >> 16) & 0x3f) as u8)
471    }
472    #[doc = "Bits 24:25 - Edge Detect Select"]
473    #[inline(always)]
474    pub fn edsel(&self) -> EDSEL_R {
475        EDSEL_R::new(((self.bits >> 24) & 3) as u8)
476    }
477    #[doc = "Bit 28 - Asynchronous reflex"]
478    #[inline(always)]
479    pub fn async_(&self) -> ASYNC_R {
480        ASYNC_R::new(((self.bits >> 28) & 1) != 0)
481    }
482}
483impl W {
484    #[doc = "Bits 0:2 - Signal Select"]
485    #[inline(always)]
486    pub fn sigsel(&mut self) -> SIGSEL_W {
487        SIGSEL_W::new(self)
488    }
489    #[doc = "Bits 16:21 - Source Select"]
490    #[inline(always)]
491    pub fn sourcesel(&mut self) -> SOURCESEL_W {
492        SOURCESEL_W::new(self)
493    }
494    #[doc = "Bits 24:25 - Edge Detect Select"]
495    #[inline(always)]
496    pub fn edsel(&mut self) -> EDSEL_W {
497        EDSEL_W::new(self)
498    }
499    #[doc = "Bit 28 - Asynchronous reflex"]
500    #[inline(always)]
501    pub fn async_(&mut self) -> ASYNC_W {
502        ASYNC_W::new(self)
503    }
504    #[doc = "Writes raw bits to the register."]
505    #[inline(always)]
506    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
507        self.0.bits(bits);
508        self
509    }
510}
511#[doc = "Channel Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch8_ctrl](index.html) module"]
512pub struct CH8_CTRL_SPEC;
513impl crate::RegisterSpec for CH8_CTRL_SPEC {
514    type Ux = u32;
515}
516#[doc = "`read()` method returns [ch8_ctrl::R](R) reader structure"]
517impl crate::Readable for CH8_CTRL_SPEC {
518    type Reader = R;
519}
520#[doc = "`write(|w| ..)` method takes [ch8_ctrl::W](W) writer structure"]
521impl crate::Writable for CH8_CTRL_SPEC {
522    type Writer = W;
523}
524#[doc = "`reset()` method sets CH8_CTRL to value 0"]
525impl crate::Resettable for CH8_CTRL_SPEC {
526    #[inline(always)]
527    fn reset_value() -> Self::Ux {
528        0
529    }
530}
efm32lg360_pac/prs/ch8_ctrl.rs

efm32lg360_pac/prs/
ch8_ctrl.rs
