efm32jg1b100_pac/prs/
ch7_ctrl.rs

1#[doc = "Register `CH7_CTRL` reader"]
2pub struct R(crate::R<CH7_CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CH7_CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CH7_CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CH7_CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CH7_CTRL` writer"]
17pub struct W(crate::W<CH7_CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CH7_CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CH7_CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CH7_CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SIGSEL` reader - Signal Select"]
38pub type SIGSEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `SIGSEL` writer - Signal Select"]
40pub type SIGSEL_W<'a> = crate::FieldWriter<'a, u32, CH7_CTRL_SPEC, u8, u8, 3, 0>;
41#[doc = "Source Select\n\nValue on reset: 0"]
42#[derive(Clone, Copy, Debug, PartialEq)]
43#[repr(u8)]
44pub enum SOURCESEL_A {
45    #[doc = "0: No source selected"]
46    NONE = 0,
47    #[doc = "1: Peripheral Reflex System"]
48    PRSL = 1,
49    #[doc = "2: Peripheral Reflex System"]
50    PRSH = 2,
51    #[doc = "6: Analog Comparator 0"]
52    ACMP0 = 6,
53    #[doc = "7: Analog Comparator 1"]
54    ACMP1 = 7,
55    #[doc = "8: Analog to Digital Converter 0"]
56    ADC0 = 8,
57    #[doc = "16: Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
58    USART0 = 16,
59    #[doc = "17: Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
60    USART1 = 17,
61    #[doc = "28: Timer 0"]
62    TIMER0 = 28,
63    #[doc = "29: Timer 1"]
64    TIMER1 = 29,
65    #[doc = "41: Real-Time Counter and Calendar"]
66    RTCC = 41,
67    #[doc = "48: General purpose Input/Output"]
68    GPIOL = 48,
69    #[doc = "49: General purpose Input/Output"]
70    GPIOH = 49,
71    #[doc = "52: Low Energy Timer 0"]
72    LETIMER0 = 52,
73    #[doc = "54: Pulse Counter 0"]
74    PCNT0 = 54,
75    #[doc = "60: CRYOTIMER"]
76    CRYOTIMER = 60,
77    #[doc = "61: Clock Management Unit"]
78    CMU = 61,
79    #[doc = "67: `1000011`"]
80    CM4 = 67,
81}
82impl From<SOURCESEL_A> for u8 {
83    #[inline(always)]
84    fn from(variant: SOURCESEL_A) -> Self {
85        variant as _
86    }
87}
88#[doc = "Field `SOURCESEL` reader - Source Select"]
89pub type SOURCESEL_R = crate::FieldReader<u8, SOURCESEL_A>;
90impl SOURCESEL_R {
91    #[doc = "Get enumerated values variant"]
92    #[inline(always)]
93    pub fn variant(&self) -> Option<SOURCESEL_A> {
94        match self.bits {
95            0 => Some(SOURCESEL_A::NONE),
96            1 => Some(SOURCESEL_A::PRSL),
97            2 => Some(SOURCESEL_A::PRSH),
98            6 => Some(SOURCESEL_A::ACMP0),
99            7 => Some(SOURCESEL_A::ACMP1),
100            8 => Some(SOURCESEL_A::ADC0),
101            16 => Some(SOURCESEL_A::USART0),
102            17 => Some(SOURCESEL_A::USART1),
103            28 => Some(SOURCESEL_A::TIMER0),
104            29 => Some(SOURCESEL_A::TIMER1),
105            41 => Some(SOURCESEL_A::RTCC),
106            48 => Some(SOURCESEL_A::GPIOL),
107            49 => Some(SOURCESEL_A::GPIOH),
108            52 => Some(SOURCESEL_A::LETIMER0),
109            54 => Some(SOURCESEL_A::PCNT0),
110            60 => Some(SOURCESEL_A::CRYOTIMER),
111            61 => Some(SOURCESEL_A::CMU),
112            67 => Some(SOURCESEL_A::CM4),
113            _ => None,
114        }
115    }
116    #[doc = "Checks if the value of the field is `NONE`"]
117    #[inline(always)]
118    pub fn is_none(&self) -> bool {
119        *self == SOURCESEL_A::NONE
120    }
121    #[doc = "Checks if the value of the field is `PRSL`"]
122    #[inline(always)]
123    pub fn is_prsl(&self) -> bool {
124        *self == SOURCESEL_A::PRSL
125    }
126    #[doc = "Checks if the value of the field is `PRSH`"]
127    #[inline(always)]
128    pub fn is_prsh(&self) -> bool {
129        *self == SOURCESEL_A::PRSH
130    }
131    #[doc = "Checks if the value of the field is `ACMP0`"]
132    #[inline(always)]
133    pub fn is_acmp0(&self) -> bool {
134        *self == SOURCESEL_A::ACMP0
135    }
136    #[doc = "Checks if the value of the field is `ACMP1`"]
137    #[inline(always)]
138    pub fn is_acmp1(&self) -> bool {
139        *self == SOURCESEL_A::ACMP1
140    }
141    #[doc = "Checks if the value of the field is `ADC0`"]
142    #[inline(always)]
143    pub fn is_adc0(&self) -> bool {
144        *self == SOURCESEL_A::ADC0
145    }
146    #[doc = "Checks if the value of the field is `USART0`"]
147    #[inline(always)]
148    pub fn is_usart0(&self) -> bool {
149        *self == SOURCESEL_A::USART0
150    }
151    #[doc = "Checks if the value of the field is `USART1`"]
152    #[inline(always)]
153    pub fn is_usart1(&self) -> bool {
154        *self == SOURCESEL_A::USART1
155    }
156    #[doc = "Checks if the value of the field is `TIMER0`"]
157    #[inline(always)]
158    pub fn is_timer0(&self) -> bool {
159        *self == SOURCESEL_A::TIMER0
160    }
161    #[doc = "Checks if the value of the field is `TIMER1`"]
162    #[inline(always)]
163    pub fn is_timer1(&self) -> bool {
164        *self == SOURCESEL_A::TIMER1
165    }
166    #[doc = "Checks if the value of the field is `RTCC`"]
167    #[inline(always)]
168    pub fn is_rtcc(&self) -> bool {
169        *self == SOURCESEL_A::RTCC
170    }
171    #[doc = "Checks if the value of the field is `GPIOL`"]
172    #[inline(always)]
173    pub fn is_gpiol(&self) -> bool {
174        *self == SOURCESEL_A::GPIOL
175    }
176    #[doc = "Checks if the value of the field is `GPIOH`"]
177    #[inline(always)]
178    pub fn is_gpioh(&self) -> bool {
179        *self == SOURCESEL_A::GPIOH
180    }
181    #[doc = "Checks if the value of the field is `LETIMER0`"]
182    #[inline(always)]
183    pub fn is_letimer0(&self) -> bool {
184        *self == SOURCESEL_A::LETIMER0
185    }
186    #[doc = "Checks if the value of the field is `PCNT0`"]
187    #[inline(always)]
188    pub fn is_pcnt0(&self) -> bool {
189        *self == SOURCESEL_A::PCNT0
190    }
191    #[doc = "Checks if the value of the field is `CRYOTIMER`"]
192    #[inline(always)]
193    pub fn is_cryotimer(&self) -> bool {
194        *self == SOURCESEL_A::CRYOTIMER
195    }
196    #[doc = "Checks if the value of the field is `CMU`"]
197    #[inline(always)]
198    pub fn is_cmu(&self) -> bool {
199        *self == SOURCESEL_A::CMU
200    }
201    #[doc = "Checks if the value of the field is `CM4`"]
202    #[inline(always)]
203    pub fn is_cm4(&self) -> bool {
204        *self == SOURCESEL_A::CM4
205    }
206}
207#[doc = "Field `SOURCESEL` writer - Source Select"]
208pub type SOURCESEL_W<'a> = crate::FieldWriter<'a, u32, CH7_CTRL_SPEC, u8, SOURCESEL_A, 7, 8>;
209impl<'a> SOURCESEL_W<'a> {
210    #[doc = "No source selected"]
211    #[inline(always)]
212    pub fn none(self) -> &'a mut W {
213        self.variant(SOURCESEL_A::NONE)
214    }
215    #[doc = "Peripheral Reflex System"]
216    #[inline(always)]
217    pub fn prsl(self) -> &'a mut W {
218        self.variant(SOURCESEL_A::PRSL)
219    }
220    #[doc = "Peripheral Reflex System"]
221    #[inline(always)]
222    pub fn prsh(self) -> &'a mut W {
223        self.variant(SOURCESEL_A::PRSH)
224    }
225    #[doc = "Analog Comparator 0"]
226    #[inline(always)]
227    pub fn acmp0(self) -> &'a mut W {
228        self.variant(SOURCESEL_A::ACMP0)
229    }
230    #[doc = "Analog Comparator 1"]
231    #[inline(always)]
232    pub fn acmp1(self) -> &'a mut W {
233        self.variant(SOURCESEL_A::ACMP1)
234    }
235    #[doc = "Analog to Digital Converter 0"]
236    #[inline(always)]
237    pub fn adc0(self) -> &'a mut W {
238        self.variant(SOURCESEL_A::ADC0)
239    }
240    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
241    #[inline(always)]
242    pub fn usart0(self) -> &'a mut W {
243        self.variant(SOURCESEL_A::USART0)
244    }
245    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
246    #[inline(always)]
247    pub fn usart1(self) -> &'a mut W {
248        self.variant(SOURCESEL_A::USART1)
249    }
250    #[doc = "Timer 0"]
251    #[inline(always)]
252    pub fn timer0(self) -> &'a mut W {
253        self.variant(SOURCESEL_A::TIMER0)
254    }
255    #[doc = "Timer 1"]
256    #[inline(always)]
257    pub fn timer1(self) -> &'a mut W {
258        self.variant(SOURCESEL_A::TIMER1)
259    }
260    #[doc = "Real-Time Counter and Calendar"]
261    #[inline(always)]
262    pub fn rtcc(self) -> &'a mut W {
263        self.variant(SOURCESEL_A::RTCC)
264    }
265    #[doc = "General purpose Input/Output"]
266    #[inline(always)]
267    pub fn gpiol(self) -> &'a mut W {
268        self.variant(SOURCESEL_A::GPIOL)
269    }
270    #[doc = "General purpose Input/Output"]
271    #[inline(always)]
272    pub fn gpioh(self) -> &'a mut W {
273        self.variant(SOURCESEL_A::GPIOH)
274    }
275    #[doc = "Low Energy Timer 0"]
276    #[inline(always)]
277    pub fn letimer0(self) -> &'a mut W {
278        self.variant(SOURCESEL_A::LETIMER0)
279    }
280    #[doc = "Pulse Counter 0"]
281    #[inline(always)]
282    pub fn pcnt0(self) -> &'a mut W {
283        self.variant(SOURCESEL_A::PCNT0)
284    }
285    #[doc = "CRYOTIMER"]
286    #[inline(always)]
287    pub fn cryotimer(self) -> &'a mut W {
288        self.variant(SOURCESEL_A::CRYOTIMER)
289    }
290    #[doc = "Clock Management Unit"]
291    #[inline(always)]
292    pub fn cmu(self) -> &'a mut W {
293        self.variant(SOURCESEL_A::CMU)
294    }
295    #[doc = "`1000011`"]
296    #[inline(always)]
297    pub fn cm4(self) -> &'a mut W {
298        self.variant(SOURCESEL_A::CM4)
299    }
300}
301#[doc = "Edge Detect Select\n\nValue on reset: 0"]
302#[derive(Clone, Copy, Debug, PartialEq)]
303#[repr(u8)]
304pub enum EDSEL_A {
305    #[doc = "0: Signal is left as it is"]
306    OFF = 0,
307    #[doc = "1: A one HFCLK cycle pulse is generated for every positive edge of the incoming signal"]
308    POSEDGE = 1,
309    #[doc = "2: A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
310    NEGEDGE = 2,
311    #[doc = "3: A one HFCLK clock cycle pulse is generated for every edge of the incoming signal"]
312    BOTHEDGES = 3,
313}
314impl From<EDSEL_A> for u8 {
315    #[inline(always)]
316    fn from(variant: EDSEL_A) -> Self {
317        variant as _
318    }
319}
320#[doc = "Field `EDSEL` reader - Edge Detect Select"]
321pub type EDSEL_R = crate::FieldReader<u8, EDSEL_A>;
322impl EDSEL_R {
323    #[doc = "Get enumerated values variant"]
324    #[inline(always)]
325    pub fn variant(&self) -> EDSEL_A {
326        match self.bits {
327            0 => EDSEL_A::OFF,
328            1 => EDSEL_A::POSEDGE,
329            2 => EDSEL_A::NEGEDGE,
330            3 => EDSEL_A::BOTHEDGES,
331            _ => unreachable!(),
332        }
333    }
334    #[doc = "Checks if the value of the field is `OFF`"]
335    #[inline(always)]
336    pub fn is_off(&self) -> bool {
337        *self == EDSEL_A::OFF
338    }
339    #[doc = "Checks if the value of the field is `POSEDGE`"]
340    #[inline(always)]
341    pub fn is_posedge(&self) -> bool {
342        *self == EDSEL_A::POSEDGE
343    }
344    #[doc = "Checks if the value of the field is `NEGEDGE`"]
345    #[inline(always)]
346    pub fn is_negedge(&self) -> bool {
347        *self == EDSEL_A::NEGEDGE
348    }
349    #[doc = "Checks if the value of the field is `BOTHEDGES`"]
350    #[inline(always)]
351    pub fn is_bothedges(&self) -> bool {
352        *self == EDSEL_A::BOTHEDGES
353    }
354}
355#[doc = "Field `EDSEL` writer - Edge Detect Select"]
356pub type EDSEL_W<'a> = crate::FieldWriterSafe<'a, u32, CH7_CTRL_SPEC, u8, EDSEL_A, 2, 20>;
357impl<'a> EDSEL_W<'a> {
358    #[doc = "Signal is left as it is"]
359    #[inline(always)]
360    pub fn off(self) -> &'a mut W {
361        self.variant(EDSEL_A::OFF)
362    }
363    #[doc = "A one HFCLK cycle pulse is generated for every positive edge of the incoming signal"]
364    #[inline(always)]
365    pub fn posedge(self) -> &'a mut W {
366        self.variant(EDSEL_A::POSEDGE)
367    }
368    #[doc = "A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
369    #[inline(always)]
370    pub fn negedge(self) -> &'a mut W {
371        self.variant(EDSEL_A::NEGEDGE)
372    }
373    #[doc = "A one HFCLK clock cycle pulse is generated for every edge of the incoming signal"]
374    #[inline(always)]
375    pub fn bothedges(self) -> &'a mut W {
376        self.variant(EDSEL_A::BOTHEDGES)
377    }
378}
379#[doc = "Field `STRETCH` reader - Stretch Channel Output"]
380pub type STRETCH_R = crate::BitReader<bool>;
381#[doc = "Field `STRETCH` writer - Stretch Channel Output"]
382pub type STRETCH_W<'a> = crate::BitWriter<'a, u32, CH7_CTRL_SPEC, bool, 25>;
383#[doc = "Field `INV` reader - Invert Channel"]
384pub type INV_R = crate::BitReader<bool>;
385#[doc = "Field `INV` writer - Invert Channel"]
386pub type INV_W<'a> = crate::BitWriter<'a, u32, CH7_CTRL_SPEC, bool, 26>;
387#[doc = "Field `ORPREV` reader - Or Previous"]
388pub type ORPREV_R = crate::BitReader<bool>;
389#[doc = "Field `ORPREV` writer - Or Previous"]
390pub type ORPREV_W<'a> = crate::BitWriter<'a, u32, CH7_CTRL_SPEC, bool, 27>;
391#[doc = "Field `ANDNEXT` reader - And Next"]
392pub type ANDNEXT_R = crate::BitReader<bool>;
393#[doc = "Field `ANDNEXT` writer - And Next"]
394pub type ANDNEXT_W<'a> = crate::BitWriter<'a, u32, CH7_CTRL_SPEC, bool, 28>;
395#[doc = "Field `ASYNC` reader - Asynchronous Reflex"]
396pub type ASYNC_R = crate::BitReader<bool>;
397#[doc = "Field `ASYNC` writer - Asynchronous Reflex"]
398pub type ASYNC_W<'a> = crate::BitWriter<'a, u32, CH7_CTRL_SPEC, bool, 30>;
399impl R {
400    #[doc = "Bits 0:2 - Signal Select"]
401    #[inline(always)]
402    pub fn sigsel(&self) -> SIGSEL_R {
403        SIGSEL_R::new((self.bits & 7) as u8)
404    }
405    #[doc = "Bits 8:14 - Source Select"]
406    #[inline(always)]
407    pub fn sourcesel(&self) -> SOURCESEL_R {
408        SOURCESEL_R::new(((self.bits >> 8) & 0x7f) as u8)
409    }
410    #[doc = "Bits 20:21 - Edge Detect Select"]
411    #[inline(always)]
412    pub fn edsel(&self) -> EDSEL_R {
413        EDSEL_R::new(((self.bits >> 20) & 3) as u8)
414    }
415    #[doc = "Bit 25 - Stretch Channel Output"]
416    #[inline(always)]
417    pub fn stretch(&self) -> STRETCH_R {
418        STRETCH_R::new(((self.bits >> 25) & 1) != 0)
419    }
420    #[doc = "Bit 26 - Invert Channel"]
421    #[inline(always)]
422    pub fn inv(&self) -> INV_R {
423        INV_R::new(((self.bits >> 26) & 1) != 0)
424    }
425    #[doc = "Bit 27 - Or Previous"]
426    #[inline(always)]
427    pub fn orprev(&self) -> ORPREV_R {
428        ORPREV_R::new(((self.bits >> 27) & 1) != 0)
429    }
430    #[doc = "Bit 28 - And Next"]
431    #[inline(always)]
432    pub fn andnext(&self) -> ANDNEXT_R {
433        ANDNEXT_R::new(((self.bits >> 28) & 1) != 0)
434    }
435    #[doc = "Bit 30 - Asynchronous Reflex"]
436    #[inline(always)]
437    pub fn async_(&self) -> ASYNC_R {
438        ASYNC_R::new(((self.bits >> 30) & 1) != 0)
439    }
440}
441impl W {
442    #[doc = "Bits 0:2 - Signal Select"]
443    #[inline(always)]
444    pub fn sigsel(&mut self) -> SIGSEL_W {
445        SIGSEL_W::new(self)
446    }
447    #[doc = "Bits 8:14 - Source Select"]
448    #[inline(always)]
449    pub fn sourcesel(&mut self) -> SOURCESEL_W {
450        SOURCESEL_W::new(self)
451    }
452    #[doc = "Bits 20:21 - Edge Detect Select"]
453    #[inline(always)]
454    pub fn edsel(&mut self) -> EDSEL_W {
455        EDSEL_W::new(self)
456    }
457    #[doc = "Bit 25 - Stretch Channel Output"]
458    #[inline(always)]
459    pub fn stretch(&mut self) -> STRETCH_W {
460        STRETCH_W::new(self)
461    }
462    #[doc = "Bit 26 - Invert Channel"]
463    #[inline(always)]
464    pub fn inv(&mut self) -> INV_W {
465        INV_W::new(self)
466    }
467    #[doc = "Bit 27 - Or Previous"]
468    #[inline(always)]
469    pub fn orprev(&mut self) -> ORPREV_W {
470        ORPREV_W::new(self)
471    }
472    #[doc = "Bit 28 - And Next"]
473    #[inline(always)]
474    pub fn andnext(&mut self) -> ANDNEXT_W {
475        ANDNEXT_W::new(self)
476    }
477    #[doc = "Bit 30 - Asynchronous Reflex"]
478    #[inline(always)]
479    pub fn async_(&mut self) -> ASYNC_W {
480        ASYNC_W::new(self)
481    }
482    #[doc = "Writes raw bits to the register."]
483    #[inline(always)]
484    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
485        self.0.bits(bits);
486        self
487    }
488}
489#[doc = "Channel Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch7_ctrl](index.html) module"]
490pub struct CH7_CTRL_SPEC;
491impl crate::RegisterSpec for CH7_CTRL_SPEC {
492    type Ux = u32;
493}
494#[doc = "`read()` method returns [ch7_ctrl::R](R) reader structure"]
495impl crate::Readable for CH7_CTRL_SPEC {
496    type Reader = R;
497}
498#[doc = "`write(|w| ..)` method takes [ch7_ctrl::W](W) writer structure"]
499impl crate::Writable for CH7_CTRL_SPEC {
500    type Writer = W;
501}
502#[doc = "`reset()` method sets CH7_CTRL to value 0"]
503impl crate::Resettable for CH7_CTRL_SPEC {
504    #[inline(always)]
505    fn reset_value() -> Self::Ux {
506        0
507    }
508}
efm32jg1b100_pac/prs/ch7_ctrl.rs

efm32jg1b100_pac/prs/
ch7_ctrl.rs
