efm32jg1b_pac/efm32jg1b100/prs/
ch0_ctrl.rs

1#[doc = "Register `CH0_CTRL` reader"]
2pub struct R(crate::R<CH0_CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CH0_CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CH0_CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CH0_CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CH0_CTRL` writer"]
17pub struct W(crate::W<CH0_CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CH0_CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CH0_CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CH0_CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SIGSEL` reader - Signal Select"]
38pub type SIGSEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `SIGSEL` writer - Signal Select"]
40pub type SIGSEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CH0_CTRL_SPEC, u8, u8, 3, O>;
41#[doc = "Field `SOURCESEL` reader - Source Select"]
42pub type SOURCESEL_R = crate::FieldReader<u8, SOURCESEL_A>;
43#[doc = "Source Select\n\nValue on reset: 0"]
44#[derive(Clone, Copy, Debug, PartialEq, Eq)]
45#[repr(u8)]
46pub enum SOURCESEL_A {
47    #[doc = "0: No source selected"]
48    NONE = 0,
49    #[doc = "1: Peripheral Reflex System"]
50    PRSL = 1,
51    #[doc = "2: Peripheral Reflex System"]
52    PRSH = 2,
53    #[doc = "6: Analog Comparator 0"]
54    ACMP0 = 6,
55    #[doc = "7: Analog Comparator 1"]
56    ACMP1 = 7,
57    #[doc = "8: Analog to Digital Converter 0"]
58    ADC0 = 8,
59    #[doc = "16: Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
60    USART0 = 16,
61    #[doc = "17: Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
62    USART1 = 17,
63    #[doc = "28: Timer 0"]
64    TIMER0 = 28,
65    #[doc = "29: Timer 1"]
66    TIMER1 = 29,
67    #[doc = "41: Real-Time Counter and Calendar"]
68    RTCC = 41,
69    #[doc = "48: General purpose Input/Output"]
70    GPIOL = 48,
71    #[doc = "49: General purpose Input/Output"]
72    GPIOH = 49,
73    #[doc = "52: Low Energy Timer 0"]
74    LETIMER0 = 52,
75    #[doc = "54: Pulse Counter 0"]
76    PCNT0 = 54,
77    #[doc = "60: CRYOTIMER"]
78    CRYOTIMER = 60,
79    #[doc = "61: Clock Management Unit"]
80    CMU = 61,
81    #[doc = "67: `1000011`"]
82    CM4 = 67,
83}
84impl From<SOURCESEL_A> for u8 {
85    #[inline(always)]
86    fn from(variant: SOURCESEL_A) -> Self {
87        variant as _
88    }
89}
90impl SOURCESEL_R {
91    #[doc = "Get enumerated values variant"]
92    #[inline(always)]
93    pub fn variant(&self) -> Option<SOURCESEL_A> {
94        match self.bits {
95            0 => Some(SOURCESEL_A::NONE),
96            1 => Some(SOURCESEL_A::PRSL),
97            2 => Some(SOURCESEL_A::PRSH),
98            6 => Some(SOURCESEL_A::ACMP0),
99            7 => Some(SOURCESEL_A::ACMP1),
100            8 => Some(SOURCESEL_A::ADC0),
101            16 => Some(SOURCESEL_A::USART0),
102            17 => Some(SOURCESEL_A::USART1),
103            28 => Some(SOURCESEL_A::TIMER0),
104            29 => Some(SOURCESEL_A::TIMER1),
105            41 => Some(SOURCESEL_A::RTCC),
106            48 => Some(SOURCESEL_A::GPIOL),
107            49 => Some(SOURCESEL_A::GPIOH),
108            52 => Some(SOURCESEL_A::LETIMER0),
109            54 => Some(SOURCESEL_A::PCNT0),
110            60 => Some(SOURCESEL_A::CRYOTIMER),
111            61 => Some(SOURCESEL_A::CMU),
112            67 => Some(SOURCESEL_A::CM4),
113            _ => None,
114        }
115    }
116    #[doc = "Checks if the value of the field is `NONE`"]
117    #[inline(always)]
118    pub fn is_none(&self) -> bool {
119        *self == SOURCESEL_A::NONE
120    }
121    #[doc = "Checks if the value of the field is `PRSL`"]
122    #[inline(always)]
123    pub fn is_prsl(&self) -> bool {
124        *self == SOURCESEL_A::PRSL
125    }
126    #[doc = "Checks if the value of the field is `PRSH`"]
127    #[inline(always)]
128    pub fn is_prsh(&self) -> bool {
129        *self == SOURCESEL_A::PRSH
130    }
131    #[doc = "Checks if the value of the field is `ACMP0`"]
132    #[inline(always)]
133    pub fn is_acmp0(&self) -> bool {
134        *self == SOURCESEL_A::ACMP0
135    }
136    #[doc = "Checks if the value of the field is `ACMP1`"]
137    #[inline(always)]
138    pub fn is_acmp1(&self) -> bool {
139        *self == SOURCESEL_A::ACMP1
140    }
141    #[doc = "Checks if the value of the field is `ADC0`"]
142    #[inline(always)]
143    pub fn is_adc0(&self) -> bool {
144        *self == SOURCESEL_A::ADC0
145    }
146    #[doc = "Checks if the value of the field is `USART0`"]
147    #[inline(always)]
148    pub fn is_usart0(&self) -> bool {
149        *self == SOURCESEL_A::USART0
150    }
151    #[doc = "Checks if the value of the field is `USART1`"]
152    #[inline(always)]
153    pub fn is_usart1(&self) -> bool {
154        *self == SOURCESEL_A::USART1
155    }
156    #[doc = "Checks if the value of the field is `TIMER0`"]
157    #[inline(always)]
158    pub fn is_timer0(&self) -> bool {
159        *self == SOURCESEL_A::TIMER0
160    }
161    #[doc = "Checks if the value of the field is `TIMER1`"]
162    #[inline(always)]
163    pub fn is_timer1(&self) -> bool {
164        *self == SOURCESEL_A::TIMER1
165    }
166    #[doc = "Checks if the value of the field is `RTCC`"]
167    #[inline(always)]
168    pub fn is_rtcc(&self) -> bool {
169        *self == SOURCESEL_A::RTCC
170    }
171    #[doc = "Checks if the value of the field is `GPIOL`"]
172    #[inline(always)]
173    pub fn is_gpiol(&self) -> bool {
174        *self == SOURCESEL_A::GPIOL
175    }
176    #[doc = "Checks if the value of the field is `GPIOH`"]
177    #[inline(always)]
178    pub fn is_gpioh(&self) -> bool {
179        *self == SOURCESEL_A::GPIOH
180    }
181    #[doc = "Checks if the value of the field is `LETIMER0`"]
182    #[inline(always)]
183    pub fn is_letimer0(&self) -> bool {
184        *self == SOURCESEL_A::LETIMER0
185    }
186    #[doc = "Checks if the value of the field is `PCNT0`"]
187    #[inline(always)]
188    pub fn is_pcnt0(&self) -> bool {
189        *self == SOURCESEL_A::PCNT0
190    }
191    #[doc = "Checks if the value of the field is `CRYOTIMER`"]
192    #[inline(always)]
193    pub fn is_cryotimer(&self) -> bool {
194        *self == SOURCESEL_A::CRYOTIMER
195    }
196    #[doc = "Checks if the value of the field is `CMU`"]
197    #[inline(always)]
198    pub fn is_cmu(&self) -> bool {
199        *self == SOURCESEL_A::CMU
200    }
201    #[doc = "Checks if the value of the field is `CM4`"]
202    #[inline(always)]
203    pub fn is_cm4(&self) -> bool {
204        *self == SOURCESEL_A::CM4
205    }
206}
207#[doc = "Field `SOURCESEL` writer - Source Select"]
208pub type SOURCESEL_W<'a, const O: u8> =
209    crate::FieldWriter<'a, u32, CH0_CTRL_SPEC, u8, SOURCESEL_A, 7, O>;
210impl<'a, const O: u8> SOURCESEL_W<'a, O> {
211    #[doc = "No source selected"]
212    #[inline(always)]
213    pub fn none(self) -> &'a mut W {
214        self.variant(SOURCESEL_A::NONE)
215    }
216    #[doc = "Peripheral Reflex System"]
217    #[inline(always)]
218    pub fn prsl(self) -> &'a mut W {
219        self.variant(SOURCESEL_A::PRSL)
220    }
221    #[doc = "Peripheral Reflex System"]
222    #[inline(always)]
223    pub fn prsh(self) -> &'a mut W {
224        self.variant(SOURCESEL_A::PRSH)
225    }
226    #[doc = "Analog Comparator 0"]
227    #[inline(always)]
228    pub fn acmp0(self) -> &'a mut W {
229        self.variant(SOURCESEL_A::ACMP0)
230    }
231    #[doc = "Analog Comparator 1"]
232    #[inline(always)]
233    pub fn acmp1(self) -> &'a mut W {
234        self.variant(SOURCESEL_A::ACMP1)
235    }
236    #[doc = "Analog to Digital Converter 0"]
237    #[inline(always)]
238    pub fn adc0(self) -> &'a mut W {
239        self.variant(SOURCESEL_A::ADC0)
240    }
241    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
242    #[inline(always)]
243    pub fn usart0(self) -> &'a mut W {
244        self.variant(SOURCESEL_A::USART0)
245    }
246    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
247    #[inline(always)]
248    pub fn usart1(self) -> &'a mut W {
249        self.variant(SOURCESEL_A::USART1)
250    }
251    #[doc = "Timer 0"]
252    #[inline(always)]
253    pub fn timer0(self) -> &'a mut W {
254        self.variant(SOURCESEL_A::TIMER0)
255    }
256    #[doc = "Timer 1"]
257    #[inline(always)]
258    pub fn timer1(self) -> &'a mut W {
259        self.variant(SOURCESEL_A::TIMER1)
260    }
261    #[doc = "Real-Time Counter and Calendar"]
262    #[inline(always)]
263    pub fn rtcc(self) -> &'a mut W {
264        self.variant(SOURCESEL_A::RTCC)
265    }
266    #[doc = "General purpose Input/Output"]
267    #[inline(always)]
268    pub fn gpiol(self) -> &'a mut W {
269        self.variant(SOURCESEL_A::GPIOL)
270    }
271    #[doc = "General purpose Input/Output"]
272    #[inline(always)]
273    pub fn gpioh(self) -> &'a mut W {
274        self.variant(SOURCESEL_A::GPIOH)
275    }
276    #[doc = "Low Energy Timer 0"]
277    #[inline(always)]
278    pub fn letimer0(self) -> &'a mut W {
279        self.variant(SOURCESEL_A::LETIMER0)
280    }
281    #[doc = "Pulse Counter 0"]
282    #[inline(always)]
283    pub fn pcnt0(self) -> &'a mut W {
284        self.variant(SOURCESEL_A::PCNT0)
285    }
286    #[doc = "CRYOTIMER"]
287    #[inline(always)]
288    pub fn cryotimer(self) -> &'a mut W {
289        self.variant(SOURCESEL_A::CRYOTIMER)
290    }
291    #[doc = "Clock Management Unit"]
292    #[inline(always)]
293    pub fn cmu(self) -> &'a mut W {
294        self.variant(SOURCESEL_A::CMU)
295    }
296    #[doc = "`1000011`"]
297    #[inline(always)]
298    pub fn cm4(self) -> &'a mut W {
299        self.variant(SOURCESEL_A::CM4)
300    }
301}
302#[doc = "Field `EDSEL` reader - Edge Detect Select"]
303pub type EDSEL_R = crate::FieldReader<u8, EDSEL_A>;
304#[doc = "Edge Detect Select\n\nValue on reset: 0"]
305#[derive(Clone, Copy, Debug, PartialEq, Eq)]
306#[repr(u8)]
307pub enum EDSEL_A {
308    #[doc = "0: Signal is left as it is"]
309    OFF = 0,
310    #[doc = "1: A one HFCLK cycle pulse is generated for every positive edge of the incoming signal"]
311    POSEDGE = 1,
312    #[doc = "2: A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
313    NEGEDGE = 2,
314    #[doc = "3: A one HFCLK clock cycle pulse is generated for every edge of the incoming signal"]
315    BOTHEDGES = 3,
316}
317impl From<EDSEL_A> for u8 {
318    #[inline(always)]
319    fn from(variant: EDSEL_A) -> Self {
320        variant as _
321    }
322}
323impl EDSEL_R {
324    #[doc = "Get enumerated values variant"]
325    #[inline(always)]
326    pub fn variant(&self) -> EDSEL_A {
327        match self.bits {
328            0 => EDSEL_A::OFF,
329            1 => EDSEL_A::POSEDGE,
330            2 => EDSEL_A::NEGEDGE,
331            3 => EDSEL_A::BOTHEDGES,
332            _ => unreachable!(),
333        }
334    }
335    #[doc = "Checks if the value of the field is `OFF`"]
336    #[inline(always)]
337    pub fn is_off(&self) -> bool {
338        *self == EDSEL_A::OFF
339    }
340    #[doc = "Checks if the value of the field is `POSEDGE`"]
341    #[inline(always)]
342    pub fn is_posedge(&self) -> bool {
343        *self == EDSEL_A::POSEDGE
344    }
345    #[doc = "Checks if the value of the field is `NEGEDGE`"]
346    #[inline(always)]
347    pub fn is_negedge(&self) -> bool {
348        *self == EDSEL_A::NEGEDGE
349    }
350    #[doc = "Checks if the value of the field is `BOTHEDGES`"]
351    #[inline(always)]
352    pub fn is_bothedges(&self) -> bool {
353        *self == EDSEL_A::BOTHEDGES
354    }
355}
356#[doc = "Field `EDSEL` writer - Edge Detect Select"]
357pub type EDSEL_W<'a, const O: u8> =
358    crate::FieldWriterSafe<'a, u32, CH0_CTRL_SPEC, u8, EDSEL_A, 2, O>;
359impl<'a, const O: u8> EDSEL_W<'a, O> {
360    #[doc = "Signal is left as it is"]
361    #[inline(always)]
362    pub fn off(self) -> &'a mut W {
363        self.variant(EDSEL_A::OFF)
364    }
365    #[doc = "A one HFCLK cycle pulse is generated for every positive edge of the incoming signal"]
366    #[inline(always)]
367    pub fn posedge(self) -> &'a mut W {
368        self.variant(EDSEL_A::POSEDGE)
369    }
370    #[doc = "A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
371    #[inline(always)]
372    pub fn negedge(self) -> &'a mut W {
373        self.variant(EDSEL_A::NEGEDGE)
374    }
375    #[doc = "A one HFCLK clock cycle pulse is generated for every edge of the incoming signal"]
376    #[inline(always)]
377    pub fn bothedges(self) -> &'a mut W {
378        self.variant(EDSEL_A::BOTHEDGES)
379    }
380}
381#[doc = "Field `STRETCH` reader - Stretch Channel Output"]
382pub type STRETCH_R = crate::BitReader<bool>;
383#[doc = "Field `STRETCH` writer - Stretch Channel Output"]
384pub type STRETCH_W<'a, const O: u8> = crate::BitWriter<'a, u32, CH0_CTRL_SPEC, bool, O>;
385#[doc = "Field `INV` reader - Invert Channel"]
386pub type INV_R = crate::BitReader<bool>;
387#[doc = "Field `INV` writer - Invert Channel"]
388pub type INV_W<'a, const O: u8> = crate::BitWriter<'a, u32, CH0_CTRL_SPEC, bool, O>;
389#[doc = "Field `ORPREV` reader - Or Previous"]
390pub type ORPREV_R = crate::BitReader<bool>;
391#[doc = "Field `ORPREV` writer - Or Previous"]
392pub type ORPREV_W<'a, const O: u8> = crate::BitWriter<'a, u32, CH0_CTRL_SPEC, bool, O>;
393#[doc = "Field `ANDNEXT` reader - And Next"]
394pub type ANDNEXT_R = crate::BitReader<bool>;
395#[doc = "Field `ANDNEXT` writer - And Next"]
396pub type ANDNEXT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CH0_CTRL_SPEC, bool, O>;
397#[doc = "Field `ASYNC` reader - Asynchronous Reflex"]
398pub type ASYNC_R = crate::BitReader<bool>;
399#[doc = "Field `ASYNC` writer - Asynchronous Reflex"]
400pub type ASYNC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CH0_CTRL_SPEC, bool, O>;
401impl R {
402    #[doc = "Bits 0:2 - Signal Select"]
403    #[inline(always)]
404    pub fn sigsel(&self) -> SIGSEL_R {
405        SIGSEL_R::new((self.bits & 7) as u8)
406    }
407    #[doc = "Bits 8:14 - Source Select"]
408    #[inline(always)]
409    pub fn sourcesel(&self) -> SOURCESEL_R {
410        SOURCESEL_R::new(((self.bits >> 8) & 0x7f) as u8)
411    }
412    #[doc = "Bits 20:21 - Edge Detect Select"]
413    #[inline(always)]
414    pub fn edsel(&self) -> EDSEL_R {
415        EDSEL_R::new(((self.bits >> 20) & 3) as u8)
416    }
417    #[doc = "Bit 25 - Stretch Channel Output"]
418    #[inline(always)]
419    pub fn stretch(&self) -> STRETCH_R {
420        STRETCH_R::new(((self.bits >> 25) & 1) != 0)
421    }
422    #[doc = "Bit 26 - Invert Channel"]
423    #[inline(always)]
424    pub fn inv(&self) -> INV_R {
425        INV_R::new(((self.bits >> 26) & 1) != 0)
426    }
427    #[doc = "Bit 27 - Or Previous"]
428    #[inline(always)]
429    pub fn orprev(&self) -> ORPREV_R {
430        ORPREV_R::new(((self.bits >> 27) & 1) != 0)
431    }
432    #[doc = "Bit 28 - And Next"]
433    #[inline(always)]
434    pub fn andnext(&self) -> ANDNEXT_R {
435        ANDNEXT_R::new(((self.bits >> 28) & 1) != 0)
436    }
437    #[doc = "Bit 30 - Asynchronous Reflex"]
438    #[inline(always)]
439    pub fn async_(&self) -> ASYNC_R {
440        ASYNC_R::new(((self.bits >> 30) & 1) != 0)
441    }
442}
443impl W {
444    #[doc = "Bits 0:2 - Signal Select"]
445    #[inline(always)]
446    #[must_use]
447    pub fn sigsel(&mut self) -> SIGSEL_W<0> {
448        SIGSEL_W::new(self)
449    }
450    #[doc = "Bits 8:14 - Source Select"]
451    #[inline(always)]
452    #[must_use]
453    pub fn sourcesel(&mut self) -> SOURCESEL_W<8> {
454        SOURCESEL_W::new(self)
455    }
456    #[doc = "Bits 20:21 - Edge Detect Select"]
457    #[inline(always)]
458    #[must_use]
459    pub fn edsel(&mut self) -> EDSEL_W<20> {
460        EDSEL_W::new(self)
461    }
462    #[doc = "Bit 25 - Stretch Channel Output"]
463    #[inline(always)]
464    #[must_use]
465    pub fn stretch(&mut self) -> STRETCH_W<25> {
466        STRETCH_W::new(self)
467    }
468    #[doc = "Bit 26 - Invert Channel"]
469    #[inline(always)]
470    #[must_use]
471    pub fn inv(&mut self) -> INV_W<26> {
472        INV_W::new(self)
473    }
474    #[doc = "Bit 27 - Or Previous"]
475    #[inline(always)]
476    #[must_use]
477    pub fn orprev(&mut self) -> ORPREV_W<27> {
478        ORPREV_W::new(self)
479    }
480    #[doc = "Bit 28 - And Next"]
481    #[inline(always)]
482    #[must_use]
483    pub fn andnext(&mut self) -> ANDNEXT_W<28> {
484        ANDNEXT_W::new(self)
485    }
486    #[doc = "Bit 30 - Asynchronous Reflex"]
487    #[inline(always)]
488    #[must_use]
489    pub fn async_(&mut self) -> ASYNC_W<30> {
490        ASYNC_W::new(self)
491    }
492    #[doc = "Writes raw bits to the register."]
493    #[inline(always)]
494    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
495        self.0.bits(bits);
496        self
497    }
498}
499#[doc = "Channel Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch0_ctrl](index.html) module"]
500pub struct CH0_CTRL_SPEC;
501impl crate::RegisterSpec for CH0_CTRL_SPEC {
502    type Ux = u32;
503}
504#[doc = "`read()` method returns [ch0_ctrl::R](R) reader structure"]
505impl crate::Readable for CH0_CTRL_SPEC {
506    type Reader = R;
507}
508#[doc = "`write(|w| ..)` method takes [ch0_ctrl::W](W) writer structure"]
509impl crate::Writable for CH0_CTRL_SPEC {
510    type Writer = W;
511    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
512    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
513}
514#[doc = "`reset()` method sets CH0_CTRL to value 0"]
515impl crate::Resettable for CH0_CTRL_SPEC {
516    const RESET_VALUE: Self::Ux = 0;
517}
efm32jg1b_pac/efm32jg1b100/prs/ch0_ctrl.rs

efm32jg1b_pac/efm32jg1b100/prs/
ch0_ctrl.rs
