efm32jg12b500_pac/prs/
ch2_ctrl.rs

1#[doc = "Register `CH2_CTRL` reader"]
2pub struct R(crate::R<CH2_CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CH2_CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CH2_CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CH2_CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CH2_CTRL` writer"]
17pub struct W(crate::W<CH2_CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CH2_CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CH2_CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CH2_CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SIGSEL` reader - Signal Select"]
38pub type SIGSEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `SIGSEL` writer - Signal Select"]
40pub type SIGSEL_W<'a> = crate::FieldWriter<'a, u32, CH2_CTRL_SPEC, u8, u8, 3, 0>;
41#[doc = "Source Select\n\nValue on reset: 0"]
42#[derive(Clone, Copy, Debug, PartialEq)]
43#[repr(u8)]
44pub enum SOURCESEL_A {
45    #[doc = "0: No source selected"]
46    NONE = 0,
47    #[doc = "1: Peripheral Reflex System"]
48    PRSL = 1,
49    #[doc = "2: Peripheral Reflex System"]
50    PRSH = 2,
51    #[doc = "3: Analog Comparator 0"]
52    ACMP0 = 3,
53    #[doc = "4: Analog Comparator 1"]
54    ACMP1 = 4,
55    #[doc = "5: Analog to Digital Converter 0"]
56    ADC0 = 5,
57    #[doc = "7: Low Energy Sensor Interface"]
58    LESENSEL = 7,
59    #[doc = "8: Low Energy Sensor Interface"]
60    LESENSEH = 8,
61    #[doc = "9: Low Energy Sensor Interface"]
62    LESENSED = 9,
63    #[doc = "10: Low Energy Sensor Interface"]
64    LESENSE = 10,
65    #[doc = "11: Real-Time Counter and Calendar"]
66    RTCC = 11,
67    #[doc = "12: General purpose Input/Output"]
68    GPIOL = 12,
69    #[doc = "13: General purpose Input/Output"]
70    GPIOH = 13,
71    #[doc = "14: Low Energy Timer 0"]
72    LETIMER0 = 14,
73    #[doc = "15: Pulse Counter 0"]
74    PCNT0 = 15,
75    #[doc = "16: Pulse Counter 1"]
76    PCNT1 = 16,
77    #[doc = "17: Pulse Counter 2"]
78    PCNT2 = 17,
79    #[doc = "18: Clock Management Unit"]
80    CMU = 18,
81    #[doc = "24: Digital to Analog Converter 0"]
82    VDAC0 = 24,
83    #[doc = "26: CRYOTIMER"]
84    CRYOTIMER = 26,
85    #[doc = "48: Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
86    USART0 = 48,
87    #[doc = "49: Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
88    USART1 = 49,
89    #[doc = "50: Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
90    USART2 = 50,
91    #[doc = "51: Universal Synchronous/Asynchronous Receiver/Transmitter 3"]
92    USART3 = 51,
93    #[doc = "60: Timer 0"]
94    TIMER0 = 60,
95    #[doc = "61: Timer 1"]
96    TIMER1 = 61,
97    #[doc = "62: Wide Timer 0"]
98    WTIMER0 = 62,
99    #[doc = "63: Wide Timer 1"]
100    WTIMER1 = 63,
101    #[doc = "67: `1000011`"]
102    CM4 = 67,
103}
104impl From<SOURCESEL_A> for u8 {
105    #[inline(always)]
106    fn from(variant: SOURCESEL_A) -> Self {
107        variant as _
108    }
109}
110#[doc = "Field `SOURCESEL` reader - Source Select"]
111pub type SOURCESEL_R = crate::FieldReader<u8, SOURCESEL_A>;
112impl SOURCESEL_R {
113    #[doc = "Get enumerated values variant"]
114    #[inline(always)]
115    pub fn variant(&self) -> Option<SOURCESEL_A> {
116        match self.bits {
117            0 => Some(SOURCESEL_A::NONE),
118            1 => Some(SOURCESEL_A::PRSL),
119            2 => Some(SOURCESEL_A::PRSH),
120            3 => Some(SOURCESEL_A::ACMP0),
121            4 => Some(SOURCESEL_A::ACMP1),
122            5 => Some(SOURCESEL_A::ADC0),
123            7 => Some(SOURCESEL_A::LESENSEL),
124            8 => Some(SOURCESEL_A::LESENSEH),
125            9 => Some(SOURCESEL_A::LESENSED),
126            10 => Some(SOURCESEL_A::LESENSE),
127            11 => Some(SOURCESEL_A::RTCC),
128            12 => Some(SOURCESEL_A::GPIOL),
129            13 => Some(SOURCESEL_A::GPIOH),
130            14 => Some(SOURCESEL_A::LETIMER0),
131            15 => Some(SOURCESEL_A::PCNT0),
132            16 => Some(SOURCESEL_A::PCNT1),
133            17 => Some(SOURCESEL_A::PCNT2),
134            18 => Some(SOURCESEL_A::CMU),
135            24 => Some(SOURCESEL_A::VDAC0),
136            26 => Some(SOURCESEL_A::CRYOTIMER),
137            48 => Some(SOURCESEL_A::USART0),
138            49 => Some(SOURCESEL_A::USART1),
139            50 => Some(SOURCESEL_A::USART2),
140            51 => Some(SOURCESEL_A::USART3),
141            60 => Some(SOURCESEL_A::TIMER0),
142            61 => Some(SOURCESEL_A::TIMER1),
143            62 => Some(SOURCESEL_A::WTIMER0),
144            63 => Some(SOURCESEL_A::WTIMER1),
145            67 => Some(SOURCESEL_A::CM4),
146            _ => None,
147        }
148    }
149    #[doc = "Checks if the value of the field is `NONE`"]
150    #[inline(always)]
151    pub fn is_none(&self) -> bool {
152        *self == SOURCESEL_A::NONE
153    }
154    #[doc = "Checks if the value of the field is `PRSL`"]
155    #[inline(always)]
156    pub fn is_prsl(&self) -> bool {
157        *self == SOURCESEL_A::PRSL
158    }
159    #[doc = "Checks if the value of the field is `PRSH`"]
160    #[inline(always)]
161    pub fn is_prsh(&self) -> bool {
162        *self == SOURCESEL_A::PRSH
163    }
164    #[doc = "Checks if the value of the field is `ACMP0`"]
165    #[inline(always)]
166    pub fn is_acmp0(&self) -> bool {
167        *self == SOURCESEL_A::ACMP0
168    }
169    #[doc = "Checks if the value of the field is `ACMP1`"]
170    #[inline(always)]
171    pub fn is_acmp1(&self) -> bool {
172        *self == SOURCESEL_A::ACMP1
173    }
174    #[doc = "Checks if the value of the field is `ADC0`"]
175    #[inline(always)]
176    pub fn is_adc0(&self) -> bool {
177        *self == SOURCESEL_A::ADC0
178    }
179    #[doc = "Checks if the value of the field is `LESENSEL`"]
180    #[inline(always)]
181    pub fn is_lesensel(&self) -> bool {
182        *self == SOURCESEL_A::LESENSEL
183    }
184    #[doc = "Checks if the value of the field is `LESENSEH`"]
185    #[inline(always)]
186    pub fn is_lesenseh(&self) -> bool {
187        *self == SOURCESEL_A::LESENSEH
188    }
189    #[doc = "Checks if the value of the field is `LESENSED`"]
190    #[inline(always)]
191    pub fn is_lesensed(&self) -> bool {
192        *self == SOURCESEL_A::LESENSED
193    }
194    #[doc = "Checks if the value of the field is `LESENSE`"]
195    #[inline(always)]
196    pub fn is_lesense(&self) -> bool {
197        *self == SOURCESEL_A::LESENSE
198    }
199    #[doc = "Checks if the value of the field is `RTCC`"]
200    #[inline(always)]
201    pub fn is_rtcc(&self) -> bool {
202        *self == SOURCESEL_A::RTCC
203    }
204    #[doc = "Checks if the value of the field is `GPIOL`"]
205    #[inline(always)]
206    pub fn is_gpiol(&self) -> bool {
207        *self == SOURCESEL_A::GPIOL
208    }
209    #[doc = "Checks if the value of the field is `GPIOH`"]
210    #[inline(always)]
211    pub fn is_gpioh(&self) -> bool {
212        *self == SOURCESEL_A::GPIOH
213    }
214    #[doc = "Checks if the value of the field is `LETIMER0`"]
215    #[inline(always)]
216    pub fn is_letimer0(&self) -> bool {
217        *self == SOURCESEL_A::LETIMER0
218    }
219    #[doc = "Checks if the value of the field is `PCNT0`"]
220    #[inline(always)]
221    pub fn is_pcnt0(&self) -> bool {
222        *self == SOURCESEL_A::PCNT0
223    }
224    #[doc = "Checks if the value of the field is `PCNT1`"]
225    #[inline(always)]
226    pub fn is_pcnt1(&self) -> bool {
227        *self == SOURCESEL_A::PCNT1
228    }
229    #[doc = "Checks if the value of the field is `PCNT2`"]
230    #[inline(always)]
231    pub fn is_pcnt2(&self) -> bool {
232        *self == SOURCESEL_A::PCNT2
233    }
234    #[doc = "Checks if the value of the field is `CMU`"]
235    #[inline(always)]
236    pub fn is_cmu(&self) -> bool {
237        *self == SOURCESEL_A::CMU
238    }
239    #[doc = "Checks if the value of the field is `VDAC0`"]
240    #[inline(always)]
241    pub fn is_vdac0(&self) -> bool {
242        *self == SOURCESEL_A::VDAC0
243    }
244    #[doc = "Checks if the value of the field is `CRYOTIMER`"]
245    #[inline(always)]
246    pub fn is_cryotimer(&self) -> bool {
247        *self == SOURCESEL_A::CRYOTIMER
248    }
249    #[doc = "Checks if the value of the field is `USART0`"]
250    #[inline(always)]
251    pub fn is_usart0(&self) -> bool {
252        *self == SOURCESEL_A::USART0
253    }
254    #[doc = "Checks if the value of the field is `USART1`"]
255    #[inline(always)]
256    pub fn is_usart1(&self) -> bool {
257        *self == SOURCESEL_A::USART1
258    }
259    #[doc = "Checks if the value of the field is `USART2`"]
260    #[inline(always)]
261    pub fn is_usart2(&self) -> bool {
262        *self == SOURCESEL_A::USART2
263    }
264    #[doc = "Checks if the value of the field is `USART3`"]
265    #[inline(always)]
266    pub fn is_usart3(&self) -> bool {
267        *self == SOURCESEL_A::USART3
268    }
269    #[doc = "Checks if the value of the field is `TIMER0`"]
270    #[inline(always)]
271    pub fn is_timer0(&self) -> bool {
272        *self == SOURCESEL_A::TIMER0
273    }
274    #[doc = "Checks if the value of the field is `TIMER1`"]
275    #[inline(always)]
276    pub fn is_timer1(&self) -> bool {
277        *self == SOURCESEL_A::TIMER1
278    }
279    #[doc = "Checks if the value of the field is `WTIMER0`"]
280    #[inline(always)]
281    pub fn is_wtimer0(&self) -> bool {
282        *self == SOURCESEL_A::WTIMER0
283    }
284    #[doc = "Checks if the value of the field is `WTIMER1`"]
285    #[inline(always)]
286    pub fn is_wtimer1(&self) -> bool {
287        *self == SOURCESEL_A::WTIMER1
288    }
289    #[doc = "Checks if the value of the field is `CM4`"]
290    #[inline(always)]
291    pub fn is_cm4(&self) -> bool {
292        *self == SOURCESEL_A::CM4
293    }
294}
295#[doc = "Field `SOURCESEL` writer - Source Select"]
296pub type SOURCESEL_W<'a> = crate::FieldWriter<'a, u32, CH2_CTRL_SPEC, u8, SOURCESEL_A, 7, 8>;
297impl<'a> SOURCESEL_W<'a> {
298    #[doc = "No source selected"]
299    #[inline(always)]
300    pub fn none(self) -> &'a mut W {
301        self.variant(SOURCESEL_A::NONE)
302    }
303    #[doc = "Peripheral Reflex System"]
304    #[inline(always)]
305    pub fn prsl(self) -> &'a mut W {
306        self.variant(SOURCESEL_A::PRSL)
307    }
308    #[doc = "Peripheral Reflex System"]
309    #[inline(always)]
310    pub fn prsh(self) -> &'a mut W {
311        self.variant(SOURCESEL_A::PRSH)
312    }
313    #[doc = "Analog Comparator 0"]
314    #[inline(always)]
315    pub fn acmp0(self) -> &'a mut W {
316        self.variant(SOURCESEL_A::ACMP0)
317    }
318    #[doc = "Analog Comparator 1"]
319    #[inline(always)]
320    pub fn acmp1(self) -> &'a mut W {
321        self.variant(SOURCESEL_A::ACMP1)
322    }
323    #[doc = "Analog to Digital Converter 0"]
324    #[inline(always)]
325    pub fn adc0(self) -> &'a mut W {
326        self.variant(SOURCESEL_A::ADC0)
327    }
328    #[doc = "Low Energy Sensor Interface"]
329    #[inline(always)]
330    pub fn lesensel(self) -> &'a mut W {
331        self.variant(SOURCESEL_A::LESENSEL)
332    }
333    #[doc = "Low Energy Sensor Interface"]
334    #[inline(always)]
335    pub fn lesenseh(self) -> &'a mut W {
336        self.variant(SOURCESEL_A::LESENSEH)
337    }
338    #[doc = "Low Energy Sensor Interface"]
339    #[inline(always)]
340    pub fn lesensed(self) -> &'a mut W {
341        self.variant(SOURCESEL_A::LESENSED)
342    }
343    #[doc = "Low Energy Sensor Interface"]
344    #[inline(always)]
345    pub fn lesense(self) -> &'a mut W {
346        self.variant(SOURCESEL_A::LESENSE)
347    }
348    #[doc = "Real-Time Counter and Calendar"]
349    #[inline(always)]
350    pub fn rtcc(self) -> &'a mut W {
351        self.variant(SOURCESEL_A::RTCC)
352    }
353    #[doc = "General purpose Input/Output"]
354    #[inline(always)]
355    pub fn gpiol(self) -> &'a mut W {
356        self.variant(SOURCESEL_A::GPIOL)
357    }
358    #[doc = "General purpose Input/Output"]
359    #[inline(always)]
360    pub fn gpioh(self) -> &'a mut W {
361        self.variant(SOURCESEL_A::GPIOH)
362    }
363    #[doc = "Low Energy Timer 0"]
364    #[inline(always)]
365    pub fn letimer0(self) -> &'a mut W {
366        self.variant(SOURCESEL_A::LETIMER0)
367    }
368    #[doc = "Pulse Counter 0"]
369    #[inline(always)]
370    pub fn pcnt0(self) -> &'a mut W {
371        self.variant(SOURCESEL_A::PCNT0)
372    }
373    #[doc = "Pulse Counter 1"]
374    #[inline(always)]
375    pub fn pcnt1(self) -> &'a mut W {
376        self.variant(SOURCESEL_A::PCNT1)
377    }
378    #[doc = "Pulse Counter 2"]
379    #[inline(always)]
380    pub fn pcnt2(self) -> &'a mut W {
381        self.variant(SOURCESEL_A::PCNT2)
382    }
383    #[doc = "Clock Management Unit"]
384    #[inline(always)]
385    pub fn cmu(self) -> &'a mut W {
386        self.variant(SOURCESEL_A::CMU)
387    }
388    #[doc = "Digital to Analog Converter 0"]
389    #[inline(always)]
390    pub fn vdac0(self) -> &'a mut W {
391        self.variant(SOURCESEL_A::VDAC0)
392    }
393    #[doc = "CRYOTIMER"]
394    #[inline(always)]
395    pub fn cryotimer(self) -> &'a mut W {
396        self.variant(SOURCESEL_A::CRYOTIMER)
397    }
398    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
399    #[inline(always)]
400    pub fn usart0(self) -> &'a mut W {
401        self.variant(SOURCESEL_A::USART0)
402    }
403    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
404    #[inline(always)]
405    pub fn usart1(self) -> &'a mut W {
406        self.variant(SOURCESEL_A::USART1)
407    }
408    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
409    #[inline(always)]
410    pub fn usart2(self) -> &'a mut W {
411        self.variant(SOURCESEL_A::USART2)
412    }
413    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 3"]
414    #[inline(always)]
415    pub fn usart3(self) -> &'a mut W {
416        self.variant(SOURCESEL_A::USART3)
417    }
418    #[doc = "Timer 0"]
419    #[inline(always)]
420    pub fn timer0(self) -> &'a mut W {
421        self.variant(SOURCESEL_A::TIMER0)
422    }
423    #[doc = "Timer 1"]
424    #[inline(always)]
425    pub fn timer1(self) -> &'a mut W {
426        self.variant(SOURCESEL_A::TIMER1)
427    }
428    #[doc = "Wide Timer 0"]
429    #[inline(always)]
430    pub fn wtimer0(self) -> &'a mut W {
431        self.variant(SOURCESEL_A::WTIMER0)
432    }
433    #[doc = "Wide Timer 1"]
434    #[inline(always)]
435    pub fn wtimer1(self) -> &'a mut W {
436        self.variant(SOURCESEL_A::WTIMER1)
437    }
438    #[doc = "`1000011`"]
439    #[inline(always)]
440    pub fn cm4(self) -> &'a mut W {
441        self.variant(SOURCESEL_A::CM4)
442    }
443}
444#[doc = "Edge Detect Select\n\nValue on reset: 0"]
445#[derive(Clone, Copy, Debug, PartialEq)]
446#[repr(u8)]
447pub enum EDSEL_A {
448    #[doc = "0: Signal is left as it is"]
449    OFF = 0,
450    #[doc = "1: A one HFCLK cycle pulse is generated for every positive edge of the incoming signal"]
451    POSEDGE = 1,
452    #[doc = "2: A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
453    NEGEDGE = 2,
454    #[doc = "3: A one HFCLK clock cycle pulse is generated for every edge of the incoming signal"]
455    BOTHEDGES = 3,
456}
457impl From<EDSEL_A> for u8 {
458    #[inline(always)]
459    fn from(variant: EDSEL_A) -> Self {
460        variant as _
461    }
462}
463#[doc = "Field `EDSEL` reader - Edge Detect Select"]
464pub type EDSEL_R = crate::FieldReader<u8, EDSEL_A>;
465impl EDSEL_R {
466    #[doc = "Get enumerated values variant"]
467    #[inline(always)]
468    pub fn variant(&self) -> EDSEL_A {
469        match self.bits {
470            0 => EDSEL_A::OFF,
471            1 => EDSEL_A::POSEDGE,
472            2 => EDSEL_A::NEGEDGE,
473            3 => EDSEL_A::BOTHEDGES,
474            _ => unreachable!(),
475        }
476    }
477    #[doc = "Checks if the value of the field is `OFF`"]
478    #[inline(always)]
479    pub fn is_off(&self) -> bool {
480        *self == EDSEL_A::OFF
481    }
482    #[doc = "Checks if the value of the field is `POSEDGE`"]
483    #[inline(always)]
484    pub fn is_posedge(&self) -> bool {
485        *self == EDSEL_A::POSEDGE
486    }
487    #[doc = "Checks if the value of the field is `NEGEDGE`"]
488    #[inline(always)]
489    pub fn is_negedge(&self) -> bool {
490        *self == EDSEL_A::NEGEDGE
491    }
492    #[doc = "Checks if the value of the field is `BOTHEDGES`"]
493    #[inline(always)]
494    pub fn is_bothedges(&self) -> bool {
495        *self == EDSEL_A::BOTHEDGES
496    }
497}
498#[doc = "Field `EDSEL` writer - Edge Detect Select"]
499pub type EDSEL_W<'a> = crate::FieldWriterSafe<'a, u32, CH2_CTRL_SPEC, u8, EDSEL_A, 2, 20>;
500impl<'a> EDSEL_W<'a> {
501    #[doc = "Signal is left as it is"]
502    #[inline(always)]
503    pub fn off(self) -> &'a mut W {
504        self.variant(EDSEL_A::OFF)
505    }
506    #[doc = "A one HFCLK cycle pulse is generated for every positive edge of the incoming signal"]
507    #[inline(always)]
508    pub fn posedge(self) -> &'a mut W {
509        self.variant(EDSEL_A::POSEDGE)
510    }
511    #[doc = "A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
512    #[inline(always)]
513    pub fn negedge(self) -> &'a mut W {
514        self.variant(EDSEL_A::NEGEDGE)
515    }
516    #[doc = "A one HFCLK clock cycle pulse is generated for every edge of the incoming signal"]
517    #[inline(always)]
518    pub fn bothedges(self) -> &'a mut W {
519        self.variant(EDSEL_A::BOTHEDGES)
520    }
521}
522#[doc = "Field `STRETCH` reader - Stretch Channel Output"]
523pub type STRETCH_R = crate::BitReader<bool>;
524#[doc = "Field `STRETCH` writer - Stretch Channel Output"]
525pub type STRETCH_W<'a> = crate::BitWriter<'a, u32, CH2_CTRL_SPEC, bool, 25>;
526#[doc = "Field `INV` reader - Invert Channel"]
527pub type INV_R = crate::BitReader<bool>;
528#[doc = "Field `INV` writer - Invert Channel"]
529pub type INV_W<'a> = crate::BitWriter<'a, u32, CH2_CTRL_SPEC, bool, 26>;
530#[doc = "Field `ORPREV` reader - Or Previous"]
531pub type ORPREV_R = crate::BitReader<bool>;
532#[doc = "Field `ORPREV` writer - Or Previous"]
533pub type ORPREV_W<'a> = crate::BitWriter<'a, u32, CH2_CTRL_SPEC, bool, 27>;
534#[doc = "Field `ANDNEXT` reader - And Next"]
535pub type ANDNEXT_R = crate::BitReader<bool>;
536#[doc = "Field `ANDNEXT` writer - And Next"]
537pub type ANDNEXT_W<'a> = crate::BitWriter<'a, u32, CH2_CTRL_SPEC, bool, 28>;
538#[doc = "Field `ASYNC` reader - Asynchronous Reflex"]
539pub type ASYNC_R = crate::BitReader<bool>;
540#[doc = "Field `ASYNC` writer - Asynchronous Reflex"]
541pub type ASYNC_W<'a> = crate::BitWriter<'a, u32, CH2_CTRL_SPEC, bool, 30>;
542impl R {
543    #[doc = "Bits 0:2 - Signal Select"]
544    #[inline(always)]
545    pub fn sigsel(&self) -> SIGSEL_R {
546        SIGSEL_R::new((self.bits & 7) as u8)
547    }
548    #[doc = "Bits 8:14 - Source Select"]
549    #[inline(always)]
550    pub fn sourcesel(&self) -> SOURCESEL_R {
551        SOURCESEL_R::new(((self.bits >> 8) & 0x7f) as u8)
552    }
553    #[doc = "Bits 20:21 - Edge Detect Select"]
554    #[inline(always)]
555    pub fn edsel(&self) -> EDSEL_R {
556        EDSEL_R::new(((self.bits >> 20) & 3) as u8)
557    }
558    #[doc = "Bit 25 - Stretch Channel Output"]
559    #[inline(always)]
560    pub fn stretch(&self) -> STRETCH_R {
561        STRETCH_R::new(((self.bits >> 25) & 1) != 0)
562    }
563    #[doc = "Bit 26 - Invert Channel"]
564    #[inline(always)]
565    pub fn inv(&self) -> INV_R {
566        INV_R::new(((self.bits >> 26) & 1) != 0)
567    }
568    #[doc = "Bit 27 - Or Previous"]
569    #[inline(always)]
570    pub fn orprev(&self) -> ORPREV_R {
571        ORPREV_R::new(((self.bits >> 27) & 1) != 0)
572    }
573    #[doc = "Bit 28 - And Next"]
574    #[inline(always)]
575    pub fn andnext(&self) -> ANDNEXT_R {
576        ANDNEXT_R::new(((self.bits >> 28) & 1) != 0)
577    }
578    #[doc = "Bit 30 - Asynchronous Reflex"]
579    #[inline(always)]
580    pub fn async_(&self) -> ASYNC_R {
581        ASYNC_R::new(((self.bits >> 30) & 1) != 0)
582    }
583}
584impl W {
585    #[doc = "Bits 0:2 - Signal Select"]
586    #[inline(always)]
587    pub fn sigsel(&mut self) -> SIGSEL_W {
588        SIGSEL_W::new(self)
589    }
590    #[doc = "Bits 8:14 - Source Select"]
591    #[inline(always)]
592    pub fn sourcesel(&mut self) -> SOURCESEL_W {
593        SOURCESEL_W::new(self)
594    }
595    #[doc = "Bits 20:21 - Edge Detect Select"]
596    #[inline(always)]
597    pub fn edsel(&mut self) -> EDSEL_W {
598        EDSEL_W::new(self)
599    }
600    #[doc = "Bit 25 - Stretch Channel Output"]
601    #[inline(always)]
602    pub fn stretch(&mut self) -> STRETCH_W {
603        STRETCH_W::new(self)
604    }
605    #[doc = "Bit 26 - Invert Channel"]
606    #[inline(always)]
607    pub fn inv(&mut self) -> INV_W {
608        INV_W::new(self)
609    }
610    #[doc = "Bit 27 - Or Previous"]
611    #[inline(always)]
612    pub fn orprev(&mut self) -> ORPREV_W {
613        ORPREV_W::new(self)
614    }
615    #[doc = "Bit 28 - And Next"]
616    #[inline(always)]
617    pub fn andnext(&mut self) -> ANDNEXT_W {
618        ANDNEXT_W::new(self)
619    }
620    #[doc = "Bit 30 - Asynchronous Reflex"]
621    #[inline(always)]
622    pub fn async_(&mut self) -> ASYNC_W {
623        ASYNC_W::new(self)
624    }
625    #[doc = "Writes raw bits to the register."]
626    #[inline(always)]
627    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
628        self.0.bits(bits);
629        self
630    }
631}
632#[doc = "Channel Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch2_ctrl](index.html) module"]
633pub struct CH2_CTRL_SPEC;
634impl crate::RegisterSpec for CH2_CTRL_SPEC {
635    type Ux = u32;
636}
637#[doc = "`read()` method returns [ch2_ctrl::R](R) reader structure"]
638impl crate::Readable for CH2_CTRL_SPEC {
639    type Reader = R;
640}
641#[doc = "`write(|w| ..)` method takes [ch2_ctrl::W](W) writer structure"]
642impl crate::Writable for CH2_CTRL_SPEC {
643    type Writer = W;
644}
645#[doc = "`reset()` method sets CH2_CTRL to value 0"]
646impl crate::Resettable for CH2_CTRL_SPEC {
647    #[inline(always)]
648    fn reset_value() -> Self::Ux {
649        0
650    }
651}
efm32jg12b500_pac/prs/ch2_ctrl.rs

efm32jg12b500_pac/prs/
ch2_ctrl.rs
