efm32jg12b_pac/efm32jg12b500/smu/
ppupatd1.rs

1#[doc = "Register `PPUPATD1` reader"]
2pub struct R(crate::R<PPUPATD1_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<PPUPATD1_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<PPUPATD1_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<PPUPATD1_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `PPUPATD1` writer"]
17pub struct W(crate::W<PPUPATD1_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<PPUPATD1_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<PPUPATD1_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<PPUPATD1_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `RMU` reader - Reset Management Unit access control bit"]
38pub type RMU_R = crate::BitReader<bool>;
39#[doc = "Field `RMU` writer - Reset Management Unit access control bit"]
40pub type RMU_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, O>;
41#[doc = "Field `RTCC` reader - Real-Time Counter and Calendar access control bit"]
42pub type RTCC_R = crate::BitReader<bool>;
43#[doc = "Field `RTCC` writer - Real-Time Counter and Calendar access control bit"]
44pub type RTCC_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, O>;
45#[doc = "Field `SMU` reader - Security Management Unit access control bit"]
46pub type SMU_R = crate::BitReader<bool>;
47#[doc = "Field `SMU` writer - Security Management Unit access control bit"]
48pub type SMU_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, O>;
49#[doc = "Field `TIMER0` reader - Timer 0 access control bit"]
50pub type TIMER0_R = crate::BitReader<bool>;
51#[doc = "Field `TIMER0` writer - Timer 0 access control bit"]
52pub type TIMER0_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, O>;
53#[doc = "Field `TIMER1` reader - Timer 1 access control bit"]
54pub type TIMER1_R = crate::BitReader<bool>;
55#[doc = "Field `TIMER1` writer - Timer 1 access control bit"]
56pub type TIMER1_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, O>;
57#[doc = "Field `TRNG0` reader - True Random Number Generator 0 access control bit"]
58pub type TRNG0_R = crate::BitReader<bool>;
59#[doc = "Field `TRNG0` writer - True Random Number Generator 0 access control bit"]
60pub type TRNG0_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, O>;
61#[doc = "Field `USART0` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit"]
62pub type USART0_R = crate::BitReader<bool>;
63#[doc = "Field `USART0` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit"]
64pub type USART0_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, O>;
65#[doc = "Field `USART1` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit"]
66pub type USART1_R = crate::BitReader<bool>;
67#[doc = "Field `USART1` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit"]
68pub type USART1_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, O>;
69#[doc = "Field `USART2` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit"]
70pub type USART2_R = crate::BitReader<bool>;
71#[doc = "Field `USART2` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit"]
72pub type USART2_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, O>;
73#[doc = "Field `USART3` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit"]
74pub type USART3_R = crate::BitReader<bool>;
75#[doc = "Field `USART3` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit"]
76pub type USART3_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, O>;
77#[doc = "Field `WDOG0` reader - Watchdog 0 access control bit"]
78pub type WDOG0_R = crate::BitReader<bool>;
79#[doc = "Field `WDOG0` writer - Watchdog 0 access control bit"]
80pub type WDOG0_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, O>;
81#[doc = "Field `WDOG1` reader - Watchdog 1 access control bit"]
82pub type WDOG1_R = crate::BitReader<bool>;
83#[doc = "Field `WDOG1` writer - Watchdog 1 access control bit"]
84pub type WDOG1_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, O>;
85#[doc = "Field `WTIMER0` reader - Wide Timer 0 access control bit"]
86pub type WTIMER0_R = crate::BitReader<bool>;
87#[doc = "Field `WTIMER0` writer - Wide Timer 0 access control bit"]
88pub type WTIMER0_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, O>;
89#[doc = "Field `WTIMER1` reader - Wide Timer 1 access control bit"]
90pub type WTIMER1_R = crate::BitReader<bool>;
91#[doc = "Field `WTIMER1` writer - Wide Timer 1 access control bit"]
92pub type WTIMER1_W<'a, const O: u8> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, O>;
93impl R {
94    #[doc = "Bit 1 - Reset Management Unit access control bit"]
95    #[inline(always)]
96    pub fn rmu(&self) -> RMU_R {
97        RMU_R::new(((self.bits >> 1) & 1) != 0)
98    }
99    #[doc = "Bit 2 - Real-Time Counter and Calendar access control bit"]
100    #[inline(always)]
101    pub fn rtcc(&self) -> RTCC_R {
102        RTCC_R::new(((self.bits >> 2) & 1) != 0)
103    }
104    #[doc = "Bit 3 - Security Management Unit access control bit"]
105    #[inline(always)]
106    pub fn smu(&self) -> SMU_R {
107        SMU_R::new(((self.bits >> 3) & 1) != 0)
108    }
109    #[doc = "Bit 5 - Timer 0 access control bit"]
110    #[inline(always)]
111    pub fn timer0(&self) -> TIMER0_R {
112        TIMER0_R::new(((self.bits >> 5) & 1) != 0)
113    }
114    #[doc = "Bit 6 - Timer 1 access control bit"]
115    #[inline(always)]
116    pub fn timer1(&self) -> TIMER1_R {
117        TIMER1_R::new(((self.bits >> 6) & 1) != 0)
118    }
119    #[doc = "Bit 7 - True Random Number Generator 0 access control bit"]
120    #[inline(always)]
121    pub fn trng0(&self) -> TRNG0_R {
122        TRNG0_R::new(((self.bits >> 7) & 1) != 0)
123    }
124    #[doc = "Bit 8 - Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit"]
125    #[inline(always)]
126    pub fn usart0(&self) -> USART0_R {
127        USART0_R::new(((self.bits >> 8) & 1) != 0)
128    }
129    #[doc = "Bit 9 - Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit"]
130    #[inline(always)]
131    pub fn usart1(&self) -> USART1_R {
132        USART1_R::new(((self.bits >> 9) & 1) != 0)
133    }
134    #[doc = "Bit 10 - Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit"]
135    #[inline(always)]
136    pub fn usart2(&self) -> USART2_R {
137        USART2_R::new(((self.bits >> 10) & 1) != 0)
138    }
139    #[doc = "Bit 11 - Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit"]
140    #[inline(always)]
141    pub fn usart3(&self) -> USART3_R {
142        USART3_R::new(((self.bits >> 11) & 1) != 0)
143    }
144    #[doc = "Bit 12 - Watchdog 0 access control bit"]
145    #[inline(always)]
146    pub fn wdog0(&self) -> WDOG0_R {
147        WDOG0_R::new(((self.bits >> 12) & 1) != 0)
148    }
149    #[doc = "Bit 13 - Watchdog 1 access control bit"]
150    #[inline(always)]
151    pub fn wdog1(&self) -> WDOG1_R {
152        WDOG1_R::new(((self.bits >> 13) & 1) != 0)
153    }
154    #[doc = "Bit 14 - Wide Timer 0 access control bit"]
155    #[inline(always)]
156    pub fn wtimer0(&self) -> WTIMER0_R {
157        WTIMER0_R::new(((self.bits >> 14) & 1) != 0)
158    }
159    #[doc = "Bit 15 - Wide Timer 1 access control bit"]
160    #[inline(always)]
161    pub fn wtimer1(&self) -> WTIMER1_R {
162        WTIMER1_R::new(((self.bits >> 15) & 1) != 0)
163    }
164}
165impl W {
166    #[doc = "Bit 1 - Reset Management Unit access control bit"]
167    #[inline(always)]
168    #[must_use]
169    pub fn rmu(&mut self) -> RMU_W<1> {
170        RMU_W::new(self)
171    }
172    #[doc = "Bit 2 - Real-Time Counter and Calendar access control bit"]
173    #[inline(always)]
174    #[must_use]
175    pub fn rtcc(&mut self) -> RTCC_W<2> {
176        RTCC_W::new(self)
177    }
178    #[doc = "Bit 3 - Security Management Unit access control bit"]
179    #[inline(always)]
180    #[must_use]
181    pub fn smu(&mut self) -> SMU_W<3> {
182        SMU_W::new(self)
183    }
184    #[doc = "Bit 5 - Timer 0 access control bit"]
185    #[inline(always)]
186    #[must_use]
187    pub fn timer0(&mut self) -> TIMER0_W<5> {
188        TIMER0_W::new(self)
189    }
190    #[doc = "Bit 6 - Timer 1 access control bit"]
191    #[inline(always)]
192    #[must_use]
193    pub fn timer1(&mut self) -> TIMER1_W<6> {
194        TIMER1_W::new(self)
195    }
196    #[doc = "Bit 7 - True Random Number Generator 0 access control bit"]
197    #[inline(always)]
198    #[must_use]
199    pub fn trng0(&mut self) -> TRNG0_W<7> {
200        TRNG0_W::new(self)
201    }
202    #[doc = "Bit 8 - Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit"]
203    #[inline(always)]
204    #[must_use]
205    pub fn usart0(&mut self) -> USART0_W<8> {
206        USART0_W::new(self)
207    }
208    #[doc = "Bit 9 - Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit"]
209    #[inline(always)]
210    #[must_use]
211    pub fn usart1(&mut self) -> USART1_W<9> {
212        USART1_W::new(self)
213    }
214    #[doc = "Bit 10 - Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit"]
215    #[inline(always)]
216    #[must_use]
217    pub fn usart2(&mut self) -> USART2_W<10> {
218        USART2_W::new(self)
219    }
220    #[doc = "Bit 11 - Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit"]
221    #[inline(always)]
222    #[must_use]
223    pub fn usart3(&mut self) -> USART3_W<11> {
224        USART3_W::new(self)
225    }
226    #[doc = "Bit 12 - Watchdog 0 access control bit"]
227    #[inline(always)]
228    #[must_use]
229    pub fn wdog0(&mut self) -> WDOG0_W<12> {
230        WDOG0_W::new(self)
231    }
232    #[doc = "Bit 13 - Watchdog 1 access control bit"]
233    #[inline(always)]
234    #[must_use]
235    pub fn wdog1(&mut self) -> WDOG1_W<13> {
236        WDOG1_W::new(self)
237    }
238    #[doc = "Bit 14 - Wide Timer 0 access control bit"]
239    #[inline(always)]
240    #[must_use]
241    pub fn wtimer0(&mut self) -> WTIMER0_W<14> {
242        WTIMER0_W::new(self)
243    }
244    #[doc = "Bit 15 - Wide Timer 1 access control bit"]
245    #[inline(always)]
246    #[must_use]
247    pub fn wtimer1(&mut self) -> WTIMER1_W<15> {
248        WTIMER1_W::new(self)
249    }
250    #[doc = "Writes raw bits to the register."]
251    #[inline(always)]
252    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
253        self.0.bits(bits);
254        self
255    }
256}
257#[doc = "PPU Privilege Access Type Descriptor 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ppupatd1](index.html) module"]
258pub struct PPUPATD1_SPEC;
259impl crate::RegisterSpec for PPUPATD1_SPEC {
260    type Ux = u32;
261}
262#[doc = "`read()` method returns [ppupatd1::R](R) reader structure"]
263impl crate::Readable for PPUPATD1_SPEC {
264    type Reader = R;
265}
266#[doc = "`write(|w| ..)` method takes [ppupatd1::W](W) writer structure"]
267impl crate::Writable for PPUPATD1_SPEC {
268    type Writer = W;
269    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
270    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
271}
272#[doc = "`reset()` method sets PPUPATD1 to value 0"]
273impl crate::Resettable for PPUPATD1_SPEC {
274    const RESET_VALUE: Self::Ux = 0;
275}
efm32jg12b_pac/efm32jg12b500/smu/ppupatd1.rs

efm32jg12b_pac/efm32jg12b500/smu/
ppupatd1.rs
