efm32jg12b_pac/efm32jg12b500/cmu/
hfxosteadystatectrl.rs

1#[doc = "Register `HFXOSTEADYSTATECTRL` reader"]
2pub struct R(crate::R<HFXOSTEADYSTATECTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<HFXOSTEADYSTATECTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<HFXOSTEADYSTATECTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<HFXOSTEADYSTATECTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `HFXOSTEADYSTATECTRL` writer"]
17pub struct W(crate::W<HFXOSTEADYSTATECTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<HFXOSTEADYSTATECTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<HFXOSTEADYSTATECTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<HFXOSTEADYSTATECTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `IBTRIMXOCORE` reader - Sets the Steady State Oscillator Core Bias Current."]
38pub type IBTRIMXOCORE_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `IBTRIMXOCORE` writer - Sets the Steady State Oscillator Core Bias Current."]
40pub type IBTRIMXOCORE_W<'a, const O: u8> =
41    crate::FieldWriter<'a, u32, HFXOSTEADYSTATECTRL_SPEC, u8, u8, 7, O>;
42#[doc = "Field `REGISH` reader - Sets the Steady State Regulator Output Current Level (shunt Regulator)"]
43pub type REGISH_R = crate::FieldReader<u8, u8>;
44#[doc = "Field `REGISH` writer - Sets the Steady State Regulator Output Current Level (shunt Regulator)"]
45pub type REGISH_W<'a, const O: u8> =
46    crate::FieldWriter<'a, u32, HFXOSTEADYSTATECTRL_SPEC, u8, u8, 4, O>;
47#[doc = "Field `CTUNE` reader - Sets Oscillator Tuning Capacitance"]
48pub type CTUNE_R = crate::FieldReader<u16, u16>;
49#[doc = "Field `CTUNE` writer - Sets Oscillator Tuning Capacitance"]
50pub type CTUNE_W<'a, const O: u8> =
51    crate::FieldWriter<'a, u32, HFXOSTEADYSTATECTRL_SPEC, u16, u16, 9, O>;
52#[doc = "Field `REGSELILOW` reader - Controls Regulator Minimum Shunt Current Detection Relative to Nominal"]
53pub type REGSELILOW_R = crate::FieldReader<u8, u8>;
54#[doc = "Field `REGSELILOW` writer - Controls Regulator Minimum Shunt Current Detection Relative to Nominal"]
55pub type REGSELILOW_W<'a, const O: u8> =
56    crate::FieldWriter<'a, u32, HFXOSTEADYSTATECTRL_SPEC, u8, u8, 2, O>;
57#[doc = "Field `PEAKDETEN` reader - Enables Oscillator Peak Detectors"]
58pub type PEAKDETEN_R = crate::BitReader<bool>;
59#[doc = "Field `PEAKDETEN` writer - Enables Oscillator Peak Detectors"]
60pub type PEAKDETEN_W<'a, const O: u8> =
61    crate::BitWriter<'a, u32, HFXOSTEADYSTATECTRL_SPEC, bool, O>;
62#[doc = "Field `REGISHUPPER` reader - Set Regulator Output Current Level (shunt Regulator). Ish = 120uA + REGISHUPPER X 120uA"]
63pub type REGISHUPPER_R = crate::FieldReader<u8, u8>;
64#[doc = "Field `REGISHUPPER` writer - Set Regulator Output Current Level (shunt Regulator). Ish = 120uA + REGISHUPPER X 120uA"]
65pub type REGISHUPPER_W<'a, const O: u8> =
66    crate::FieldWriter<'a, u32, HFXOSTEADYSTATECTRL_SPEC, u8, u8, 4, O>;
67impl R {
68    #[doc = "Bits 0:6 - Sets the Steady State Oscillator Core Bias Current."]
69    #[inline(always)]
70    pub fn ibtrimxocore(&self) -> IBTRIMXOCORE_R {
71        IBTRIMXOCORE_R::new((self.bits & 0x7f) as u8)
72    }
73    #[doc = "Bits 7:10 - Sets the Steady State Regulator Output Current Level (shunt Regulator)"]
74    #[inline(always)]
75    pub fn regish(&self) -> REGISH_R {
76        REGISH_R::new(((self.bits >> 7) & 0x0f) as u8)
77    }
78    #[doc = "Bits 11:19 - Sets Oscillator Tuning Capacitance"]
79    #[inline(always)]
80    pub fn ctune(&self) -> CTUNE_R {
81        CTUNE_R::new(((self.bits >> 11) & 0x01ff) as u16)
82    }
83    #[doc = "Bits 24:25 - Controls Regulator Minimum Shunt Current Detection Relative to Nominal"]
84    #[inline(always)]
85    pub fn regselilow(&self) -> REGSELILOW_R {
86        REGSELILOW_R::new(((self.bits >> 24) & 3) as u8)
87    }
88    #[doc = "Bit 26 - Enables Oscillator Peak Detectors"]
89    #[inline(always)]
90    pub fn peakdeten(&self) -> PEAKDETEN_R {
91        PEAKDETEN_R::new(((self.bits >> 26) & 1) != 0)
92    }
93    #[doc = "Bits 28:31 - Set Regulator Output Current Level (shunt Regulator). Ish = 120uA + REGISHUPPER X 120uA"]
94    #[inline(always)]
95    pub fn regishupper(&self) -> REGISHUPPER_R {
96        REGISHUPPER_R::new(((self.bits >> 28) & 0x0f) as u8)
97    }
98}
99impl W {
100    #[doc = "Bits 0:6 - Sets the Steady State Oscillator Core Bias Current."]
101    #[inline(always)]
102    #[must_use]
103    pub fn ibtrimxocore(&mut self) -> IBTRIMXOCORE_W<0> {
104        IBTRIMXOCORE_W::new(self)
105    }
106    #[doc = "Bits 7:10 - Sets the Steady State Regulator Output Current Level (shunt Regulator)"]
107    #[inline(always)]
108    #[must_use]
109    pub fn regish(&mut self) -> REGISH_W<7> {
110        REGISH_W::new(self)
111    }
112    #[doc = "Bits 11:19 - Sets Oscillator Tuning Capacitance"]
113    #[inline(always)]
114    #[must_use]
115    pub fn ctune(&mut self) -> CTUNE_W<11> {
116        CTUNE_W::new(self)
117    }
118    #[doc = "Bits 24:25 - Controls Regulator Minimum Shunt Current Detection Relative to Nominal"]
119    #[inline(always)]
120    #[must_use]
121    pub fn regselilow(&mut self) -> REGSELILOW_W<24> {
122        REGSELILOW_W::new(self)
123    }
124    #[doc = "Bit 26 - Enables Oscillator Peak Detectors"]
125    #[inline(always)]
126    #[must_use]
127    pub fn peakdeten(&mut self) -> PEAKDETEN_W<26> {
128        PEAKDETEN_W::new(self)
129    }
130    #[doc = "Bits 28:31 - Set Regulator Output Current Level (shunt Regulator). Ish = 120uA + REGISHUPPER X 120uA"]
131    #[inline(always)]
132    #[must_use]
133    pub fn regishupper(&mut self) -> REGISHUPPER_W<28> {
134        REGISHUPPER_W::new(self)
135    }
136    #[doc = "Writes raw bits to the register."]
137    #[inline(always)]
138    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
139        self.0.bits(bits);
140        self
141    }
142}
143#[doc = "HFXO Steady State Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfxosteadystatectrl](index.html) module"]
144pub struct HFXOSTEADYSTATECTRL_SPEC;
145impl crate::RegisterSpec for HFXOSTEADYSTATECTRL_SPEC {
146    type Ux = u32;
147}
148#[doc = "`read()` method returns [hfxosteadystatectrl::R](R) reader structure"]
149impl crate::Readable for HFXOSTEADYSTATECTRL_SPEC {
150    type Reader = R;
151}
152#[doc = "`write(|w| ..)` method takes [hfxosteadystatectrl::W](W) writer structure"]
153impl crate::Writable for HFXOSTEADYSTATECTRL_SPEC {
154    type Writer = W;
155    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
156    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
157}
158#[doc = "`reset()` method sets HFXOSTEADYSTATECTRL to value 0xa30b_4507"]
159impl crate::Resettable for HFXOSTEADYSTATECTRL_SPEC {
160    const RESET_VALUE: Self::Ux = 0xa30b_4507;
161}
efm32jg12b_pac/efm32jg12b500/cmu/hfxosteadystatectrl.rs

efm32jg12b_pac/efm32jg12b500/cmu/
hfxosteadystatectrl.rs
