efm32jg12b_pac/efm32jg12b500/cmu/
hfbusclken0.rs

1#[doc = "Register `HFBUSCLKEN0` reader"]
2pub struct R(crate::R<HFBUSCLKEN0_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<HFBUSCLKEN0_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<HFBUSCLKEN0_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<HFBUSCLKEN0_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `HFBUSCLKEN0` writer"]
17pub struct W(crate::W<HFBUSCLKEN0_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<HFBUSCLKEN0_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<HFBUSCLKEN0_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<HFBUSCLKEN0_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CRYPTO0` reader - Advanced Encryption Standard Accelerator 0 Clock Enable"]
38pub type CRYPTO0_R = crate::BitReader<bool>;
39#[doc = "Field `CRYPTO0` writer - Advanced Encryption Standard Accelerator 0 Clock Enable"]
40pub type CRYPTO0_W<'a, const O: u8> = crate::BitWriter<'a, u32, HFBUSCLKEN0_SPEC, bool, O>;
41#[doc = "Field `CRYPTO1` reader - Advanced Encryption Standard Accelerator 1 Clock Enable"]
42pub type CRYPTO1_R = crate::BitReader<bool>;
43#[doc = "Field `CRYPTO1` writer - Advanced Encryption Standard Accelerator 1 Clock Enable"]
44pub type CRYPTO1_W<'a, const O: u8> = crate::BitWriter<'a, u32, HFBUSCLKEN0_SPEC, bool, O>;
45#[doc = "Field `LE` reader - Low Energy Peripheral Interface Clock Enable"]
46pub type LE_R = crate::BitReader<bool>;
47#[doc = "Field `LE` writer - Low Energy Peripheral Interface Clock Enable"]
48pub type LE_W<'a, const O: u8> = crate::BitWriter<'a, u32, HFBUSCLKEN0_SPEC, bool, O>;
49#[doc = "Field `GPIO` reader - General purpose Input/Output Clock Enable"]
50pub type GPIO_R = crate::BitReader<bool>;
51#[doc = "Field `GPIO` writer - General purpose Input/Output Clock Enable"]
52pub type GPIO_W<'a, const O: u8> = crate::BitWriter<'a, u32, HFBUSCLKEN0_SPEC, bool, O>;
53#[doc = "Field `PRS` reader - Peripheral Reflex System Clock Enable"]
54pub type PRS_R = crate::BitReader<bool>;
55#[doc = "Field `PRS` writer - Peripheral Reflex System Clock Enable"]
56pub type PRS_W<'a, const O: u8> = crate::BitWriter<'a, u32, HFBUSCLKEN0_SPEC, bool, O>;
57#[doc = "Field `LDMA` reader - Linked Direct Memory Access Controller Clock Enable"]
58pub type LDMA_R = crate::BitReader<bool>;
59#[doc = "Field `LDMA` writer - Linked Direct Memory Access Controller Clock Enable"]
60pub type LDMA_W<'a, const O: u8> = crate::BitWriter<'a, u32, HFBUSCLKEN0_SPEC, bool, O>;
61#[doc = "Field `GPCRC` reader - General Purpose CRC Clock Enable"]
62pub type GPCRC_R = crate::BitReader<bool>;
63#[doc = "Field `GPCRC` writer - General Purpose CRC Clock Enable"]
64pub type GPCRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, HFBUSCLKEN0_SPEC, bool, O>;
65impl R {
66    #[doc = "Bit 0 - Advanced Encryption Standard Accelerator 0 Clock Enable"]
67    #[inline(always)]
68    pub fn crypto0(&self) -> CRYPTO0_R {
69        CRYPTO0_R::new((self.bits & 1) != 0)
70    }
71    #[doc = "Bit 1 - Advanced Encryption Standard Accelerator 1 Clock Enable"]
72    #[inline(always)]
73    pub fn crypto1(&self) -> CRYPTO1_R {
74        CRYPTO1_R::new(((self.bits >> 1) & 1) != 0)
75    }
76    #[doc = "Bit 2 - Low Energy Peripheral Interface Clock Enable"]
77    #[inline(always)]
78    pub fn le(&self) -> LE_R {
79        LE_R::new(((self.bits >> 2) & 1) != 0)
80    }
81    #[doc = "Bit 3 - General purpose Input/Output Clock Enable"]
82    #[inline(always)]
83    pub fn gpio(&self) -> GPIO_R {
84        GPIO_R::new(((self.bits >> 3) & 1) != 0)
85    }
86    #[doc = "Bit 4 - Peripheral Reflex System Clock Enable"]
87    #[inline(always)]
88    pub fn prs(&self) -> PRS_R {
89        PRS_R::new(((self.bits >> 4) & 1) != 0)
90    }
91    #[doc = "Bit 5 - Linked Direct Memory Access Controller Clock Enable"]
92    #[inline(always)]
93    pub fn ldma(&self) -> LDMA_R {
94        LDMA_R::new(((self.bits >> 5) & 1) != 0)
95    }
96    #[doc = "Bit 6 - General Purpose CRC Clock Enable"]
97    #[inline(always)]
98    pub fn gpcrc(&self) -> GPCRC_R {
99        GPCRC_R::new(((self.bits >> 6) & 1) != 0)
100    }
101}
102impl W {
103    #[doc = "Bit 0 - Advanced Encryption Standard Accelerator 0 Clock Enable"]
104    #[inline(always)]
105    #[must_use]
106    pub fn crypto0(&mut self) -> CRYPTO0_W<0> {
107        CRYPTO0_W::new(self)
108    }
109    #[doc = "Bit 1 - Advanced Encryption Standard Accelerator 1 Clock Enable"]
110    #[inline(always)]
111    #[must_use]
112    pub fn crypto1(&mut self) -> CRYPTO1_W<1> {
113        CRYPTO1_W::new(self)
114    }
115    #[doc = "Bit 2 - Low Energy Peripheral Interface Clock Enable"]
116    #[inline(always)]
117    #[must_use]
118    pub fn le(&mut self) -> LE_W<2> {
119        LE_W::new(self)
120    }
121    #[doc = "Bit 3 - General purpose Input/Output Clock Enable"]
122    #[inline(always)]
123    #[must_use]
124    pub fn gpio(&mut self) -> GPIO_W<3> {
125        GPIO_W::new(self)
126    }
127    #[doc = "Bit 4 - Peripheral Reflex System Clock Enable"]
128    #[inline(always)]
129    #[must_use]
130    pub fn prs(&mut self) -> PRS_W<4> {
131        PRS_W::new(self)
132    }
133    #[doc = "Bit 5 - Linked Direct Memory Access Controller Clock Enable"]
134    #[inline(always)]
135    #[must_use]
136    pub fn ldma(&mut self) -> LDMA_W<5> {
137        LDMA_W::new(self)
138    }
139    #[doc = "Bit 6 - General Purpose CRC Clock Enable"]
140    #[inline(always)]
141    #[must_use]
142    pub fn gpcrc(&mut self) -> GPCRC_W<6> {
143        GPCRC_W::new(self)
144    }
145    #[doc = "Writes raw bits to the register."]
146    #[inline(always)]
147    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
148        self.0.bits(bits);
149        self
150    }
151}
152#[doc = "High Frequency Bus Clock Enable Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfbusclken0](index.html) module"]
153pub struct HFBUSCLKEN0_SPEC;
154impl crate::RegisterSpec for HFBUSCLKEN0_SPEC {
155    type Ux = u32;
156}
157#[doc = "`read()` method returns [hfbusclken0::R](R) reader structure"]
158impl crate::Readable for HFBUSCLKEN0_SPEC {
159    type Reader = R;
160}
161#[doc = "`write(|w| ..)` method takes [hfbusclken0::W](W) writer structure"]
162impl crate::Writable for HFBUSCLKEN0_SPEC {
163    type Writer = W;
164    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
165    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
166}
167#[doc = "`reset()` method sets HFBUSCLKEN0 to value 0"]
168impl crate::Resettable for HFBUSCLKEN0_SPEC {
169    const RESET_VALUE: Self::Ux = 0;
170}
efm32jg12b_pac/efm32jg12b500/cmu/hfbusclken0.rs

efm32jg12b_pac/efm32jg12b500/cmu/
hfbusclken0.rs
