efm32jg12b_pac/efm32jg12b500/adc0/
singlectrlx.rs

1#[doc = "Register `SINGLECTRLX` reader"]
2pub struct R(crate::R<SINGLECTRLX_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SINGLECTRLX_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SINGLECTRLX_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SINGLECTRLX_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `SINGLECTRLX` writer"]
17pub struct W(crate::W<SINGLECTRLX_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<SINGLECTRLX_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<SINGLECTRLX_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<SINGLECTRLX_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `VREFSEL` reader - Single Channel Reference Selection"]
38pub type VREFSEL_R = crate::FieldReader<u8, VREFSEL_A>;
39#[doc = "Single Channel Reference Selection\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum VREFSEL_A {
43    #[doc = "0: Internal 0.83V Bandgap reference"]
44    VBGR = 0,
45    #[doc = "1: Scaled AVDD: AVDD*(the VREF attenuation factor)"]
46    VDDXWATT = 1,
47    #[doc = "2: Scaled singled ended external Vref: ADCn_EXTP*(the VREF attenuation factor)"]
48    VREFPWATT = 2,
49    #[doc = "3: Raw single ended external Vref: ADCn_EXTP"]
50    VREFP = 3,
51    #[doc = "4: Special mode used to generate ENTROPY."]
52    VENTROPY = 4,
53    #[doc = "5: Scaled differential external Vref from : (ADCn_EXTP-ADCn_EXTN)*(the VREF attenuation factor)"]
54    VREFPNWATT = 5,
55    #[doc = "6: Raw differential external Vref from : (ADCn_EXTP-ADCn_EXTN)"]
56    VREFPN = 6,
57    #[doc = "7: Internal Bandgap reference at low setting 0.78V"]
58    VBGRLOW = 7,
59}
60impl From<VREFSEL_A> for u8 {
61    #[inline(always)]
62    fn from(variant: VREFSEL_A) -> Self {
63        variant as _
64    }
65}
66impl VREFSEL_R {
67    #[doc = "Get enumerated values variant"]
68    #[inline(always)]
69    pub fn variant(&self) -> VREFSEL_A {
70        match self.bits {
71            0 => VREFSEL_A::VBGR,
72            1 => VREFSEL_A::VDDXWATT,
73            2 => VREFSEL_A::VREFPWATT,
74            3 => VREFSEL_A::VREFP,
75            4 => VREFSEL_A::VENTROPY,
76            5 => VREFSEL_A::VREFPNWATT,
77            6 => VREFSEL_A::VREFPN,
78            7 => VREFSEL_A::VBGRLOW,
79            _ => unreachable!(),
80        }
81    }
82    #[doc = "Checks if the value of the field is `VBGR`"]
83    #[inline(always)]
84    pub fn is_vbgr(&self) -> bool {
85        *self == VREFSEL_A::VBGR
86    }
87    #[doc = "Checks if the value of the field is `VDDXWATT`"]
88    #[inline(always)]
89    pub fn is_vddxwatt(&self) -> bool {
90        *self == VREFSEL_A::VDDXWATT
91    }
92    #[doc = "Checks if the value of the field is `VREFPWATT`"]
93    #[inline(always)]
94    pub fn is_vrefpwatt(&self) -> bool {
95        *self == VREFSEL_A::VREFPWATT
96    }
97    #[doc = "Checks if the value of the field is `VREFP`"]
98    #[inline(always)]
99    pub fn is_vrefp(&self) -> bool {
100        *self == VREFSEL_A::VREFP
101    }
102    #[doc = "Checks if the value of the field is `VENTROPY`"]
103    #[inline(always)]
104    pub fn is_ventropy(&self) -> bool {
105        *self == VREFSEL_A::VENTROPY
106    }
107    #[doc = "Checks if the value of the field is `VREFPNWATT`"]
108    #[inline(always)]
109    pub fn is_vrefpnwatt(&self) -> bool {
110        *self == VREFSEL_A::VREFPNWATT
111    }
112    #[doc = "Checks if the value of the field is `VREFPN`"]
113    #[inline(always)]
114    pub fn is_vrefpn(&self) -> bool {
115        *self == VREFSEL_A::VREFPN
116    }
117    #[doc = "Checks if the value of the field is `VBGRLOW`"]
118    #[inline(always)]
119    pub fn is_vbgrlow(&self) -> bool {
120        *self == VREFSEL_A::VBGRLOW
121    }
122}
123#[doc = "Field `VREFSEL` writer - Single Channel Reference Selection"]
124pub type VREFSEL_W<'a, const O: u8> =
125    crate::FieldWriterSafe<'a, u32, SINGLECTRLX_SPEC, u8, VREFSEL_A, 3, O>;
126impl<'a, const O: u8> VREFSEL_W<'a, O> {
127    #[doc = "Internal 0.83V Bandgap reference"]
128    #[inline(always)]
129    pub fn vbgr(self) -> &'a mut W {
130        self.variant(VREFSEL_A::VBGR)
131    }
132    #[doc = "Scaled AVDD: AVDD*(the VREF attenuation factor)"]
133    #[inline(always)]
134    pub fn vddxwatt(self) -> &'a mut W {
135        self.variant(VREFSEL_A::VDDXWATT)
136    }
137    #[doc = "Scaled singled ended external Vref: ADCn_EXTP*(the VREF attenuation factor)"]
138    #[inline(always)]
139    pub fn vrefpwatt(self) -> &'a mut W {
140        self.variant(VREFSEL_A::VREFPWATT)
141    }
142    #[doc = "Raw single ended external Vref: ADCn_EXTP"]
143    #[inline(always)]
144    pub fn vrefp(self) -> &'a mut W {
145        self.variant(VREFSEL_A::VREFP)
146    }
147    #[doc = "Special mode used to generate ENTROPY."]
148    #[inline(always)]
149    pub fn ventropy(self) -> &'a mut W {
150        self.variant(VREFSEL_A::VENTROPY)
151    }
152    #[doc = "Scaled differential external Vref from : (ADCn_EXTP-ADCn_EXTN)*(the VREF attenuation factor)"]
153    #[inline(always)]
154    pub fn vrefpnwatt(self) -> &'a mut W {
155        self.variant(VREFSEL_A::VREFPNWATT)
156    }
157    #[doc = "Raw differential external Vref from : (ADCn_EXTP-ADCn_EXTN)"]
158    #[inline(always)]
159    pub fn vrefpn(self) -> &'a mut W {
160        self.variant(VREFSEL_A::VREFPN)
161    }
162    #[doc = "Internal Bandgap reference at low setting 0.78V"]
163    #[inline(always)]
164    pub fn vbgrlow(self) -> &'a mut W {
165        self.variant(VREFSEL_A::VBGRLOW)
166    }
167}
168#[doc = "Field `VREFATTFIX` reader - Enable Fixed Scaling on VREF"]
169pub type VREFATTFIX_R = crate::BitReader<bool>;
170#[doc = "Field `VREFATTFIX` writer - Enable Fixed Scaling on VREF"]
171pub type VREFATTFIX_W<'a, const O: u8> = crate::BitWriter<'a, u32, SINGLECTRLX_SPEC, bool, O>;
172#[doc = "Field `VREFATT` reader - Code for VREF Attenuation Factor When VREFSEL is 1, 2 or 5"]
173pub type VREFATT_R = crate::FieldReader<u8, u8>;
174#[doc = "Field `VREFATT` writer - Code for VREF Attenuation Factor When VREFSEL is 1, 2 or 5"]
175pub type VREFATT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SINGLECTRLX_SPEC, u8, u8, 4, O>;
176#[doc = "Field `VINATT` reader - Code for VIN Attenuation Factor"]
177pub type VINATT_R = crate::FieldReader<u8, u8>;
178#[doc = "Field `VINATT` writer - Code for VIN Attenuation Factor"]
179pub type VINATT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SINGLECTRLX_SPEC, u8, u8, 4, O>;
180#[doc = "Field `DVL` reader - Single Channel DV Level Select"]
181pub type DVL_R = crate::FieldReader<u8, u8>;
182#[doc = "Field `DVL` writer - Single Channel DV Level Select"]
183pub type DVL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SINGLECTRLX_SPEC, u8, u8, 2, O>;
184#[doc = "Field `FIFOOFACT` reader - Single Channel FIFO Overflow Action"]
185pub type FIFOOFACT_R = crate::BitReader<bool>;
186#[doc = "Field `FIFOOFACT` writer - Single Channel FIFO Overflow Action"]
187pub type FIFOOFACT_W<'a, const O: u8> = crate::BitWriter<'a, u32, SINGLECTRLX_SPEC, bool, O>;
188#[doc = "Field `PRSMODE` reader - Single Channel PRS Trigger Mode"]
189pub type PRSMODE_R = crate::BitReader<bool>;
190#[doc = "Field `PRSMODE` writer - Single Channel PRS Trigger Mode"]
191pub type PRSMODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, SINGLECTRLX_SPEC, bool, O>;
192#[doc = "Field `PRSSEL` reader - Single Channel PRS Trigger Select"]
193pub type PRSSEL_R = crate::FieldReader<u8, PRSSEL_A>;
194#[doc = "Single Channel PRS Trigger Select\n\nValue on reset: 0"]
195#[derive(Clone, Copy, Debug, PartialEq, Eq)]
196#[repr(u8)]
197pub enum PRSSEL_A {
198    #[doc = "0: PRS ch 0 triggers single channel"]
199    PRSCH0 = 0,
200    #[doc = "1: PRS ch 1 triggers single channel"]
201    PRSCH1 = 1,
202    #[doc = "2: PRS ch 2 triggers single channel"]
203    PRSCH2 = 2,
204    #[doc = "3: PRS ch 3 triggers single channel"]
205    PRSCH3 = 3,
206    #[doc = "4: PRS ch 4 triggers single channel"]
207    PRSCH4 = 4,
208    #[doc = "5: PRS ch 5 triggers single channel"]
209    PRSCH5 = 5,
210    #[doc = "6: PRS ch 6 triggers single channel"]
211    PRSCH6 = 6,
212    #[doc = "7: PRS ch 7 triggers single channel"]
213    PRSCH7 = 7,
214    #[doc = "8: PRS ch 8 triggers single channel"]
215    PRSCH8 = 8,
216    #[doc = "9: PRS ch 9 triggers single channel"]
217    PRSCH9 = 9,
218    #[doc = "10: PRS ch 10 triggers single channel"]
219    PRSCH10 = 10,
220    #[doc = "11: PRS ch 11 triggers single channel"]
221    PRSCH11 = 11,
222}
223impl From<PRSSEL_A> for u8 {
224    #[inline(always)]
225    fn from(variant: PRSSEL_A) -> Self {
226        variant as _
227    }
228}
229impl PRSSEL_R {
230    #[doc = "Get enumerated values variant"]
231    #[inline(always)]
232    pub fn variant(&self) -> Option<PRSSEL_A> {
233        match self.bits {
234            0 => Some(PRSSEL_A::PRSCH0),
235            1 => Some(PRSSEL_A::PRSCH1),
236            2 => Some(PRSSEL_A::PRSCH2),
237            3 => Some(PRSSEL_A::PRSCH3),
238            4 => Some(PRSSEL_A::PRSCH4),
239            5 => Some(PRSSEL_A::PRSCH5),
240            6 => Some(PRSSEL_A::PRSCH6),
241            7 => Some(PRSSEL_A::PRSCH7),
242            8 => Some(PRSSEL_A::PRSCH8),
243            9 => Some(PRSSEL_A::PRSCH9),
244            10 => Some(PRSSEL_A::PRSCH10),
245            11 => Some(PRSSEL_A::PRSCH11),
246            _ => None,
247        }
248    }
249    #[doc = "Checks if the value of the field is `PRSCH0`"]
250    #[inline(always)]
251    pub fn is_prsch0(&self) -> bool {
252        *self == PRSSEL_A::PRSCH0
253    }
254    #[doc = "Checks if the value of the field is `PRSCH1`"]
255    #[inline(always)]
256    pub fn is_prsch1(&self) -> bool {
257        *self == PRSSEL_A::PRSCH1
258    }
259    #[doc = "Checks if the value of the field is `PRSCH2`"]
260    #[inline(always)]
261    pub fn is_prsch2(&self) -> bool {
262        *self == PRSSEL_A::PRSCH2
263    }
264    #[doc = "Checks if the value of the field is `PRSCH3`"]
265    #[inline(always)]
266    pub fn is_prsch3(&self) -> bool {
267        *self == PRSSEL_A::PRSCH3
268    }
269    #[doc = "Checks if the value of the field is `PRSCH4`"]
270    #[inline(always)]
271    pub fn is_prsch4(&self) -> bool {
272        *self == PRSSEL_A::PRSCH4
273    }
274    #[doc = "Checks if the value of the field is `PRSCH5`"]
275    #[inline(always)]
276    pub fn is_prsch5(&self) -> bool {
277        *self == PRSSEL_A::PRSCH5
278    }
279    #[doc = "Checks if the value of the field is `PRSCH6`"]
280    #[inline(always)]
281    pub fn is_prsch6(&self) -> bool {
282        *self == PRSSEL_A::PRSCH6
283    }
284    #[doc = "Checks if the value of the field is `PRSCH7`"]
285    #[inline(always)]
286    pub fn is_prsch7(&self) -> bool {
287        *self == PRSSEL_A::PRSCH7
288    }
289    #[doc = "Checks if the value of the field is `PRSCH8`"]
290    #[inline(always)]
291    pub fn is_prsch8(&self) -> bool {
292        *self == PRSSEL_A::PRSCH8
293    }
294    #[doc = "Checks if the value of the field is `PRSCH9`"]
295    #[inline(always)]
296    pub fn is_prsch9(&self) -> bool {
297        *self == PRSSEL_A::PRSCH9
298    }
299    #[doc = "Checks if the value of the field is `PRSCH10`"]
300    #[inline(always)]
301    pub fn is_prsch10(&self) -> bool {
302        *self == PRSSEL_A::PRSCH10
303    }
304    #[doc = "Checks if the value of the field is `PRSCH11`"]
305    #[inline(always)]
306    pub fn is_prsch11(&self) -> bool {
307        *self == PRSSEL_A::PRSCH11
308    }
309}
310#[doc = "Field `PRSSEL` writer - Single Channel PRS Trigger Select"]
311pub type PRSSEL_W<'a, const O: u8> =
312    crate::FieldWriter<'a, u32, SINGLECTRLX_SPEC, u8, PRSSEL_A, 4, O>;
313impl<'a, const O: u8> PRSSEL_W<'a, O> {
314    #[doc = "PRS ch 0 triggers single channel"]
315    #[inline(always)]
316    pub fn prsch0(self) -> &'a mut W {
317        self.variant(PRSSEL_A::PRSCH0)
318    }
319    #[doc = "PRS ch 1 triggers single channel"]
320    #[inline(always)]
321    pub fn prsch1(self) -> &'a mut W {
322        self.variant(PRSSEL_A::PRSCH1)
323    }
324    #[doc = "PRS ch 2 triggers single channel"]
325    #[inline(always)]
326    pub fn prsch2(self) -> &'a mut W {
327        self.variant(PRSSEL_A::PRSCH2)
328    }
329    #[doc = "PRS ch 3 triggers single channel"]
330    #[inline(always)]
331    pub fn prsch3(self) -> &'a mut W {
332        self.variant(PRSSEL_A::PRSCH3)
333    }
334    #[doc = "PRS ch 4 triggers single channel"]
335    #[inline(always)]
336    pub fn prsch4(self) -> &'a mut W {
337        self.variant(PRSSEL_A::PRSCH4)
338    }
339    #[doc = "PRS ch 5 triggers single channel"]
340    #[inline(always)]
341    pub fn prsch5(self) -> &'a mut W {
342        self.variant(PRSSEL_A::PRSCH5)
343    }
344    #[doc = "PRS ch 6 triggers single channel"]
345    #[inline(always)]
346    pub fn prsch6(self) -> &'a mut W {
347        self.variant(PRSSEL_A::PRSCH6)
348    }
349    #[doc = "PRS ch 7 triggers single channel"]
350    #[inline(always)]
351    pub fn prsch7(self) -> &'a mut W {
352        self.variant(PRSSEL_A::PRSCH7)
353    }
354    #[doc = "PRS ch 8 triggers single channel"]
355    #[inline(always)]
356    pub fn prsch8(self) -> &'a mut W {
357        self.variant(PRSSEL_A::PRSCH8)
358    }
359    #[doc = "PRS ch 9 triggers single channel"]
360    #[inline(always)]
361    pub fn prsch9(self) -> &'a mut W {
362        self.variant(PRSSEL_A::PRSCH9)
363    }
364    #[doc = "PRS ch 10 triggers single channel"]
365    #[inline(always)]
366    pub fn prsch10(self) -> &'a mut W {
367        self.variant(PRSSEL_A::PRSCH10)
368    }
369    #[doc = "PRS ch 11 triggers single channel"]
370    #[inline(always)]
371    pub fn prsch11(self) -> &'a mut W {
372        self.variant(PRSSEL_A::PRSCH11)
373    }
374}
375#[doc = "Field `CONVSTARTDELAY` reader - Delay Value for Next Conversion Start If CONVSTARTDELAYEN is Set"]
376pub type CONVSTARTDELAY_R = crate::FieldReader<u8, u8>;
377#[doc = "Field `CONVSTARTDELAY` writer - Delay Value for Next Conversion Start If CONVSTARTDELAYEN is Set"]
378pub type CONVSTARTDELAY_W<'a, const O: u8> =
379    crate::FieldWriter<'a, u32, SINGLECTRLX_SPEC, u8, u8, 5, O>;
380#[doc = "Field `CONVSTARTDELAYEN` reader - Enable Delaying Next Conversion Start"]
381pub type CONVSTARTDELAYEN_R = crate::BitReader<bool>;
382#[doc = "Field `CONVSTARTDELAYEN` writer - Enable Delaying Next Conversion Start"]
383pub type CONVSTARTDELAYEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SINGLECTRLX_SPEC, bool, O>;
384#[doc = "Field `REPDELAY` reader - REPDELAY Select for SINGLE REP Mode"]
385pub type REPDELAY_R = crate::FieldReader<u8, REPDELAY_A>;
386#[doc = "REPDELAY Select for SINGLE REP Mode\n\nValue on reset: 0"]
387#[derive(Clone, Copy, Debug, PartialEq, Eq)]
388#[repr(u8)]
389pub enum REPDELAY_A {
390    #[doc = "0: No delay"]
391    NODELAY = 0,
392    #[doc = "1: 4 conversion clock cycles"]
393    _4CYCLES = 1,
394    #[doc = "2: 8 conversion clock cycles"]
395    _8CYCLES = 2,
396    #[doc = "3: 16 conversion clock cycles"]
397    _16CYCLES = 3,
398    #[doc = "4: 32 conversion clock cycles"]
399    _32CYCLES = 4,
400    #[doc = "5: 64 conversion clock cycles"]
401    _64CYCLES = 5,
402    #[doc = "6: 128 conversion clock cycles"]
403    _128CYCLES = 6,
404    #[doc = "7: 256 conversion clock cycles"]
405    _256CYCLES = 7,
406}
407impl From<REPDELAY_A> for u8 {
408    #[inline(always)]
409    fn from(variant: REPDELAY_A) -> Self {
410        variant as _
411    }
412}
413impl REPDELAY_R {
414    #[doc = "Get enumerated values variant"]
415    #[inline(always)]
416    pub fn variant(&self) -> REPDELAY_A {
417        match self.bits {
418            0 => REPDELAY_A::NODELAY,
419            1 => REPDELAY_A::_4CYCLES,
420            2 => REPDELAY_A::_8CYCLES,
421            3 => REPDELAY_A::_16CYCLES,
422            4 => REPDELAY_A::_32CYCLES,
423            5 => REPDELAY_A::_64CYCLES,
424            6 => REPDELAY_A::_128CYCLES,
425            7 => REPDELAY_A::_256CYCLES,
426            _ => unreachable!(),
427        }
428    }
429    #[doc = "Checks if the value of the field is `NODELAY`"]
430    #[inline(always)]
431    pub fn is_nodelay(&self) -> bool {
432        *self == REPDELAY_A::NODELAY
433    }
434    #[doc = "Checks if the value of the field is `_4CYCLES`"]
435    #[inline(always)]
436    pub fn is_4cycles(&self) -> bool {
437        *self == REPDELAY_A::_4CYCLES
438    }
439    #[doc = "Checks if the value of the field is `_8CYCLES`"]
440    #[inline(always)]
441    pub fn is_8cycles(&self) -> bool {
442        *self == REPDELAY_A::_8CYCLES
443    }
444    #[doc = "Checks if the value of the field is `_16CYCLES`"]
445    #[inline(always)]
446    pub fn is_16cycles(&self) -> bool {
447        *self == REPDELAY_A::_16CYCLES
448    }
449    #[doc = "Checks if the value of the field is `_32CYCLES`"]
450    #[inline(always)]
451    pub fn is_32cycles(&self) -> bool {
452        *self == REPDELAY_A::_32CYCLES
453    }
454    #[doc = "Checks if the value of the field is `_64CYCLES`"]
455    #[inline(always)]
456    pub fn is_64cycles(&self) -> bool {
457        *self == REPDELAY_A::_64CYCLES
458    }
459    #[doc = "Checks if the value of the field is `_128CYCLES`"]
460    #[inline(always)]
461    pub fn is_128cycles(&self) -> bool {
462        *self == REPDELAY_A::_128CYCLES
463    }
464    #[doc = "Checks if the value of the field is `_256CYCLES`"]
465    #[inline(always)]
466    pub fn is_256cycles(&self) -> bool {
467        *self == REPDELAY_A::_256CYCLES
468    }
469}
470#[doc = "Field `REPDELAY` writer - REPDELAY Select for SINGLE REP Mode"]
471pub type REPDELAY_W<'a, const O: u8> =
472    crate::FieldWriterSafe<'a, u32, SINGLECTRLX_SPEC, u8, REPDELAY_A, 3, O>;
473impl<'a, const O: u8> REPDELAY_W<'a, O> {
474    #[doc = "No delay"]
475    #[inline(always)]
476    pub fn nodelay(self) -> &'a mut W {
477        self.variant(REPDELAY_A::NODELAY)
478    }
479    #[doc = "4 conversion clock cycles"]
480    #[inline(always)]
481    pub fn _4cycles(self) -> &'a mut W {
482        self.variant(REPDELAY_A::_4CYCLES)
483    }
484    #[doc = "8 conversion clock cycles"]
485    #[inline(always)]
486    pub fn _8cycles(self) -> &'a mut W {
487        self.variant(REPDELAY_A::_8CYCLES)
488    }
489    #[doc = "16 conversion clock cycles"]
490    #[inline(always)]
491    pub fn _16cycles(self) -> &'a mut W {
492        self.variant(REPDELAY_A::_16CYCLES)
493    }
494    #[doc = "32 conversion clock cycles"]
495    #[inline(always)]
496    pub fn _32cycles(self) -> &'a mut W {
497        self.variant(REPDELAY_A::_32CYCLES)
498    }
499    #[doc = "64 conversion clock cycles"]
500    #[inline(always)]
501    pub fn _64cycles(self) -> &'a mut W {
502        self.variant(REPDELAY_A::_64CYCLES)
503    }
504    #[doc = "128 conversion clock cycles"]
505    #[inline(always)]
506    pub fn _128cycles(self) -> &'a mut W {
507        self.variant(REPDELAY_A::_128CYCLES)
508    }
509    #[doc = "256 conversion clock cycles"]
510    #[inline(always)]
511    pub fn _256cycles(self) -> &'a mut W {
512        self.variant(REPDELAY_A::_256CYCLES)
513    }
514}
515impl R {
516    #[doc = "Bits 0:2 - Single Channel Reference Selection"]
517    #[inline(always)]
518    pub fn vrefsel(&self) -> VREFSEL_R {
519        VREFSEL_R::new((self.bits & 7) as u8)
520    }
521    #[doc = "Bit 3 - Enable Fixed Scaling on VREF"]
522    #[inline(always)]
523    pub fn vrefattfix(&self) -> VREFATTFIX_R {
524        VREFATTFIX_R::new(((self.bits >> 3) & 1) != 0)
525    }
526    #[doc = "Bits 4:7 - Code for VREF Attenuation Factor When VREFSEL is 1, 2 or 5"]
527    #[inline(always)]
528    pub fn vrefatt(&self) -> VREFATT_R {
529        VREFATT_R::new(((self.bits >> 4) & 0x0f) as u8)
530    }
531    #[doc = "Bits 8:11 - Code for VIN Attenuation Factor"]
532    #[inline(always)]
533    pub fn vinatt(&self) -> VINATT_R {
534        VINATT_R::new(((self.bits >> 8) & 0x0f) as u8)
535    }
536    #[doc = "Bits 12:13 - Single Channel DV Level Select"]
537    #[inline(always)]
538    pub fn dvl(&self) -> DVL_R {
539        DVL_R::new(((self.bits >> 12) & 3) as u8)
540    }
541    #[doc = "Bit 14 - Single Channel FIFO Overflow Action"]
542    #[inline(always)]
543    pub fn fifoofact(&self) -> FIFOOFACT_R {
544        FIFOOFACT_R::new(((self.bits >> 14) & 1) != 0)
545    }
546    #[doc = "Bit 16 - Single Channel PRS Trigger Mode"]
547    #[inline(always)]
548    pub fn prsmode(&self) -> PRSMODE_R {
549        PRSMODE_R::new(((self.bits >> 16) & 1) != 0)
550    }
551    #[doc = "Bits 17:20 - Single Channel PRS Trigger Select"]
552    #[inline(always)]
553    pub fn prssel(&self) -> PRSSEL_R {
554        PRSSEL_R::new(((self.bits >> 17) & 0x0f) as u8)
555    }
556    #[doc = "Bits 22:26 - Delay Value for Next Conversion Start If CONVSTARTDELAYEN is Set"]
557    #[inline(always)]
558    pub fn convstartdelay(&self) -> CONVSTARTDELAY_R {
559        CONVSTARTDELAY_R::new(((self.bits >> 22) & 0x1f) as u8)
560    }
561    #[doc = "Bit 27 - Enable Delaying Next Conversion Start"]
562    #[inline(always)]
563    pub fn convstartdelayen(&self) -> CONVSTARTDELAYEN_R {
564        CONVSTARTDELAYEN_R::new(((self.bits >> 27) & 1) != 0)
565    }
566    #[doc = "Bits 29:31 - REPDELAY Select for SINGLE REP Mode"]
567    #[inline(always)]
568    pub fn repdelay(&self) -> REPDELAY_R {
569        REPDELAY_R::new(((self.bits >> 29) & 7) as u8)
570    }
571}
572impl W {
573    #[doc = "Bits 0:2 - Single Channel Reference Selection"]
574    #[inline(always)]
575    #[must_use]
576    pub fn vrefsel(&mut self) -> VREFSEL_W<0> {
577        VREFSEL_W::new(self)
578    }
579    #[doc = "Bit 3 - Enable Fixed Scaling on VREF"]
580    #[inline(always)]
581    #[must_use]
582    pub fn vrefattfix(&mut self) -> VREFATTFIX_W<3> {
583        VREFATTFIX_W::new(self)
584    }
585    #[doc = "Bits 4:7 - Code for VREF Attenuation Factor When VREFSEL is 1, 2 or 5"]
586    #[inline(always)]
587    #[must_use]
588    pub fn vrefatt(&mut self) -> VREFATT_W<4> {
589        VREFATT_W::new(self)
590    }
591    #[doc = "Bits 8:11 - Code for VIN Attenuation Factor"]
592    #[inline(always)]
593    #[must_use]
594    pub fn vinatt(&mut self) -> VINATT_W<8> {
595        VINATT_W::new(self)
596    }
597    #[doc = "Bits 12:13 - Single Channel DV Level Select"]
598    #[inline(always)]
599    #[must_use]
600    pub fn dvl(&mut self) -> DVL_W<12> {
601        DVL_W::new(self)
602    }
603    #[doc = "Bit 14 - Single Channel FIFO Overflow Action"]
604    #[inline(always)]
605    #[must_use]
606    pub fn fifoofact(&mut self) -> FIFOOFACT_W<14> {
607        FIFOOFACT_W::new(self)
608    }
609    #[doc = "Bit 16 - Single Channel PRS Trigger Mode"]
610    #[inline(always)]
611    #[must_use]
612    pub fn prsmode(&mut self) -> PRSMODE_W<16> {
613        PRSMODE_W::new(self)
614    }
615    #[doc = "Bits 17:20 - Single Channel PRS Trigger Select"]
616    #[inline(always)]
617    #[must_use]
618    pub fn prssel(&mut self) -> PRSSEL_W<17> {
619        PRSSEL_W::new(self)
620    }
621    #[doc = "Bits 22:26 - Delay Value for Next Conversion Start If CONVSTARTDELAYEN is Set"]
622    #[inline(always)]
623    #[must_use]
624    pub fn convstartdelay(&mut self) -> CONVSTARTDELAY_W<22> {
625        CONVSTARTDELAY_W::new(self)
626    }
627    #[doc = "Bit 27 - Enable Delaying Next Conversion Start"]
628    #[inline(always)]
629    #[must_use]
630    pub fn convstartdelayen(&mut self) -> CONVSTARTDELAYEN_W<27> {
631        CONVSTARTDELAYEN_W::new(self)
632    }
633    #[doc = "Bits 29:31 - REPDELAY Select for SINGLE REP Mode"]
634    #[inline(always)]
635    #[must_use]
636    pub fn repdelay(&mut self) -> REPDELAY_W<29> {
637        REPDELAY_W::new(self)
638    }
639    #[doc = "Writes raw bits to the register."]
640    #[inline(always)]
641    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
642        self.0.bits(bits);
643        self
644    }
645}
646#[doc = "Single Channel Control Register Continued\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [singlectrlx](index.html) module"]
647pub struct SINGLECTRLX_SPEC;
648impl crate::RegisterSpec for SINGLECTRLX_SPEC {
649    type Ux = u32;
650}
651#[doc = "`read()` method returns [singlectrlx::R](R) reader structure"]
652impl crate::Readable for SINGLECTRLX_SPEC {
653    type Reader = R;
654}
655#[doc = "`write(|w| ..)` method takes [singlectrlx::W](W) writer structure"]
656impl crate::Writable for SINGLECTRLX_SPEC {
657    type Writer = W;
658    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
659    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
660}
661#[doc = "`reset()` method sets SINGLECTRLX to value 0"]
662impl crate::Resettable for SINGLECTRLX_SPEC {
663    const RESET_VALUE: Self::Ux = 0;
664}
efm32jg12b_pac/efm32jg12b500/adc0/singlectrlx.rs

efm32jg12b_pac/efm32jg12b500/adc0/
singlectrlx.rs
