efm32jg12b_pac/efm32jg12b500/vdac0/
ien.rs

1#[doc = "Register `IEN` reader"]
2pub struct R(crate::R<IEN_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<IEN_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<IEN_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<IEN_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `IEN` writer"]
17pub struct W(crate::W<IEN_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<IEN_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<IEN_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<IEN_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CH0CD` reader - CH0CD Interrupt Enable"]
38pub type CH0CD_R = crate::BitReader<bool>;
39#[doc = "Field `CH0CD` writer - CH0CD Interrupt Enable"]
40pub type CH0CD_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
41#[doc = "Field `CH1CD` reader - CH1CD Interrupt Enable"]
42pub type CH1CD_R = crate::BitReader<bool>;
43#[doc = "Field `CH1CD` writer - CH1CD Interrupt Enable"]
44pub type CH1CD_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
45#[doc = "Field `CH0OF` reader - CH0OF Interrupt Enable"]
46pub type CH0OF_R = crate::BitReader<bool>;
47#[doc = "Field `CH0OF` writer - CH0OF Interrupt Enable"]
48pub type CH0OF_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
49#[doc = "Field `CH1OF` reader - CH1OF Interrupt Enable"]
50pub type CH1OF_R = crate::BitReader<bool>;
51#[doc = "Field `CH1OF` writer - CH1OF Interrupt Enable"]
52pub type CH1OF_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
53#[doc = "Field `CH0UF` reader - CH0UF Interrupt Enable"]
54pub type CH0UF_R = crate::BitReader<bool>;
55#[doc = "Field `CH0UF` writer - CH0UF Interrupt Enable"]
56pub type CH0UF_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
57#[doc = "Field `CH1UF` reader - CH1UF Interrupt Enable"]
58pub type CH1UF_R = crate::BitReader<bool>;
59#[doc = "Field `CH1UF` writer - CH1UF Interrupt Enable"]
60pub type CH1UF_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
61#[doc = "Field `CH0BL` reader - CH0BL Interrupt Enable"]
62pub type CH0BL_R = crate::BitReader<bool>;
63#[doc = "Field `CH0BL` writer - CH0BL Interrupt Enable"]
64pub type CH0BL_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
65#[doc = "Field `CH1BL` reader - CH1BL Interrupt Enable"]
66pub type CH1BL_R = crate::BitReader<bool>;
67#[doc = "Field `CH1BL` writer - CH1BL Interrupt Enable"]
68pub type CH1BL_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
69#[doc = "Field `EM23ERR` reader - EM23ERR Interrupt Enable"]
70pub type EM23ERR_R = crate::BitReader<bool>;
71#[doc = "Field `EM23ERR` writer - EM23ERR Interrupt Enable"]
72pub type EM23ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
73#[doc = "Field `OPA0APORTCONFLICT` reader - OPA0APORTCONFLICT Interrupt Enable"]
74pub type OPA0APORTCONFLICT_R = crate::BitReader<bool>;
75#[doc = "Field `OPA0APORTCONFLICT` writer - OPA0APORTCONFLICT Interrupt Enable"]
76pub type OPA0APORTCONFLICT_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
77#[doc = "Field `OPA1APORTCONFLICT` reader - OPA1APORTCONFLICT Interrupt Enable"]
78pub type OPA1APORTCONFLICT_R = crate::BitReader<bool>;
79#[doc = "Field `OPA1APORTCONFLICT` writer - OPA1APORTCONFLICT Interrupt Enable"]
80pub type OPA1APORTCONFLICT_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
81#[doc = "Field `OPA2APORTCONFLICT` reader - OPA2APORTCONFLICT Interrupt Enable"]
82pub type OPA2APORTCONFLICT_R = crate::BitReader<bool>;
83#[doc = "Field `OPA2APORTCONFLICT` writer - OPA2APORTCONFLICT Interrupt Enable"]
84pub type OPA2APORTCONFLICT_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
85#[doc = "Field `OPA0PRSTIMEDERR` reader - OPA0PRSTIMEDERR Interrupt Enable"]
86pub type OPA0PRSTIMEDERR_R = crate::BitReader<bool>;
87#[doc = "Field `OPA0PRSTIMEDERR` writer - OPA0PRSTIMEDERR Interrupt Enable"]
88pub type OPA0PRSTIMEDERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
89#[doc = "Field `OPA1PRSTIMEDERR` reader - OPA1PRSTIMEDERR Interrupt Enable"]
90pub type OPA1PRSTIMEDERR_R = crate::BitReader<bool>;
91#[doc = "Field `OPA1PRSTIMEDERR` writer - OPA1PRSTIMEDERR Interrupt Enable"]
92pub type OPA1PRSTIMEDERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
93#[doc = "Field `OPA2PRSTIMEDERR` reader - OPA2PRSTIMEDERR Interrupt Enable"]
94pub type OPA2PRSTIMEDERR_R = crate::BitReader<bool>;
95#[doc = "Field `OPA2PRSTIMEDERR` writer - OPA2PRSTIMEDERR Interrupt Enable"]
96pub type OPA2PRSTIMEDERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
97#[doc = "Field `OPA0OUTVALID` reader - OPA0OUTVALID Interrupt Enable"]
98pub type OPA0OUTVALID_R = crate::BitReader<bool>;
99#[doc = "Field `OPA0OUTVALID` writer - OPA0OUTVALID Interrupt Enable"]
100pub type OPA0OUTVALID_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
101#[doc = "Field `OPA1OUTVALID` reader - OPA1OUTVALID Interrupt Enable"]
102pub type OPA1OUTVALID_R = crate::BitReader<bool>;
103#[doc = "Field `OPA1OUTVALID` writer - OPA1OUTVALID Interrupt Enable"]
104pub type OPA1OUTVALID_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
105#[doc = "Field `OPA2OUTVALID` reader - OPA2OUTVALID Interrupt Enable"]
106pub type OPA2OUTVALID_R = crate::BitReader<bool>;
107#[doc = "Field `OPA2OUTVALID` writer - OPA2OUTVALID Interrupt Enable"]
108pub type OPA2OUTVALID_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
109impl R {
110    #[doc = "Bit 0 - CH0CD Interrupt Enable"]
111    #[inline(always)]
112    pub fn ch0cd(&self) -> CH0CD_R {
113        CH0CD_R::new((self.bits & 1) != 0)
114    }
115    #[doc = "Bit 1 - CH1CD Interrupt Enable"]
116    #[inline(always)]
117    pub fn ch1cd(&self) -> CH1CD_R {
118        CH1CD_R::new(((self.bits >> 1) & 1) != 0)
119    }
120    #[doc = "Bit 2 - CH0OF Interrupt Enable"]
121    #[inline(always)]
122    pub fn ch0of(&self) -> CH0OF_R {
123        CH0OF_R::new(((self.bits >> 2) & 1) != 0)
124    }
125    #[doc = "Bit 3 - CH1OF Interrupt Enable"]
126    #[inline(always)]
127    pub fn ch1of(&self) -> CH1OF_R {
128        CH1OF_R::new(((self.bits >> 3) & 1) != 0)
129    }
130    #[doc = "Bit 4 - CH0UF Interrupt Enable"]
131    #[inline(always)]
132    pub fn ch0uf(&self) -> CH0UF_R {
133        CH0UF_R::new(((self.bits >> 4) & 1) != 0)
134    }
135    #[doc = "Bit 5 - CH1UF Interrupt Enable"]
136    #[inline(always)]
137    pub fn ch1uf(&self) -> CH1UF_R {
138        CH1UF_R::new(((self.bits >> 5) & 1) != 0)
139    }
140    #[doc = "Bit 6 - CH0BL Interrupt Enable"]
141    #[inline(always)]
142    pub fn ch0bl(&self) -> CH0BL_R {
143        CH0BL_R::new(((self.bits >> 6) & 1) != 0)
144    }
145    #[doc = "Bit 7 - CH1BL Interrupt Enable"]
146    #[inline(always)]
147    pub fn ch1bl(&self) -> CH1BL_R {
148        CH1BL_R::new(((self.bits >> 7) & 1) != 0)
149    }
150    #[doc = "Bit 15 - EM23ERR Interrupt Enable"]
151    #[inline(always)]
152    pub fn em23err(&self) -> EM23ERR_R {
153        EM23ERR_R::new(((self.bits >> 15) & 1) != 0)
154    }
155    #[doc = "Bit 16 - OPA0APORTCONFLICT Interrupt Enable"]
156    #[inline(always)]
157    pub fn opa0aportconflict(&self) -> OPA0APORTCONFLICT_R {
158        OPA0APORTCONFLICT_R::new(((self.bits >> 16) & 1) != 0)
159    }
160    #[doc = "Bit 17 - OPA1APORTCONFLICT Interrupt Enable"]
161    #[inline(always)]
162    pub fn opa1aportconflict(&self) -> OPA1APORTCONFLICT_R {
163        OPA1APORTCONFLICT_R::new(((self.bits >> 17) & 1) != 0)
164    }
165    #[doc = "Bit 18 - OPA2APORTCONFLICT Interrupt Enable"]
166    #[inline(always)]
167    pub fn opa2aportconflict(&self) -> OPA2APORTCONFLICT_R {
168        OPA2APORTCONFLICT_R::new(((self.bits >> 18) & 1) != 0)
169    }
170    #[doc = "Bit 20 - OPA0PRSTIMEDERR Interrupt Enable"]
171    #[inline(always)]
172    pub fn opa0prstimederr(&self) -> OPA0PRSTIMEDERR_R {
173        OPA0PRSTIMEDERR_R::new(((self.bits >> 20) & 1) != 0)
174    }
175    #[doc = "Bit 21 - OPA1PRSTIMEDERR Interrupt Enable"]
176    #[inline(always)]
177    pub fn opa1prstimederr(&self) -> OPA1PRSTIMEDERR_R {
178        OPA1PRSTIMEDERR_R::new(((self.bits >> 21) & 1) != 0)
179    }
180    #[doc = "Bit 22 - OPA2PRSTIMEDERR Interrupt Enable"]
181    #[inline(always)]
182    pub fn opa2prstimederr(&self) -> OPA2PRSTIMEDERR_R {
183        OPA2PRSTIMEDERR_R::new(((self.bits >> 22) & 1) != 0)
184    }
185    #[doc = "Bit 28 - OPA0OUTVALID Interrupt Enable"]
186    #[inline(always)]
187    pub fn opa0outvalid(&self) -> OPA0OUTVALID_R {
188        OPA0OUTVALID_R::new(((self.bits >> 28) & 1) != 0)
189    }
190    #[doc = "Bit 29 - OPA1OUTVALID Interrupt Enable"]
191    #[inline(always)]
192    pub fn opa1outvalid(&self) -> OPA1OUTVALID_R {
193        OPA1OUTVALID_R::new(((self.bits >> 29) & 1) != 0)
194    }
195    #[doc = "Bit 30 - OPA2OUTVALID Interrupt Enable"]
196    #[inline(always)]
197    pub fn opa2outvalid(&self) -> OPA2OUTVALID_R {
198        OPA2OUTVALID_R::new(((self.bits >> 30) & 1) != 0)
199    }
200}
201impl W {
202    #[doc = "Bit 0 - CH0CD Interrupt Enable"]
203    #[inline(always)]
204    #[must_use]
205    pub fn ch0cd(&mut self) -> CH0CD_W<0> {
206        CH0CD_W::new(self)
207    }
208    #[doc = "Bit 1 - CH1CD Interrupt Enable"]
209    #[inline(always)]
210    #[must_use]
211    pub fn ch1cd(&mut self) -> CH1CD_W<1> {
212        CH1CD_W::new(self)
213    }
214    #[doc = "Bit 2 - CH0OF Interrupt Enable"]
215    #[inline(always)]
216    #[must_use]
217    pub fn ch0of(&mut self) -> CH0OF_W<2> {
218        CH0OF_W::new(self)
219    }
220    #[doc = "Bit 3 - CH1OF Interrupt Enable"]
221    #[inline(always)]
222    #[must_use]
223    pub fn ch1of(&mut self) -> CH1OF_W<3> {
224        CH1OF_W::new(self)
225    }
226    #[doc = "Bit 4 - CH0UF Interrupt Enable"]
227    #[inline(always)]
228    #[must_use]
229    pub fn ch0uf(&mut self) -> CH0UF_W<4> {
230        CH0UF_W::new(self)
231    }
232    #[doc = "Bit 5 - CH1UF Interrupt Enable"]
233    #[inline(always)]
234    #[must_use]
235    pub fn ch1uf(&mut self) -> CH1UF_W<5> {
236        CH1UF_W::new(self)
237    }
238    #[doc = "Bit 6 - CH0BL Interrupt Enable"]
239    #[inline(always)]
240    #[must_use]
241    pub fn ch0bl(&mut self) -> CH0BL_W<6> {
242        CH0BL_W::new(self)
243    }
244    #[doc = "Bit 7 - CH1BL Interrupt Enable"]
245    #[inline(always)]
246    #[must_use]
247    pub fn ch1bl(&mut self) -> CH1BL_W<7> {
248        CH1BL_W::new(self)
249    }
250    #[doc = "Bit 15 - EM23ERR Interrupt Enable"]
251    #[inline(always)]
252    #[must_use]
253    pub fn em23err(&mut self) -> EM23ERR_W<15> {
254        EM23ERR_W::new(self)
255    }
256    #[doc = "Bit 16 - OPA0APORTCONFLICT Interrupt Enable"]
257    #[inline(always)]
258    #[must_use]
259    pub fn opa0aportconflict(&mut self) -> OPA0APORTCONFLICT_W<16> {
260        OPA0APORTCONFLICT_W::new(self)
261    }
262    #[doc = "Bit 17 - OPA1APORTCONFLICT Interrupt Enable"]
263    #[inline(always)]
264    #[must_use]
265    pub fn opa1aportconflict(&mut self) -> OPA1APORTCONFLICT_W<17> {
266        OPA1APORTCONFLICT_W::new(self)
267    }
268    #[doc = "Bit 18 - OPA2APORTCONFLICT Interrupt Enable"]
269    #[inline(always)]
270    #[must_use]
271    pub fn opa2aportconflict(&mut self) -> OPA2APORTCONFLICT_W<18> {
272        OPA2APORTCONFLICT_W::new(self)
273    }
274    #[doc = "Bit 20 - OPA0PRSTIMEDERR Interrupt Enable"]
275    #[inline(always)]
276    #[must_use]
277    pub fn opa0prstimederr(&mut self) -> OPA0PRSTIMEDERR_W<20> {
278        OPA0PRSTIMEDERR_W::new(self)
279    }
280    #[doc = "Bit 21 - OPA1PRSTIMEDERR Interrupt Enable"]
281    #[inline(always)]
282    #[must_use]
283    pub fn opa1prstimederr(&mut self) -> OPA1PRSTIMEDERR_W<21> {
284        OPA1PRSTIMEDERR_W::new(self)
285    }
286    #[doc = "Bit 22 - OPA2PRSTIMEDERR Interrupt Enable"]
287    #[inline(always)]
288    #[must_use]
289    pub fn opa2prstimederr(&mut self) -> OPA2PRSTIMEDERR_W<22> {
290        OPA2PRSTIMEDERR_W::new(self)
291    }
292    #[doc = "Bit 28 - OPA0OUTVALID Interrupt Enable"]
293    #[inline(always)]
294    #[must_use]
295    pub fn opa0outvalid(&mut self) -> OPA0OUTVALID_W<28> {
296        OPA0OUTVALID_W::new(self)
297    }
298    #[doc = "Bit 29 - OPA1OUTVALID Interrupt Enable"]
299    #[inline(always)]
300    #[must_use]
301    pub fn opa1outvalid(&mut self) -> OPA1OUTVALID_W<29> {
302        OPA1OUTVALID_W::new(self)
303    }
304    #[doc = "Bit 30 - OPA2OUTVALID Interrupt Enable"]
305    #[inline(always)]
306    #[must_use]
307    pub fn opa2outvalid(&mut self) -> OPA2OUTVALID_W<30> {
308        OPA2OUTVALID_W::new(self)
309    }
310    #[doc = "Writes raw bits to the register."]
311    #[inline(always)]
312    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
313        self.0.bits(bits);
314        self
315    }
316}
317#[doc = "Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ien](index.html) module"]
318pub struct IEN_SPEC;
319impl crate::RegisterSpec for IEN_SPEC {
320    type Ux = u32;
321}
322#[doc = "`read()` method returns [ien::R](R) reader structure"]
323impl crate::Readable for IEN_SPEC {
324    type Reader = R;
325}
326#[doc = "`write(|w| ..)` method takes [ien::W](W) writer structure"]
327impl crate::Writable for IEN_SPEC {
328    type Writer = W;
329    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
330    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
331}
332#[doc = "`reset()` method sets IEN to value 0"]
333impl crate::Resettable for IEN_SPEC {
334    const RESET_VALUE: Self::Ux = 0;
335}
efm32jg12b_pac/efm32jg12b500/vdac0/ien.rs

efm32jg12b_pac/efm32jg12b500/vdac0/
ien.rs
