efm32jg12b_pac/efm32jg12b500/prs/
ch3_ctrl.rs

1#[doc = "Register `CH3_CTRL` reader"]
2pub struct R(crate::R<CH3_CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CH3_CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CH3_CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CH3_CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CH3_CTRL` writer"]
17pub struct W(crate::W<CH3_CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CH3_CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CH3_CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CH3_CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SIGSEL` reader - Signal Select"]
38pub type SIGSEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `SIGSEL` writer - Signal Select"]
40pub type SIGSEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CH3_CTRL_SPEC, u8, u8, 3, O>;
41#[doc = "Field `SOURCESEL` reader - Source Select"]
42pub type SOURCESEL_R = crate::FieldReader<u8, SOURCESEL_A>;
43#[doc = "Source Select\n\nValue on reset: 0"]
44#[derive(Clone, Copy, Debug, PartialEq, Eq)]
45#[repr(u8)]
46pub enum SOURCESEL_A {
47    #[doc = "0: No source selected"]
48    NONE = 0,
49    #[doc = "1: Peripheral Reflex System"]
50    PRSL = 1,
51    #[doc = "2: Peripheral Reflex System"]
52    PRSH = 2,
53    #[doc = "3: Analog Comparator 0"]
54    ACMP0 = 3,
55    #[doc = "4: Analog Comparator 1"]
56    ACMP1 = 4,
57    #[doc = "5: Analog to Digital Converter 0"]
58    ADC0 = 5,
59    #[doc = "7: Low Energy Sensor Interface"]
60    LESENSEL = 7,
61    #[doc = "8: Low Energy Sensor Interface"]
62    LESENSEH = 8,
63    #[doc = "9: Low Energy Sensor Interface"]
64    LESENSED = 9,
65    #[doc = "10: Low Energy Sensor Interface"]
66    LESENSE = 10,
67    #[doc = "11: Real-Time Counter and Calendar"]
68    RTCC = 11,
69    #[doc = "12: General purpose Input/Output"]
70    GPIOL = 12,
71    #[doc = "13: General purpose Input/Output"]
72    GPIOH = 13,
73    #[doc = "14: Low Energy Timer 0"]
74    LETIMER0 = 14,
75    #[doc = "15: Pulse Counter 0"]
76    PCNT0 = 15,
77    #[doc = "16: Pulse Counter 1"]
78    PCNT1 = 16,
79    #[doc = "17: Pulse Counter 2"]
80    PCNT2 = 17,
81    #[doc = "18: Clock Management Unit"]
82    CMU = 18,
83    #[doc = "24: Digital to Analog Converter 0"]
84    VDAC0 = 24,
85    #[doc = "26: CRYOTIMER"]
86    CRYOTIMER = 26,
87    #[doc = "48: Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
88    USART0 = 48,
89    #[doc = "49: Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
90    USART1 = 49,
91    #[doc = "50: Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
92    USART2 = 50,
93    #[doc = "51: Universal Synchronous/Asynchronous Receiver/Transmitter 3"]
94    USART3 = 51,
95    #[doc = "60: Timer 0"]
96    TIMER0 = 60,
97    #[doc = "61: Timer 1"]
98    TIMER1 = 61,
99    #[doc = "62: Wide Timer 0"]
100    WTIMER0 = 62,
101    #[doc = "63: Wide Timer 1"]
102    WTIMER1 = 63,
103    #[doc = "67: `1000011`"]
104    CM4 = 67,
105}
106impl From<SOURCESEL_A> for u8 {
107    #[inline(always)]
108    fn from(variant: SOURCESEL_A) -> Self {
109        variant as _
110    }
111}
112impl SOURCESEL_R {
113    #[doc = "Get enumerated values variant"]
114    #[inline(always)]
115    pub fn variant(&self) -> Option<SOURCESEL_A> {
116        match self.bits {
117            0 => Some(SOURCESEL_A::NONE),
118            1 => Some(SOURCESEL_A::PRSL),
119            2 => Some(SOURCESEL_A::PRSH),
120            3 => Some(SOURCESEL_A::ACMP0),
121            4 => Some(SOURCESEL_A::ACMP1),
122            5 => Some(SOURCESEL_A::ADC0),
123            7 => Some(SOURCESEL_A::LESENSEL),
124            8 => Some(SOURCESEL_A::LESENSEH),
125            9 => Some(SOURCESEL_A::LESENSED),
126            10 => Some(SOURCESEL_A::LESENSE),
127            11 => Some(SOURCESEL_A::RTCC),
128            12 => Some(SOURCESEL_A::GPIOL),
129            13 => Some(SOURCESEL_A::GPIOH),
130            14 => Some(SOURCESEL_A::LETIMER0),
131            15 => Some(SOURCESEL_A::PCNT0),
132            16 => Some(SOURCESEL_A::PCNT1),
133            17 => Some(SOURCESEL_A::PCNT2),
134            18 => Some(SOURCESEL_A::CMU),
135            24 => Some(SOURCESEL_A::VDAC0),
136            26 => Some(SOURCESEL_A::CRYOTIMER),
137            48 => Some(SOURCESEL_A::USART0),
138            49 => Some(SOURCESEL_A::USART1),
139            50 => Some(SOURCESEL_A::USART2),
140            51 => Some(SOURCESEL_A::USART3),
141            60 => Some(SOURCESEL_A::TIMER0),
142            61 => Some(SOURCESEL_A::TIMER1),
143            62 => Some(SOURCESEL_A::WTIMER0),
144            63 => Some(SOURCESEL_A::WTIMER1),
145            67 => Some(SOURCESEL_A::CM4),
146            _ => None,
147        }
148    }
149    #[doc = "Checks if the value of the field is `NONE`"]
150    #[inline(always)]
151    pub fn is_none(&self) -> bool {
152        *self == SOURCESEL_A::NONE
153    }
154    #[doc = "Checks if the value of the field is `PRSL`"]
155    #[inline(always)]
156    pub fn is_prsl(&self) -> bool {
157        *self == SOURCESEL_A::PRSL
158    }
159    #[doc = "Checks if the value of the field is `PRSH`"]
160    #[inline(always)]
161    pub fn is_prsh(&self) -> bool {
162        *self == SOURCESEL_A::PRSH
163    }
164    #[doc = "Checks if the value of the field is `ACMP0`"]
165    #[inline(always)]
166    pub fn is_acmp0(&self) -> bool {
167        *self == SOURCESEL_A::ACMP0
168    }
169    #[doc = "Checks if the value of the field is `ACMP1`"]
170    #[inline(always)]
171    pub fn is_acmp1(&self) -> bool {
172        *self == SOURCESEL_A::ACMP1
173    }
174    #[doc = "Checks if the value of the field is `ADC0`"]
175    #[inline(always)]
176    pub fn is_adc0(&self) -> bool {
177        *self == SOURCESEL_A::ADC0
178    }
179    #[doc = "Checks if the value of the field is `LESENSEL`"]
180    #[inline(always)]
181    pub fn is_lesensel(&self) -> bool {
182        *self == SOURCESEL_A::LESENSEL
183    }
184    #[doc = "Checks if the value of the field is `LESENSEH`"]
185    #[inline(always)]
186    pub fn is_lesenseh(&self) -> bool {
187        *self == SOURCESEL_A::LESENSEH
188    }
189    #[doc = "Checks if the value of the field is `LESENSED`"]
190    #[inline(always)]
191    pub fn is_lesensed(&self) -> bool {
192        *self == SOURCESEL_A::LESENSED
193    }
194    #[doc = "Checks if the value of the field is `LESENSE`"]
195    #[inline(always)]
196    pub fn is_lesense(&self) -> bool {
197        *self == SOURCESEL_A::LESENSE
198    }
199    #[doc = "Checks if the value of the field is `RTCC`"]
200    #[inline(always)]
201    pub fn is_rtcc(&self) -> bool {
202        *self == SOURCESEL_A::RTCC
203    }
204    #[doc = "Checks if the value of the field is `GPIOL`"]
205    #[inline(always)]
206    pub fn is_gpiol(&self) -> bool {
207        *self == SOURCESEL_A::GPIOL
208    }
209    #[doc = "Checks if the value of the field is `GPIOH`"]
210    #[inline(always)]
211    pub fn is_gpioh(&self) -> bool {
212        *self == SOURCESEL_A::GPIOH
213    }
214    #[doc = "Checks if the value of the field is `LETIMER0`"]
215    #[inline(always)]
216    pub fn is_letimer0(&self) -> bool {
217        *self == SOURCESEL_A::LETIMER0
218    }
219    #[doc = "Checks if the value of the field is `PCNT0`"]
220    #[inline(always)]
221    pub fn is_pcnt0(&self) -> bool {
222        *self == SOURCESEL_A::PCNT0
223    }
224    #[doc = "Checks if the value of the field is `PCNT1`"]
225    #[inline(always)]
226    pub fn is_pcnt1(&self) -> bool {
227        *self == SOURCESEL_A::PCNT1
228    }
229    #[doc = "Checks if the value of the field is `PCNT2`"]
230    #[inline(always)]
231    pub fn is_pcnt2(&self) -> bool {
232        *self == SOURCESEL_A::PCNT2
233    }
234    #[doc = "Checks if the value of the field is `CMU`"]
235    #[inline(always)]
236    pub fn is_cmu(&self) -> bool {
237        *self == SOURCESEL_A::CMU
238    }
239    #[doc = "Checks if the value of the field is `VDAC0`"]
240    #[inline(always)]
241    pub fn is_vdac0(&self) -> bool {
242        *self == SOURCESEL_A::VDAC0
243    }
244    #[doc = "Checks if the value of the field is `CRYOTIMER`"]
245    #[inline(always)]
246    pub fn is_cryotimer(&self) -> bool {
247        *self == SOURCESEL_A::CRYOTIMER
248    }
249    #[doc = "Checks if the value of the field is `USART0`"]
250    #[inline(always)]
251    pub fn is_usart0(&self) -> bool {
252        *self == SOURCESEL_A::USART0
253    }
254    #[doc = "Checks if the value of the field is `USART1`"]
255    #[inline(always)]
256    pub fn is_usart1(&self) -> bool {
257        *self == SOURCESEL_A::USART1
258    }
259    #[doc = "Checks if the value of the field is `USART2`"]
260    #[inline(always)]
261    pub fn is_usart2(&self) -> bool {
262        *self == SOURCESEL_A::USART2
263    }
264    #[doc = "Checks if the value of the field is `USART3`"]
265    #[inline(always)]
266    pub fn is_usart3(&self) -> bool {
267        *self == SOURCESEL_A::USART3
268    }
269    #[doc = "Checks if the value of the field is `TIMER0`"]
270    #[inline(always)]
271    pub fn is_timer0(&self) -> bool {
272        *self == SOURCESEL_A::TIMER0
273    }
274    #[doc = "Checks if the value of the field is `TIMER1`"]
275    #[inline(always)]
276    pub fn is_timer1(&self) -> bool {
277        *self == SOURCESEL_A::TIMER1
278    }
279    #[doc = "Checks if the value of the field is `WTIMER0`"]
280    #[inline(always)]
281    pub fn is_wtimer0(&self) -> bool {
282        *self == SOURCESEL_A::WTIMER0
283    }
284    #[doc = "Checks if the value of the field is `WTIMER1`"]
285    #[inline(always)]
286    pub fn is_wtimer1(&self) -> bool {
287        *self == SOURCESEL_A::WTIMER1
288    }
289    #[doc = "Checks if the value of the field is `CM4`"]
290    #[inline(always)]
291    pub fn is_cm4(&self) -> bool {
292        *self == SOURCESEL_A::CM4
293    }
294}
295#[doc = "Field `SOURCESEL` writer - Source Select"]
296pub type SOURCESEL_W<'a, const O: u8> =
297    crate::FieldWriter<'a, u32, CH3_CTRL_SPEC, u8, SOURCESEL_A, 7, O>;
298impl<'a, const O: u8> SOURCESEL_W<'a, O> {
299    #[doc = "No source selected"]
300    #[inline(always)]
301    pub fn none(self) -> &'a mut W {
302        self.variant(SOURCESEL_A::NONE)
303    }
304    #[doc = "Peripheral Reflex System"]
305    #[inline(always)]
306    pub fn prsl(self) -> &'a mut W {
307        self.variant(SOURCESEL_A::PRSL)
308    }
309    #[doc = "Peripheral Reflex System"]
310    #[inline(always)]
311    pub fn prsh(self) -> &'a mut W {
312        self.variant(SOURCESEL_A::PRSH)
313    }
314    #[doc = "Analog Comparator 0"]
315    #[inline(always)]
316    pub fn acmp0(self) -> &'a mut W {
317        self.variant(SOURCESEL_A::ACMP0)
318    }
319    #[doc = "Analog Comparator 1"]
320    #[inline(always)]
321    pub fn acmp1(self) -> &'a mut W {
322        self.variant(SOURCESEL_A::ACMP1)
323    }
324    #[doc = "Analog to Digital Converter 0"]
325    #[inline(always)]
326    pub fn adc0(self) -> &'a mut W {
327        self.variant(SOURCESEL_A::ADC0)
328    }
329    #[doc = "Low Energy Sensor Interface"]
330    #[inline(always)]
331    pub fn lesensel(self) -> &'a mut W {
332        self.variant(SOURCESEL_A::LESENSEL)
333    }
334    #[doc = "Low Energy Sensor Interface"]
335    #[inline(always)]
336    pub fn lesenseh(self) -> &'a mut W {
337        self.variant(SOURCESEL_A::LESENSEH)
338    }
339    #[doc = "Low Energy Sensor Interface"]
340    #[inline(always)]
341    pub fn lesensed(self) -> &'a mut W {
342        self.variant(SOURCESEL_A::LESENSED)
343    }
344    #[doc = "Low Energy Sensor Interface"]
345    #[inline(always)]
346    pub fn lesense(self) -> &'a mut W {
347        self.variant(SOURCESEL_A::LESENSE)
348    }
349    #[doc = "Real-Time Counter and Calendar"]
350    #[inline(always)]
351    pub fn rtcc(self) -> &'a mut W {
352        self.variant(SOURCESEL_A::RTCC)
353    }
354    #[doc = "General purpose Input/Output"]
355    #[inline(always)]
356    pub fn gpiol(self) -> &'a mut W {
357        self.variant(SOURCESEL_A::GPIOL)
358    }
359    #[doc = "General purpose Input/Output"]
360    #[inline(always)]
361    pub fn gpioh(self) -> &'a mut W {
362        self.variant(SOURCESEL_A::GPIOH)
363    }
364    #[doc = "Low Energy Timer 0"]
365    #[inline(always)]
366    pub fn letimer0(self) -> &'a mut W {
367        self.variant(SOURCESEL_A::LETIMER0)
368    }
369    #[doc = "Pulse Counter 0"]
370    #[inline(always)]
371    pub fn pcnt0(self) -> &'a mut W {
372        self.variant(SOURCESEL_A::PCNT0)
373    }
374    #[doc = "Pulse Counter 1"]
375    #[inline(always)]
376    pub fn pcnt1(self) -> &'a mut W {
377        self.variant(SOURCESEL_A::PCNT1)
378    }
379    #[doc = "Pulse Counter 2"]
380    #[inline(always)]
381    pub fn pcnt2(self) -> &'a mut W {
382        self.variant(SOURCESEL_A::PCNT2)
383    }
384    #[doc = "Clock Management Unit"]
385    #[inline(always)]
386    pub fn cmu(self) -> &'a mut W {
387        self.variant(SOURCESEL_A::CMU)
388    }
389    #[doc = "Digital to Analog Converter 0"]
390    #[inline(always)]
391    pub fn vdac0(self) -> &'a mut W {
392        self.variant(SOURCESEL_A::VDAC0)
393    }
394    #[doc = "CRYOTIMER"]
395    #[inline(always)]
396    pub fn cryotimer(self) -> &'a mut W {
397        self.variant(SOURCESEL_A::CRYOTIMER)
398    }
399    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
400    #[inline(always)]
401    pub fn usart0(self) -> &'a mut W {
402        self.variant(SOURCESEL_A::USART0)
403    }
404    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
405    #[inline(always)]
406    pub fn usart1(self) -> &'a mut W {
407        self.variant(SOURCESEL_A::USART1)
408    }
409    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
410    #[inline(always)]
411    pub fn usart2(self) -> &'a mut W {
412        self.variant(SOURCESEL_A::USART2)
413    }
414    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 3"]
415    #[inline(always)]
416    pub fn usart3(self) -> &'a mut W {
417        self.variant(SOURCESEL_A::USART3)
418    }
419    #[doc = "Timer 0"]
420    #[inline(always)]
421    pub fn timer0(self) -> &'a mut W {
422        self.variant(SOURCESEL_A::TIMER0)
423    }
424    #[doc = "Timer 1"]
425    #[inline(always)]
426    pub fn timer1(self) -> &'a mut W {
427        self.variant(SOURCESEL_A::TIMER1)
428    }
429    #[doc = "Wide Timer 0"]
430    #[inline(always)]
431    pub fn wtimer0(self) -> &'a mut W {
432        self.variant(SOURCESEL_A::WTIMER0)
433    }
434    #[doc = "Wide Timer 1"]
435    #[inline(always)]
436    pub fn wtimer1(self) -> &'a mut W {
437        self.variant(SOURCESEL_A::WTIMER1)
438    }
439    #[doc = "`1000011`"]
440    #[inline(always)]
441    pub fn cm4(self) -> &'a mut W {
442        self.variant(SOURCESEL_A::CM4)
443    }
444}
445#[doc = "Field `EDSEL` reader - Edge Detect Select"]
446pub type EDSEL_R = crate::FieldReader<u8, EDSEL_A>;
447#[doc = "Edge Detect Select\n\nValue on reset: 0"]
448#[derive(Clone, Copy, Debug, PartialEq, Eq)]
449#[repr(u8)]
450pub enum EDSEL_A {
451    #[doc = "0: Signal is left as it is"]
452    OFF = 0,
453    #[doc = "1: A one HFCLK cycle pulse is generated for every positive edge of the incoming signal"]
454    POSEDGE = 1,
455    #[doc = "2: A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
456    NEGEDGE = 2,
457    #[doc = "3: A one HFCLK clock cycle pulse is generated for every edge of the incoming signal"]
458    BOTHEDGES = 3,
459}
460impl From<EDSEL_A> for u8 {
461    #[inline(always)]
462    fn from(variant: EDSEL_A) -> Self {
463        variant as _
464    }
465}
466impl EDSEL_R {
467    #[doc = "Get enumerated values variant"]
468    #[inline(always)]
469    pub fn variant(&self) -> EDSEL_A {
470        match self.bits {
471            0 => EDSEL_A::OFF,
472            1 => EDSEL_A::POSEDGE,
473            2 => EDSEL_A::NEGEDGE,
474            3 => EDSEL_A::BOTHEDGES,
475            _ => unreachable!(),
476        }
477    }
478    #[doc = "Checks if the value of the field is `OFF`"]
479    #[inline(always)]
480    pub fn is_off(&self) -> bool {
481        *self == EDSEL_A::OFF
482    }
483    #[doc = "Checks if the value of the field is `POSEDGE`"]
484    #[inline(always)]
485    pub fn is_posedge(&self) -> bool {
486        *self == EDSEL_A::POSEDGE
487    }
488    #[doc = "Checks if the value of the field is `NEGEDGE`"]
489    #[inline(always)]
490    pub fn is_negedge(&self) -> bool {
491        *self == EDSEL_A::NEGEDGE
492    }
493    #[doc = "Checks if the value of the field is `BOTHEDGES`"]
494    #[inline(always)]
495    pub fn is_bothedges(&self) -> bool {
496        *self == EDSEL_A::BOTHEDGES
497    }
498}
499#[doc = "Field `EDSEL` writer - Edge Detect Select"]
500pub type EDSEL_W<'a, const O: u8> =
501    crate::FieldWriterSafe<'a, u32, CH3_CTRL_SPEC, u8, EDSEL_A, 2, O>;
502impl<'a, const O: u8> EDSEL_W<'a, O> {
503    #[doc = "Signal is left as it is"]
504    #[inline(always)]
505    pub fn off(self) -> &'a mut W {
506        self.variant(EDSEL_A::OFF)
507    }
508    #[doc = "A one HFCLK cycle pulse is generated for every positive edge of the incoming signal"]
509    #[inline(always)]
510    pub fn posedge(self) -> &'a mut W {
511        self.variant(EDSEL_A::POSEDGE)
512    }
513    #[doc = "A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
514    #[inline(always)]
515    pub fn negedge(self) -> &'a mut W {
516        self.variant(EDSEL_A::NEGEDGE)
517    }
518    #[doc = "A one HFCLK clock cycle pulse is generated for every edge of the incoming signal"]
519    #[inline(always)]
520    pub fn bothedges(self) -> &'a mut W {
521        self.variant(EDSEL_A::BOTHEDGES)
522    }
523}
524#[doc = "Field `STRETCH` reader - Stretch Channel Output"]
525pub type STRETCH_R = crate::BitReader<bool>;
526#[doc = "Field `STRETCH` writer - Stretch Channel Output"]
527pub type STRETCH_W<'a, const O: u8> = crate::BitWriter<'a, u32, CH3_CTRL_SPEC, bool, O>;
528#[doc = "Field `INV` reader - Invert Channel"]
529pub type INV_R = crate::BitReader<bool>;
530#[doc = "Field `INV` writer - Invert Channel"]
531pub type INV_W<'a, const O: u8> = crate::BitWriter<'a, u32, CH3_CTRL_SPEC, bool, O>;
532#[doc = "Field `ORPREV` reader - Or Previous"]
533pub type ORPREV_R = crate::BitReader<bool>;
534#[doc = "Field `ORPREV` writer - Or Previous"]
535pub type ORPREV_W<'a, const O: u8> = crate::BitWriter<'a, u32, CH3_CTRL_SPEC, bool, O>;
536#[doc = "Field `ANDNEXT` reader - And Next"]
537pub type ANDNEXT_R = crate::BitReader<bool>;
538#[doc = "Field `ANDNEXT` writer - And Next"]
539pub type ANDNEXT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CH3_CTRL_SPEC, bool, O>;
540#[doc = "Field `ASYNC` reader - Asynchronous Reflex"]
541pub type ASYNC_R = crate::BitReader<bool>;
542#[doc = "Field `ASYNC` writer - Asynchronous Reflex"]
543pub type ASYNC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CH3_CTRL_SPEC, bool, O>;
544impl R {
545    #[doc = "Bits 0:2 - Signal Select"]
546    #[inline(always)]
547    pub fn sigsel(&self) -> SIGSEL_R {
548        SIGSEL_R::new((self.bits & 7) as u8)
549    }
550    #[doc = "Bits 8:14 - Source Select"]
551    #[inline(always)]
552    pub fn sourcesel(&self) -> SOURCESEL_R {
553        SOURCESEL_R::new(((self.bits >> 8) & 0x7f) as u8)
554    }
555    #[doc = "Bits 20:21 - Edge Detect Select"]
556    #[inline(always)]
557    pub fn edsel(&self) -> EDSEL_R {
558        EDSEL_R::new(((self.bits >> 20) & 3) as u8)
559    }
560    #[doc = "Bit 25 - Stretch Channel Output"]
561    #[inline(always)]
562    pub fn stretch(&self) -> STRETCH_R {
563        STRETCH_R::new(((self.bits >> 25) & 1) != 0)
564    }
565    #[doc = "Bit 26 - Invert Channel"]
566    #[inline(always)]
567    pub fn inv(&self) -> INV_R {
568        INV_R::new(((self.bits >> 26) & 1) != 0)
569    }
570    #[doc = "Bit 27 - Or Previous"]
571    #[inline(always)]
572    pub fn orprev(&self) -> ORPREV_R {
573        ORPREV_R::new(((self.bits >> 27) & 1) != 0)
574    }
575    #[doc = "Bit 28 - And Next"]
576    #[inline(always)]
577    pub fn andnext(&self) -> ANDNEXT_R {
578        ANDNEXT_R::new(((self.bits >> 28) & 1) != 0)
579    }
580    #[doc = "Bit 30 - Asynchronous Reflex"]
581    #[inline(always)]
582    pub fn async_(&self) -> ASYNC_R {
583        ASYNC_R::new(((self.bits >> 30) & 1) != 0)
584    }
585}
586impl W {
587    #[doc = "Bits 0:2 - Signal Select"]
588    #[inline(always)]
589    #[must_use]
590    pub fn sigsel(&mut self) -> SIGSEL_W<0> {
591        SIGSEL_W::new(self)
592    }
593    #[doc = "Bits 8:14 - Source Select"]
594    #[inline(always)]
595    #[must_use]
596    pub fn sourcesel(&mut self) -> SOURCESEL_W<8> {
597        SOURCESEL_W::new(self)
598    }
599    #[doc = "Bits 20:21 - Edge Detect Select"]
600    #[inline(always)]
601    #[must_use]
602    pub fn edsel(&mut self) -> EDSEL_W<20> {
603        EDSEL_W::new(self)
604    }
605    #[doc = "Bit 25 - Stretch Channel Output"]
606    #[inline(always)]
607    #[must_use]
608    pub fn stretch(&mut self) -> STRETCH_W<25> {
609        STRETCH_W::new(self)
610    }
611    #[doc = "Bit 26 - Invert Channel"]
612    #[inline(always)]
613    #[must_use]
614    pub fn inv(&mut self) -> INV_W<26> {
615        INV_W::new(self)
616    }
617    #[doc = "Bit 27 - Or Previous"]
618    #[inline(always)]
619    #[must_use]
620    pub fn orprev(&mut self) -> ORPREV_W<27> {
621        ORPREV_W::new(self)
622    }
623    #[doc = "Bit 28 - And Next"]
624    #[inline(always)]
625    #[must_use]
626    pub fn andnext(&mut self) -> ANDNEXT_W<28> {
627        ANDNEXT_W::new(self)
628    }
629    #[doc = "Bit 30 - Asynchronous Reflex"]
630    #[inline(always)]
631    #[must_use]
632    pub fn async_(&mut self) -> ASYNC_W<30> {
633        ASYNC_W::new(self)
634    }
635    #[doc = "Writes raw bits to the register."]
636    #[inline(always)]
637    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
638        self.0.bits(bits);
639        self
640    }
641}
642#[doc = "Channel Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch3_ctrl](index.html) module"]
643pub struct CH3_CTRL_SPEC;
644impl crate::RegisterSpec for CH3_CTRL_SPEC {
645    type Ux = u32;
646}
647#[doc = "`read()` method returns [ch3_ctrl::R](R) reader structure"]
648impl crate::Readable for CH3_CTRL_SPEC {
649    type Reader = R;
650}
651#[doc = "`write(|w| ..)` method takes [ch3_ctrl::W](W) writer structure"]
652impl crate::Writable for CH3_CTRL_SPEC {
653    type Writer = W;
654    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
655    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
656}
657#[doc = "`reset()` method sets CH3_CTRL to value 0"]
658impl crate::Resettable for CH3_CTRL_SPEC {
659    const RESET_VALUE: Self::Ux = 0;
660}
efm32jg12b_pac/efm32jg12b500/prs/ch3_ctrl.rs

efm32jg12b_pac/efm32jg12b500/prs/
ch3_ctrl.rs
