efm32jg12b_pac/efm32jg12b500/gpio/
routepen.rs

1#[doc = "Register `ROUTEPEN` reader"]
2pub struct R(crate::R<ROUTEPEN_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<ROUTEPEN_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<ROUTEPEN_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<ROUTEPEN_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `ROUTEPEN` writer"]
17pub struct W(crate::W<ROUTEPEN_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<ROUTEPEN_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<ROUTEPEN_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<ROUTEPEN_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SWCLKTCKPEN` reader - Serial Wire Clock and JTAG Test Clock Pin Enable"]
38pub type SWCLKTCKPEN_R = crate::BitReader<bool>;
39#[doc = "Field `SWCLKTCKPEN` writer - Serial Wire Clock and JTAG Test Clock Pin Enable"]
40pub type SWCLKTCKPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ROUTEPEN_SPEC, bool, O>;
41#[doc = "Field `SWDIOTMSPEN` reader - Serial Wire Data and JTAG Test Mode Select Pin Enable"]
42pub type SWDIOTMSPEN_R = crate::BitReader<bool>;
43#[doc = "Field `SWDIOTMSPEN` writer - Serial Wire Data and JTAG Test Mode Select Pin Enable"]
44pub type SWDIOTMSPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ROUTEPEN_SPEC, bool, O>;
45#[doc = "Field `TDOPEN` reader - JTAG Test Debug Output Pin Enable"]
46pub type TDOPEN_R = crate::BitReader<bool>;
47#[doc = "Field `TDOPEN` writer - JTAG Test Debug Output Pin Enable"]
48pub type TDOPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ROUTEPEN_SPEC, bool, O>;
49#[doc = "Field `TDIPEN` reader - JTAG Test Debug Input Pin Enable"]
50pub type TDIPEN_R = crate::BitReader<bool>;
51#[doc = "Field `TDIPEN` writer - JTAG Test Debug Input Pin Enable"]
52pub type TDIPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ROUTEPEN_SPEC, bool, O>;
53#[doc = "Field `SWVPEN` reader - Serial Wire Viewer Output Pin Enable"]
54pub type SWVPEN_R = crate::BitReader<bool>;
55#[doc = "Field `SWVPEN` writer - Serial Wire Viewer Output Pin Enable"]
56pub type SWVPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ROUTEPEN_SPEC, bool, O>;
57#[doc = "Field `ETMTCLKPEN` reader - ETM Trace Clock Pin Enable"]
58pub type ETMTCLKPEN_R = crate::BitReader<bool>;
59#[doc = "Field `ETMTCLKPEN` writer - ETM Trace Clock Pin Enable"]
60pub type ETMTCLKPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ROUTEPEN_SPEC, bool, O>;
61#[doc = "Field `ETMTD0PEN` reader - ETM Trace Data Pin Enable"]
62pub type ETMTD0PEN_R = crate::BitReader<bool>;
63#[doc = "Field `ETMTD0PEN` writer - ETM Trace Data Pin Enable"]
64pub type ETMTD0PEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ROUTEPEN_SPEC, bool, O>;
65#[doc = "Field `ETMTD1PEN` reader - ETM Trace Data Pin Enable"]
66pub type ETMTD1PEN_R = crate::BitReader<bool>;
67#[doc = "Field `ETMTD1PEN` writer - ETM Trace Data Pin Enable"]
68pub type ETMTD1PEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ROUTEPEN_SPEC, bool, O>;
69#[doc = "Field `ETMTD2PEN` reader - ETM Trace Data Pin Enable"]
70pub type ETMTD2PEN_R = crate::BitReader<bool>;
71#[doc = "Field `ETMTD2PEN` writer - ETM Trace Data Pin Enable"]
72pub type ETMTD2PEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ROUTEPEN_SPEC, bool, O>;
73#[doc = "Field `ETMTD3PEN` reader - ETM Trace Data Pin Enable"]
74pub type ETMTD3PEN_R = crate::BitReader<bool>;
75#[doc = "Field `ETMTD3PEN` writer - ETM Trace Data Pin Enable"]
76pub type ETMTD3PEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ROUTEPEN_SPEC, bool, O>;
77impl R {
78    #[doc = "Bit 0 - Serial Wire Clock and JTAG Test Clock Pin Enable"]
79    #[inline(always)]
80    pub fn swclktckpen(&self) -> SWCLKTCKPEN_R {
81        SWCLKTCKPEN_R::new((self.bits & 1) != 0)
82    }
83    #[doc = "Bit 1 - Serial Wire Data and JTAG Test Mode Select Pin Enable"]
84    #[inline(always)]
85    pub fn swdiotmspen(&self) -> SWDIOTMSPEN_R {
86        SWDIOTMSPEN_R::new(((self.bits >> 1) & 1) != 0)
87    }
88    #[doc = "Bit 2 - JTAG Test Debug Output Pin Enable"]
89    #[inline(always)]
90    pub fn tdopen(&self) -> TDOPEN_R {
91        TDOPEN_R::new(((self.bits >> 2) & 1) != 0)
92    }
93    #[doc = "Bit 3 - JTAG Test Debug Input Pin Enable"]
94    #[inline(always)]
95    pub fn tdipen(&self) -> TDIPEN_R {
96        TDIPEN_R::new(((self.bits >> 3) & 1) != 0)
97    }
98    #[doc = "Bit 4 - Serial Wire Viewer Output Pin Enable"]
99    #[inline(always)]
100    pub fn swvpen(&self) -> SWVPEN_R {
101        SWVPEN_R::new(((self.bits >> 4) & 1) != 0)
102    }
103    #[doc = "Bit 16 - ETM Trace Clock Pin Enable"]
104    #[inline(always)]
105    pub fn etmtclkpen(&self) -> ETMTCLKPEN_R {
106        ETMTCLKPEN_R::new(((self.bits >> 16) & 1) != 0)
107    }
108    #[doc = "Bit 17 - ETM Trace Data Pin Enable"]
109    #[inline(always)]
110    pub fn etmtd0pen(&self) -> ETMTD0PEN_R {
111        ETMTD0PEN_R::new(((self.bits >> 17) & 1) != 0)
112    }
113    #[doc = "Bit 18 - ETM Trace Data Pin Enable"]
114    #[inline(always)]
115    pub fn etmtd1pen(&self) -> ETMTD1PEN_R {
116        ETMTD1PEN_R::new(((self.bits >> 18) & 1) != 0)
117    }
118    #[doc = "Bit 19 - ETM Trace Data Pin Enable"]
119    #[inline(always)]
120    pub fn etmtd2pen(&self) -> ETMTD2PEN_R {
121        ETMTD2PEN_R::new(((self.bits >> 19) & 1) != 0)
122    }
123    #[doc = "Bit 20 - ETM Trace Data Pin Enable"]
124    #[inline(always)]
125    pub fn etmtd3pen(&self) -> ETMTD3PEN_R {
126        ETMTD3PEN_R::new(((self.bits >> 20) & 1) != 0)
127    }
128}
129impl W {
130    #[doc = "Bit 0 - Serial Wire Clock and JTAG Test Clock Pin Enable"]
131    #[inline(always)]
132    #[must_use]
133    pub fn swclktckpen(&mut self) -> SWCLKTCKPEN_W<0> {
134        SWCLKTCKPEN_W::new(self)
135    }
136    #[doc = "Bit 1 - Serial Wire Data and JTAG Test Mode Select Pin Enable"]
137    #[inline(always)]
138    #[must_use]
139    pub fn swdiotmspen(&mut self) -> SWDIOTMSPEN_W<1> {
140        SWDIOTMSPEN_W::new(self)
141    }
142    #[doc = "Bit 2 - JTAG Test Debug Output Pin Enable"]
143    #[inline(always)]
144    #[must_use]
145    pub fn tdopen(&mut self) -> TDOPEN_W<2> {
146        TDOPEN_W::new(self)
147    }
148    #[doc = "Bit 3 - JTAG Test Debug Input Pin Enable"]
149    #[inline(always)]
150    #[must_use]
151    pub fn tdipen(&mut self) -> TDIPEN_W<3> {
152        TDIPEN_W::new(self)
153    }
154    #[doc = "Bit 4 - Serial Wire Viewer Output Pin Enable"]
155    #[inline(always)]
156    #[must_use]
157    pub fn swvpen(&mut self) -> SWVPEN_W<4> {
158        SWVPEN_W::new(self)
159    }
160    #[doc = "Bit 16 - ETM Trace Clock Pin Enable"]
161    #[inline(always)]
162    #[must_use]
163    pub fn etmtclkpen(&mut self) -> ETMTCLKPEN_W<16> {
164        ETMTCLKPEN_W::new(self)
165    }
166    #[doc = "Bit 17 - ETM Trace Data Pin Enable"]
167    #[inline(always)]
168    #[must_use]
169    pub fn etmtd0pen(&mut self) -> ETMTD0PEN_W<17> {
170        ETMTD0PEN_W::new(self)
171    }
172    #[doc = "Bit 18 - ETM Trace Data Pin Enable"]
173    #[inline(always)]
174    #[must_use]
175    pub fn etmtd1pen(&mut self) -> ETMTD1PEN_W<18> {
176        ETMTD1PEN_W::new(self)
177    }
178    #[doc = "Bit 19 - ETM Trace Data Pin Enable"]
179    #[inline(always)]
180    #[must_use]
181    pub fn etmtd2pen(&mut self) -> ETMTD2PEN_W<19> {
182        ETMTD2PEN_W::new(self)
183    }
184    #[doc = "Bit 20 - ETM Trace Data Pin Enable"]
185    #[inline(always)]
186    #[must_use]
187    pub fn etmtd3pen(&mut self) -> ETMTD3PEN_W<20> {
188        ETMTD3PEN_W::new(self)
189    }
190    #[doc = "Writes raw bits to the register."]
191    #[inline(always)]
192    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
193        self.0.bits(bits);
194        self
195    }
196}
197#[doc = "I/O Routing Pin Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [routepen](index.html) module"]
198pub struct ROUTEPEN_SPEC;
199impl crate::RegisterSpec for ROUTEPEN_SPEC {
200    type Ux = u32;
201}
202#[doc = "`read()` method returns [routepen::R](R) reader structure"]
203impl crate::Readable for ROUTEPEN_SPEC {
204    type Reader = R;
205}
206#[doc = "`write(|w| ..)` method takes [routepen::W](W) writer structure"]
207impl crate::Writable for ROUTEPEN_SPEC {
208    type Writer = W;
209    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
210    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
211}
212#[doc = "`reset()` method sets ROUTEPEN to value 0x0f"]
213impl crate::Resettable for ROUTEPEN_SPEC {
214    const RESET_VALUE: Self::Ux = 0x0f;
215}
efm32jg12b_pac/efm32jg12b500/gpio/routepen.rs

efm32jg12b_pac/efm32jg12b500/gpio/
routepen.rs
