efm32hg321_pac/dma/
ch2_ctrl.rs

1#[doc = "Register `CH2_CTRL` reader"]
2pub struct R(crate::R<CH2_CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CH2_CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CH2_CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CH2_CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CH2_CTRL` writer"]
17pub struct W(crate::W<CH2_CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CH2_CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CH2_CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CH2_CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SIGSEL` reader - Signal Select"]
38pub type SIGSEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `SIGSEL` writer - Signal Select"]
40pub type SIGSEL_W<'a> = crate::FieldWriter<'a, u32, CH2_CTRL_SPEC, u8, u8, 4, 0>;
41#[doc = "Source Select\n\nValue on reset: 0"]
42#[derive(Clone, Copy, Debug, PartialEq)]
43#[repr(u8)]
44pub enum SOURCESEL_A {
45    #[doc = "0: No source selected"]
46    NONE = 0,
47    #[doc = "8: Analog to Digital Converter 0"]
48    ADC0 = 8,
49    #[doc = "12: Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
50    USART0 = 12,
51    #[doc = "13: Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
52    USART1 = 13,
53    #[doc = "16: Low Energy UART 0"]
54    LEUART0 = 16,
55    #[doc = "20: I2C 0"]
56    I2C0 = 20,
57    #[doc = "24: Timer 0"]
58    TIMER0 = 24,
59    #[doc = "25: Timer 1"]
60    TIMER1 = 25,
61    #[doc = "26: Timer 2"]
62    TIMER2 = 26,
63    #[doc = "48: `110000`"]
64    MSC = 48,
65}
66impl From<SOURCESEL_A> for u8 {
67    #[inline(always)]
68    fn from(variant: SOURCESEL_A) -> Self {
69        variant as _
70    }
71}
72#[doc = "Field `SOURCESEL` reader - Source Select"]
73pub type SOURCESEL_R = crate::FieldReader<u8, SOURCESEL_A>;
74impl SOURCESEL_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub fn variant(&self) -> Option<SOURCESEL_A> {
78        match self.bits {
79            0 => Some(SOURCESEL_A::NONE),
80            8 => Some(SOURCESEL_A::ADC0),
81            12 => Some(SOURCESEL_A::USART0),
82            13 => Some(SOURCESEL_A::USART1),
83            16 => Some(SOURCESEL_A::LEUART0),
84            20 => Some(SOURCESEL_A::I2C0),
85            24 => Some(SOURCESEL_A::TIMER0),
86            25 => Some(SOURCESEL_A::TIMER1),
87            26 => Some(SOURCESEL_A::TIMER2),
88            48 => Some(SOURCESEL_A::MSC),
89            _ => None,
90        }
91    }
92    #[doc = "Checks if the value of the field is `NONE`"]
93    #[inline(always)]
94    pub fn is_none(&self) -> bool {
95        *self == SOURCESEL_A::NONE
96    }
97    #[doc = "Checks if the value of the field is `ADC0`"]
98    #[inline(always)]
99    pub fn is_adc0(&self) -> bool {
100        *self == SOURCESEL_A::ADC0
101    }
102    #[doc = "Checks if the value of the field is `USART0`"]
103    #[inline(always)]
104    pub fn is_usart0(&self) -> bool {
105        *self == SOURCESEL_A::USART0
106    }
107    #[doc = "Checks if the value of the field is `USART1`"]
108    #[inline(always)]
109    pub fn is_usart1(&self) -> bool {
110        *self == SOURCESEL_A::USART1
111    }
112    #[doc = "Checks if the value of the field is `LEUART0`"]
113    #[inline(always)]
114    pub fn is_leuart0(&self) -> bool {
115        *self == SOURCESEL_A::LEUART0
116    }
117    #[doc = "Checks if the value of the field is `I2C0`"]
118    #[inline(always)]
119    pub fn is_i2c0(&self) -> bool {
120        *self == SOURCESEL_A::I2C0
121    }
122    #[doc = "Checks if the value of the field is `TIMER0`"]
123    #[inline(always)]
124    pub fn is_timer0(&self) -> bool {
125        *self == SOURCESEL_A::TIMER0
126    }
127    #[doc = "Checks if the value of the field is `TIMER1`"]
128    #[inline(always)]
129    pub fn is_timer1(&self) -> bool {
130        *self == SOURCESEL_A::TIMER1
131    }
132    #[doc = "Checks if the value of the field is `TIMER2`"]
133    #[inline(always)]
134    pub fn is_timer2(&self) -> bool {
135        *self == SOURCESEL_A::TIMER2
136    }
137    #[doc = "Checks if the value of the field is `MSC`"]
138    #[inline(always)]
139    pub fn is_msc(&self) -> bool {
140        *self == SOURCESEL_A::MSC
141    }
142}
143#[doc = "Field `SOURCESEL` writer - Source Select"]
144pub type SOURCESEL_W<'a> = crate::FieldWriter<'a, u32, CH2_CTRL_SPEC, u8, SOURCESEL_A, 6, 16>;
145impl<'a> SOURCESEL_W<'a> {
146    #[doc = "No source selected"]
147    #[inline(always)]
148    pub fn none(self) -> &'a mut W {
149        self.variant(SOURCESEL_A::NONE)
150    }
151    #[doc = "Analog to Digital Converter 0"]
152    #[inline(always)]
153    pub fn adc0(self) -> &'a mut W {
154        self.variant(SOURCESEL_A::ADC0)
155    }
156    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
157    #[inline(always)]
158    pub fn usart0(self) -> &'a mut W {
159        self.variant(SOURCESEL_A::USART0)
160    }
161    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
162    #[inline(always)]
163    pub fn usart1(self) -> &'a mut W {
164        self.variant(SOURCESEL_A::USART1)
165    }
166    #[doc = "Low Energy UART 0"]
167    #[inline(always)]
168    pub fn leuart0(self) -> &'a mut W {
169        self.variant(SOURCESEL_A::LEUART0)
170    }
171    #[doc = "I2C 0"]
172    #[inline(always)]
173    pub fn i2c0(self) -> &'a mut W {
174        self.variant(SOURCESEL_A::I2C0)
175    }
176    #[doc = "Timer 0"]
177    #[inline(always)]
178    pub fn timer0(self) -> &'a mut W {
179        self.variant(SOURCESEL_A::TIMER0)
180    }
181    #[doc = "Timer 1"]
182    #[inline(always)]
183    pub fn timer1(self) -> &'a mut W {
184        self.variant(SOURCESEL_A::TIMER1)
185    }
186    #[doc = "Timer 2"]
187    #[inline(always)]
188    pub fn timer2(self) -> &'a mut W {
189        self.variant(SOURCESEL_A::TIMER2)
190    }
191    #[doc = "`110000`"]
192    #[inline(always)]
193    pub fn msc(self) -> &'a mut W {
194        self.variant(SOURCESEL_A::MSC)
195    }
196}
197impl R {
198    #[doc = "Bits 0:3 - Signal Select"]
199    #[inline(always)]
200    pub fn sigsel(&self) -> SIGSEL_R {
201        SIGSEL_R::new((self.bits & 0x0f) as u8)
202    }
203    #[doc = "Bits 16:21 - Source Select"]
204    #[inline(always)]
205    pub fn sourcesel(&self) -> SOURCESEL_R {
206        SOURCESEL_R::new(((self.bits >> 16) & 0x3f) as u8)
207    }
208}
209impl W {
210    #[doc = "Bits 0:3 - Signal Select"]
211    #[inline(always)]
212    pub fn sigsel(&mut self) -> SIGSEL_W {
213        SIGSEL_W::new(self)
214    }
215    #[doc = "Bits 16:21 - Source Select"]
216    #[inline(always)]
217    pub fn sourcesel(&mut self) -> SOURCESEL_W {
218        SOURCESEL_W::new(self)
219    }
220    #[doc = "Writes raw bits to the register."]
221    #[inline(always)]
222    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
223        self.0.bits(bits);
224        self
225    }
226}
227#[doc = "Channel Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch2_ctrl](index.html) module"]
228pub struct CH2_CTRL_SPEC;
229impl crate::RegisterSpec for CH2_CTRL_SPEC {
230    type Ux = u32;
231}
232#[doc = "`read()` method returns [ch2_ctrl::R](R) reader structure"]
233impl crate::Readable for CH2_CTRL_SPEC {
234    type Reader = R;
235}
236#[doc = "`write(|w| ..)` method takes [ch2_ctrl::W](W) writer structure"]
237impl crate::Writable for CH2_CTRL_SPEC {
238    type Writer = W;
239}
240#[doc = "`reset()` method sets CH2_CTRL to value 0"]
241impl crate::Resettable for CH2_CTRL_SPEC {
242    #[inline(always)]
243    fn reset_value() -> Self::Ux {
244        0
245    }
246}
efm32hg321_pac/dma/ch2_ctrl.rs

efm32hg321_pac/dma/
ch2_ctrl.rs
