efm32hg310_pac/usb/
diep1_int.rs

1#[doc = "Register `DIEP1_INT` reader"]
2pub struct R(crate::R<DIEP1_INT_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DIEP1_INT_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DIEP1_INT_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DIEP1_INT_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `DIEP1_INT` writer"]
17pub struct W(crate::W<DIEP1_INT_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DIEP1_INT_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DIEP1_INT_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DIEP1_INT_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `XFERCOMPL` reader - Transfer Completed Interrupt"]
38pub type XFERCOMPL_R = crate::BitReader<bool>;
39#[doc = "Field `XFERCOMPL` writer - Transfer Completed Interrupt"]
40pub type XFERCOMPL_W<'a> = crate::BitWriter<'a, u32, DIEP1_INT_SPEC, bool, 0>;
41#[doc = "Field `EPDISBLD` reader - Endpoint Disabled Interrupt"]
42pub type EPDISBLD_R = crate::BitReader<bool>;
43#[doc = "Field `EPDISBLD` writer - Endpoint Disabled Interrupt"]
44pub type EPDISBLD_W<'a> = crate::BitWriter<'a, u32, DIEP1_INT_SPEC, bool, 1>;
45#[doc = "Field `AHBERR` reader - AHB Error"]
46pub type AHBERR_R = crate::BitReader<bool>;
47#[doc = "Field `AHBERR` writer - AHB Error"]
48pub type AHBERR_W<'a> = crate::BitWriter<'a, u32, DIEP1_INT_SPEC, bool, 2>;
49#[doc = "Field `TIMEOUT` reader - Timeout Condition"]
50pub type TIMEOUT_R = crate::BitReader<bool>;
51#[doc = "Field `TIMEOUT` writer - Timeout Condition"]
52pub type TIMEOUT_W<'a> = crate::BitWriter<'a, u32, DIEP1_INT_SPEC, bool, 3>;
53#[doc = "Field `INTKNTXFEMP` reader - IN Token Received When TxFIFO is Empty"]
54pub type INTKNTXFEMP_R = crate::BitReader<bool>;
55#[doc = "Field `INTKNTXFEMP` writer - IN Token Received When TxFIFO is Empty"]
56pub type INTKNTXFEMP_W<'a> = crate::BitWriter<'a, u32, DIEP1_INT_SPEC, bool, 4>;
57#[doc = "Field `INEPNAKEFF` reader - IN Endpoint NAK Effective"]
58pub type INEPNAKEFF_R = crate::BitReader<bool>;
59#[doc = "Field `INEPNAKEFF` writer - IN Endpoint NAK Effective"]
60pub type INEPNAKEFF_W<'a> = crate::BitWriter<'a, u32, DIEP1_INT_SPEC, bool, 6>;
61#[doc = "Field `TXFEMP` reader - Transmit FIFO Empty"]
62pub type TXFEMP_R = crate::BitReader<bool>;
63#[doc = "Field `PKTDRPSTS` reader - Packet Drop Status"]
64pub type PKTDRPSTS_R = crate::BitReader<bool>;
65#[doc = "Field `PKTDRPSTS` writer - Packet Drop Status"]
66pub type PKTDRPSTS_W<'a> = crate::BitWriter<'a, u32, DIEP1_INT_SPEC, bool, 11>;
67#[doc = "Field `BBLEERR` reader - NAK Interrupt"]
68pub type BBLEERR_R = crate::BitReader<bool>;
69#[doc = "Field `BBLEERR` writer - NAK Interrupt"]
70pub type BBLEERR_W<'a> = crate::BitWriter<'a, u32, DIEP1_INT_SPEC, bool, 12>;
71#[doc = "Field `NAKINTRPT` reader - NAK Interrupt"]
72pub type NAKINTRPT_R = crate::BitReader<bool>;
73#[doc = "Field `NAKINTRPT` writer - NAK Interrupt"]
74pub type NAKINTRPT_W<'a> = crate::BitWriter<'a, u32, DIEP1_INT_SPEC, bool, 13>;
75impl R {
76    #[doc = "Bit 0 - Transfer Completed Interrupt"]
77    #[inline(always)]
78    pub fn xfercompl(&self) -> XFERCOMPL_R {
79        XFERCOMPL_R::new((self.bits & 1) != 0)
80    }
81    #[doc = "Bit 1 - Endpoint Disabled Interrupt"]
82    #[inline(always)]
83    pub fn epdisbld(&self) -> EPDISBLD_R {
84        EPDISBLD_R::new(((self.bits >> 1) & 1) != 0)
85    }
86    #[doc = "Bit 2 - AHB Error"]
87    #[inline(always)]
88    pub fn ahberr(&self) -> AHBERR_R {
89        AHBERR_R::new(((self.bits >> 2) & 1) != 0)
90    }
91    #[doc = "Bit 3 - Timeout Condition"]
92    #[inline(always)]
93    pub fn timeout(&self) -> TIMEOUT_R {
94        TIMEOUT_R::new(((self.bits >> 3) & 1) != 0)
95    }
96    #[doc = "Bit 4 - IN Token Received When TxFIFO is Empty"]
97    #[inline(always)]
98    pub fn intkntxfemp(&self) -> INTKNTXFEMP_R {
99        INTKNTXFEMP_R::new(((self.bits >> 4) & 1) != 0)
100    }
101    #[doc = "Bit 6 - IN Endpoint NAK Effective"]
102    #[inline(always)]
103    pub fn inepnakeff(&self) -> INEPNAKEFF_R {
104        INEPNAKEFF_R::new(((self.bits >> 6) & 1) != 0)
105    }
106    #[doc = "Bit 7 - Transmit FIFO Empty"]
107    #[inline(always)]
108    pub fn txfemp(&self) -> TXFEMP_R {
109        TXFEMP_R::new(((self.bits >> 7) & 1) != 0)
110    }
111    #[doc = "Bit 11 - Packet Drop Status"]
112    #[inline(always)]
113    pub fn pktdrpsts(&self) -> PKTDRPSTS_R {
114        PKTDRPSTS_R::new(((self.bits >> 11) & 1) != 0)
115    }
116    #[doc = "Bit 12 - NAK Interrupt"]
117    #[inline(always)]
118    pub fn bbleerr(&self) -> BBLEERR_R {
119        BBLEERR_R::new(((self.bits >> 12) & 1) != 0)
120    }
121    #[doc = "Bit 13 - NAK Interrupt"]
122    #[inline(always)]
123    pub fn nakintrpt(&self) -> NAKINTRPT_R {
124        NAKINTRPT_R::new(((self.bits >> 13) & 1) != 0)
125    }
126}
127impl W {
128    #[doc = "Bit 0 - Transfer Completed Interrupt"]
129    #[inline(always)]
130    pub fn xfercompl(&mut self) -> XFERCOMPL_W {
131        XFERCOMPL_W::new(self)
132    }
133    #[doc = "Bit 1 - Endpoint Disabled Interrupt"]
134    #[inline(always)]
135    pub fn epdisbld(&mut self) -> EPDISBLD_W {
136        EPDISBLD_W::new(self)
137    }
138    #[doc = "Bit 2 - AHB Error"]
139    #[inline(always)]
140    pub fn ahberr(&mut self) -> AHBERR_W {
141        AHBERR_W::new(self)
142    }
143    #[doc = "Bit 3 - Timeout Condition"]
144    #[inline(always)]
145    pub fn timeout(&mut self) -> TIMEOUT_W {
146        TIMEOUT_W::new(self)
147    }
148    #[doc = "Bit 4 - IN Token Received When TxFIFO is Empty"]
149    #[inline(always)]
150    pub fn intkntxfemp(&mut self) -> INTKNTXFEMP_W {
151        INTKNTXFEMP_W::new(self)
152    }
153    #[doc = "Bit 6 - IN Endpoint NAK Effective"]
154    #[inline(always)]
155    pub fn inepnakeff(&mut self) -> INEPNAKEFF_W {
156        INEPNAKEFF_W::new(self)
157    }
158    #[doc = "Bit 11 - Packet Drop Status"]
159    #[inline(always)]
160    pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W {
161        PKTDRPSTS_W::new(self)
162    }
163    #[doc = "Bit 12 - NAK Interrupt"]
164    #[inline(always)]
165    pub fn bbleerr(&mut self) -> BBLEERR_W {
166        BBLEERR_W::new(self)
167    }
168    #[doc = "Bit 13 - NAK Interrupt"]
169    #[inline(always)]
170    pub fn nakintrpt(&mut self) -> NAKINTRPT_W {
171        NAKINTRPT_W::new(self)
172    }
173    #[doc = "Writes raw bits to the register."]
174    #[inline(always)]
175    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
176        self.0.bits(bits);
177        self
178    }
179}
180#[doc = "Device IN Endpoint x+1 Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diep1_int](index.html) module"]
181pub struct DIEP1_INT_SPEC;
182impl crate::RegisterSpec for DIEP1_INT_SPEC {
183    type Ux = u32;
184}
185#[doc = "`read()` method returns [diep1_int::R](R) reader structure"]
186impl crate::Readable for DIEP1_INT_SPEC {
187    type Reader = R;
188}
189#[doc = "`write(|w| ..)` method takes [diep1_int::W](W) writer structure"]
190impl crate::Writable for DIEP1_INT_SPEC {
191    type Writer = W;
192}
193#[doc = "`reset()` method sets DIEP1_INT to value 0x80"]
194impl crate::Resettable for DIEP1_INT_SPEC {
195    #[inline(always)]
196    fn reset_value() -> Self::Ux {
197        0x80
198    }
199}
efm32hg310_pac/usb/diep1_int.rs

efm32hg310_pac/usb/
diep1_int.rs
