efm32hg310_pac/usb/
pcgcctl.rs

1#[doc = "Register `PCGCCTL` reader"]
2pub struct R(crate::R<PCGCCTL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<PCGCCTL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<PCGCCTL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<PCGCCTL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `PCGCCTL` writer"]
17pub struct W(crate::W<PCGCCTL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<PCGCCTL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<PCGCCTL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<PCGCCTL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `STOPPCLK` reader - Stop PHY clock"]
38pub type STOPPCLK_R = crate::BitReader<bool>;
39#[doc = "Field `STOPPCLK` writer - Stop PHY clock"]
40pub type STOPPCLK_W<'a> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, 0>;
41#[doc = "Field `GATEHCLK` reader - Gate HCLK"]
42pub type GATEHCLK_R = crate::BitReader<bool>;
43#[doc = "Field `GATEHCLK` writer - Gate HCLK"]
44pub type GATEHCLK_W<'a> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, 1>;
45#[doc = "Field `PWRCLMP` reader - Power Clamp"]
46pub type PWRCLMP_R = crate::BitReader<bool>;
47#[doc = "Field `PWRCLMP` writer - Power Clamp"]
48pub type PWRCLMP_W<'a> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, 2>;
49#[doc = "Field `RSTPDWNMODULE` reader - Reset Power-Down Modules"]
50pub type RSTPDWNMODULE_R = crate::BitReader<bool>;
51#[doc = "Field `RSTPDWNMODULE` writer - Reset Power-Down Modules"]
52pub type RSTPDWNMODULE_W<'a> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, 3>;
53#[doc = "Field `PHYSLEEP` reader - PHY In Sleep"]
54pub type PHYSLEEP_R = crate::BitReader<bool>;
55impl R {
56    #[doc = "Bit 0 - Stop PHY clock"]
57    #[inline(always)]
58    pub fn stoppclk(&self) -> STOPPCLK_R {
59        STOPPCLK_R::new((self.bits & 1) != 0)
60    }
61    #[doc = "Bit 1 - Gate HCLK"]
62    #[inline(always)]
63    pub fn gatehclk(&self) -> GATEHCLK_R {
64        GATEHCLK_R::new(((self.bits >> 1) & 1) != 0)
65    }
66    #[doc = "Bit 2 - Power Clamp"]
67    #[inline(always)]
68    pub fn pwrclmp(&self) -> PWRCLMP_R {
69        PWRCLMP_R::new(((self.bits >> 2) & 1) != 0)
70    }
71    #[doc = "Bit 3 - Reset Power-Down Modules"]
72    #[inline(always)]
73    pub fn rstpdwnmodule(&self) -> RSTPDWNMODULE_R {
74        RSTPDWNMODULE_R::new(((self.bits >> 3) & 1) != 0)
75    }
76    #[doc = "Bit 6 - PHY In Sleep"]
77    #[inline(always)]
78    pub fn physleep(&self) -> PHYSLEEP_R {
79        PHYSLEEP_R::new(((self.bits >> 6) & 1) != 0)
80    }
81}
82impl W {
83    #[doc = "Bit 0 - Stop PHY clock"]
84    #[inline(always)]
85    pub fn stoppclk(&mut self) -> STOPPCLK_W {
86        STOPPCLK_W::new(self)
87    }
88    #[doc = "Bit 1 - Gate HCLK"]
89    #[inline(always)]
90    pub fn gatehclk(&mut self) -> GATEHCLK_W {
91        GATEHCLK_W::new(self)
92    }
93    #[doc = "Bit 2 - Power Clamp"]
94    #[inline(always)]
95    pub fn pwrclmp(&mut self) -> PWRCLMP_W {
96        PWRCLMP_W::new(self)
97    }
98    #[doc = "Bit 3 - Reset Power-Down Modules"]
99    #[inline(always)]
100    pub fn rstpdwnmodule(&mut self) -> RSTPDWNMODULE_W {
101        RSTPDWNMODULE_W::new(self)
102    }
103    #[doc = "Writes raw bits to the register."]
104    #[inline(always)]
105    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
106        self.0.bits(bits);
107        self
108    }
109}
110#[doc = "Power and Clock Gating Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pcgcctl](index.html) module"]
111pub struct PCGCCTL_SPEC;
112impl crate::RegisterSpec for PCGCCTL_SPEC {
113    type Ux = u32;
114}
115#[doc = "`read()` method returns [pcgcctl::R](R) reader structure"]
116impl crate::Readable for PCGCCTL_SPEC {
117    type Reader = R;
118}
119#[doc = "`write(|w| ..)` method takes [pcgcctl::W](W) writer structure"]
120impl crate::Writable for PCGCCTL_SPEC {
121    type Writer = W;
122}
123#[doc = "`reset()` method sets PCGCCTL to value 0"]
124impl crate::Resettable for PCGCCTL_SPEC {
125    #[inline(always)]
126    fn reset_value() -> Self::Ux {
127        0
128    }
129}
efm32hg310_pac/usb/pcgcctl.rs

efm32hg310_pac/usb/
pcgcctl.rs
