efm32hg310_pac/usb/
doep0_int.rs

1#[doc = "Register `DOEP0_INT` reader"]
2pub struct R(crate::R<DOEP0_INT_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DOEP0_INT_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DOEP0_INT_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DOEP0_INT_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `DOEP0_INT` writer"]
17pub struct W(crate::W<DOEP0_INT_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DOEP0_INT_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DOEP0_INT_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DOEP0_INT_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `XFERCOMPL` reader - Transfer Completed Interrupt"]
38pub type XFERCOMPL_R = crate::BitReader<bool>;
39#[doc = "Field `XFERCOMPL` writer - Transfer Completed Interrupt"]
40pub type XFERCOMPL_W<'a> = crate::BitWriter<'a, u32, DOEP0_INT_SPEC, bool, 0>;
41#[doc = "Field `EPDISBLD` reader - Endpoint Disabled Interrupt"]
42pub type EPDISBLD_R = crate::BitReader<bool>;
43#[doc = "Field `EPDISBLD` writer - Endpoint Disabled Interrupt"]
44pub type EPDISBLD_W<'a> = crate::BitWriter<'a, u32, DOEP0_INT_SPEC, bool, 1>;
45#[doc = "Field `AHBERR` reader - AHB Error"]
46pub type AHBERR_R = crate::BitReader<bool>;
47#[doc = "Field `AHBERR` writer - AHB Error"]
48pub type AHBERR_W<'a> = crate::BitWriter<'a, u32, DOEP0_INT_SPEC, bool, 2>;
49#[doc = "Field `SETUP` reader - Setup Phase Done"]
50pub type SETUP_R = crate::BitReader<bool>;
51#[doc = "Field `SETUP` writer - Setup Phase Done"]
52pub type SETUP_W<'a> = crate::BitWriter<'a, u32, DOEP0_INT_SPEC, bool, 3>;
53#[doc = "Field `OUTTKNEPDIS` reader - OUT Token Received When Endpoint Disabled"]
54pub type OUTTKNEPDIS_R = crate::BitReader<bool>;
55#[doc = "Field `OUTTKNEPDIS` writer - OUT Token Received When Endpoint Disabled"]
56pub type OUTTKNEPDIS_W<'a> = crate::BitWriter<'a, u32, DOEP0_INT_SPEC, bool, 4>;
57#[doc = "Field `STSPHSERCVD` reader - Status Phase Received For Control Write"]
58pub type STSPHSERCVD_R = crate::BitReader<bool>;
59#[doc = "Field `STSPHSERCVD` writer - Status Phase Received For Control Write"]
60pub type STSPHSERCVD_W<'a> = crate::BitWriter<'a, u32, DOEP0_INT_SPEC, bool, 5>;
61#[doc = "Field `BACK2BACKSETUP` reader - Back-to-Back SETUP Packets Received"]
62pub type BACK2BACKSETUP_R = crate::BitReader<bool>;
63#[doc = "Field `BACK2BACKSETUP` writer - Back-to-Back SETUP Packets Received"]
64pub type BACK2BACKSETUP_W<'a> = crate::BitWriter<'a, u32, DOEP0_INT_SPEC, bool, 6>;
65#[doc = "Field `PKTDRPSTS` reader - Packet Drop Status"]
66pub type PKTDRPSTS_R = crate::BitReader<bool>;
67#[doc = "Field `PKTDRPSTS` writer - Packet Drop Status"]
68pub type PKTDRPSTS_W<'a> = crate::BitWriter<'a, u32, DOEP0_INT_SPEC, bool, 11>;
69#[doc = "Field `BBLEERR` reader - Babble Error"]
70pub type BBLEERR_R = crate::BitReader<bool>;
71#[doc = "Field `BBLEERR` writer - Babble Error"]
72pub type BBLEERR_W<'a> = crate::BitWriter<'a, u32, DOEP0_INT_SPEC, bool, 12>;
73#[doc = "Field `NAKINTRPT` reader - NAK Interrupt"]
74pub type NAKINTRPT_R = crate::BitReader<bool>;
75#[doc = "Field `NAKINTRPT` writer - NAK Interrupt"]
76pub type NAKINTRPT_W<'a> = crate::BitWriter<'a, u32, DOEP0_INT_SPEC, bool, 13>;
77#[doc = "Field `STUPPKTRCVD` reader - Setup Packet Received"]
78pub type STUPPKTRCVD_R = crate::BitReader<bool>;
79#[doc = "Field `STUPPKTRCVD` writer - Setup Packet Received"]
80pub type STUPPKTRCVD_W<'a> = crate::BitWriter<'a, u32, DOEP0_INT_SPEC, bool, 15>;
81impl R {
82    #[doc = "Bit 0 - Transfer Completed Interrupt"]
83    #[inline(always)]
84    pub fn xfercompl(&self) -> XFERCOMPL_R {
85        XFERCOMPL_R::new((self.bits & 1) != 0)
86    }
87    #[doc = "Bit 1 - Endpoint Disabled Interrupt"]
88    #[inline(always)]
89    pub fn epdisbld(&self) -> EPDISBLD_R {
90        EPDISBLD_R::new(((self.bits >> 1) & 1) != 0)
91    }
92    #[doc = "Bit 2 - AHB Error"]
93    #[inline(always)]
94    pub fn ahberr(&self) -> AHBERR_R {
95        AHBERR_R::new(((self.bits >> 2) & 1) != 0)
96    }
97    #[doc = "Bit 3 - Setup Phase Done"]
98    #[inline(always)]
99    pub fn setup(&self) -> SETUP_R {
100        SETUP_R::new(((self.bits >> 3) & 1) != 0)
101    }
102    #[doc = "Bit 4 - OUT Token Received When Endpoint Disabled"]
103    #[inline(always)]
104    pub fn outtknepdis(&self) -> OUTTKNEPDIS_R {
105        OUTTKNEPDIS_R::new(((self.bits >> 4) & 1) != 0)
106    }
107    #[doc = "Bit 5 - Status Phase Received For Control Write"]
108    #[inline(always)]
109    pub fn stsphsercvd(&self) -> STSPHSERCVD_R {
110        STSPHSERCVD_R::new(((self.bits >> 5) & 1) != 0)
111    }
112    #[doc = "Bit 6 - Back-to-Back SETUP Packets Received"]
113    #[inline(always)]
114    pub fn back2backsetup(&self) -> BACK2BACKSETUP_R {
115        BACK2BACKSETUP_R::new(((self.bits >> 6) & 1) != 0)
116    }
117    #[doc = "Bit 11 - Packet Drop Status"]
118    #[inline(always)]
119    pub fn pktdrpsts(&self) -> PKTDRPSTS_R {
120        PKTDRPSTS_R::new(((self.bits >> 11) & 1) != 0)
121    }
122    #[doc = "Bit 12 - Babble Error"]
123    #[inline(always)]
124    pub fn bbleerr(&self) -> BBLEERR_R {
125        BBLEERR_R::new(((self.bits >> 12) & 1) != 0)
126    }
127    #[doc = "Bit 13 - NAK Interrupt"]
128    #[inline(always)]
129    pub fn nakintrpt(&self) -> NAKINTRPT_R {
130        NAKINTRPT_R::new(((self.bits >> 13) & 1) != 0)
131    }
132    #[doc = "Bit 15 - Setup Packet Received"]
133    #[inline(always)]
134    pub fn stuppktrcvd(&self) -> STUPPKTRCVD_R {
135        STUPPKTRCVD_R::new(((self.bits >> 15) & 1) != 0)
136    }
137}
138impl W {
139    #[doc = "Bit 0 - Transfer Completed Interrupt"]
140    #[inline(always)]
141    pub fn xfercompl(&mut self) -> XFERCOMPL_W {
142        XFERCOMPL_W::new(self)
143    }
144    #[doc = "Bit 1 - Endpoint Disabled Interrupt"]
145    #[inline(always)]
146    pub fn epdisbld(&mut self) -> EPDISBLD_W {
147        EPDISBLD_W::new(self)
148    }
149    #[doc = "Bit 2 - AHB Error"]
150    #[inline(always)]
151    pub fn ahberr(&mut self) -> AHBERR_W {
152        AHBERR_W::new(self)
153    }
154    #[doc = "Bit 3 - Setup Phase Done"]
155    #[inline(always)]
156    pub fn setup(&mut self) -> SETUP_W {
157        SETUP_W::new(self)
158    }
159    #[doc = "Bit 4 - OUT Token Received When Endpoint Disabled"]
160    #[inline(always)]
161    pub fn outtknepdis(&mut self) -> OUTTKNEPDIS_W {
162        OUTTKNEPDIS_W::new(self)
163    }
164    #[doc = "Bit 5 - Status Phase Received For Control Write"]
165    #[inline(always)]
166    pub fn stsphsercvd(&mut self) -> STSPHSERCVD_W {
167        STSPHSERCVD_W::new(self)
168    }
169    #[doc = "Bit 6 - Back-to-Back SETUP Packets Received"]
170    #[inline(always)]
171    pub fn back2backsetup(&mut self) -> BACK2BACKSETUP_W {
172        BACK2BACKSETUP_W::new(self)
173    }
174    #[doc = "Bit 11 - Packet Drop Status"]
175    #[inline(always)]
176    pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W {
177        PKTDRPSTS_W::new(self)
178    }
179    #[doc = "Bit 12 - Babble Error"]
180    #[inline(always)]
181    pub fn bbleerr(&mut self) -> BBLEERR_W {
182        BBLEERR_W::new(self)
183    }
184    #[doc = "Bit 13 - NAK Interrupt"]
185    #[inline(always)]
186    pub fn nakintrpt(&mut self) -> NAKINTRPT_W {
187        NAKINTRPT_W::new(self)
188    }
189    #[doc = "Bit 15 - Setup Packet Received"]
190    #[inline(always)]
191    pub fn stuppktrcvd(&mut self) -> STUPPKTRCVD_W {
192        STUPPKTRCVD_W::new(self)
193    }
194    #[doc = "Writes raw bits to the register."]
195    #[inline(always)]
196    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
197        self.0.bits(bits);
198        self
199    }
200}
201#[doc = "Device OUT Endpoint x+1 Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doep0_int](index.html) module"]
202pub struct DOEP0_INT_SPEC;
203impl crate::RegisterSpec for DOEP0_INT_SPEC {
204    type Ux = u32;
205}
206#[doc = "`read()` method returns [doep0_int::R](R) reader structure"]
207impl crate::Readable for DOEP0_INT_SPEC {
208    type Reader = R;
209}
210#[doc = "`write(|w| ..)` method takes [doep0_int::W](W) writer structure"]
211impl crate::Writable for DOEP0_INT_SPEC {
212    type Writer = W;
213}
214#[doc = "`reset()` method sets DOEP0_INT to value 0"]
215impl crate::Resettable for DOEP0_INT_SPEC {
216    #[inline(always)]
217    fn reset_value() -> Self::Ux {
218        0
219    }
220}
efm32hg310_pac/usb/doep0_int.rs

efm32hg310_pac/usb/
doep0_int.rs
