efm32hg310_pac/prs/
ch1_ctrl.rs

1#[doc = "Register `CH1_CTRL` reader"]
2pub struct R(crate::R<CH1_CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CH1_CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CH1_CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CH1_CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CH1_CTRL` writer"]
17pub struct W(crate::W<CH1_CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CH1_CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CH1_CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CH1_CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SIGSEL` reader - Signal Select"]
38pub type SIGSEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `SIGSEL` writer - Signal Select"]
40pub type SIGSEL_W<'a> = crate::FieldWriter<'a, u32, CH1_CTRL_SPEC, u8, u8, 3, 0>;
41#[doc = "Source Select\n\nValue on reset: 0"]
42#[derive(Clone, Copy, Debug, PartialEq)]
43#[repr(u8)]
44pub enum SOURCESEL_A {
45    #[doc = "0: No source selected"]
46    NONE = 0,
47    #[doc = "1: Voltage Comparator"]
48    VCMP = 1,
49    #[doc = "2: Analog Comparator 0"]
50    ACMP0 = 2,
51    #[doc = "8: Analog to Digital Converter 0"]
52    ADC0 = 8,
53    #[doc = "16: Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
54    USART0 = 16,
55    #[doc = "17: Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
56    USART1 = 17,
57    #[doc = "28: Timer 0"]
58    TIMER0 = 28,
59    #[doc = "29: Timer 1"]
60    TIMER1 = 29,
61    #[doc = "30: Timer 2"]
62    TIMER2 = 30,
63    #[doc = "36: Universal Serial Bus Interface"]
64    USB = 36,
65    #[doc = "40: Real-Time Counter"]
66    RTC = 40,
67    #[doc = "48: General purpose Input/Output"]
68    GPIOL = 48,
69    #[doc = "49: General purpose Input/Output"]
70    GPIOH = 49,
71    #[doc = "54: Pulse Counter 0"]
72    PCNT0 = 54,
73}
74impl From<SOURCESEL_A> for u8 {
75    #[inline(always)]
76    fn from(variant: SOURCESEL_A) -> Self {
77        variant as _
78    }
79}
80#[doc = "Field `SOURCESEL` reader - Source Select"]
81pub type SOURCESEL_R = crate::FieldReader<u8, SOURCESEL_A>;
82impl SOURCESEL_R {
83    #[doc = "Get enumerated values variant"]
84    #[inline(always)]
85    pub fn variant(&self) -> Option<SOURCESEL_A> {
86        match self.bits {
87            0 => Some(SOURCESEL_A::NONE),
88            1 => Some(SOURCESEL_A::VCMP),
89            2 => Some(SOURCESEL_A::ACMP0),
90            8 => Some(SOURCESEL_A::ADC0),
91            16 => Some(SOURCESEL_A::USART0),
92            17 => Some(SOURCESEL_A::USART1),
93            28 => Some(SOURCESEL_A::TIMER0),
94            29 => Some(SOURCESEL_A::TIMER1),
95            30 => Some(SOURCESEL_A::TIMER2),
96            36 => Some(SOURCESEL_A::USB),
97            40 => Some(SOURCESEL_A::RTC),
98            48 => Some(SOURCESEL_A::GPIOL),
99            49 => Some(SOURCESEL_A::GPIOH),
100            54 => Some(SOURCESEL_A::PCNT0),
101            _ => None,
102        }
103    }
104    #[doc = "Checks if the value of the field is `NONE`"]
105    #[inline(always)]
106    pub fn is_none(&self) -> bool {
107        *self == SOURCESEL_A::NONE
108    }
109    #[doc = "Checks if the value of the field is `VCMP`"]
110    #[inline(always)]
111    pub fn is_vcmp(&self) -> bool {
112        *self == SOURCESEL_A::VCMP
113    }
114    #[doc = "Checks if the value of the field is `ACMP0`"]
115    #[inline(always)]
116    pub fn is_acmp0(&self) -> bool {
117        *self == SOURCESEL_A::ACMP0
118    }
119    #[doc = "Checks if the value of the field is `ADC0`"]
120    #[inline(always)]
121    pub fn is_adc0(&self) -> bool {
122        *self == SOURCESEL_A::ADC0
123    }
124    #[doc = "Checks if the value of the field is `USART0`"]
125    #[inline(always)]
126    pub fn is_usart0(&self) -> bool {
127        *self == SOURCESEL_A::USART0
128    }
129    #[doc = "Checks if the value of the field is `USART1`"]
130    #[inline(always)]
131    pub fn is_usart1(&self) -> bool {
132        *self == SOURCESEL_A::USART1
133    }
134    #[doc = "Checks if the value of the field is `TIMER0`"]
135    #[inline(always)]
136    pub fn is_timer0(&self) -> bool {
137        *self == SOURCESEL_A::TIMER0
138    }
139    #[doc = "Checks if the value of the field is `TIMER1`"]
140    #[inline(always)]
141    pub fn is_timer1(&self) -> bool {
142        *self == SOURCESEL_A::TIMER1
143    }
144    #[doc = "Checks if the value of the field is `TIMER2`"]
145    #[inline(always)]
146    pub fn is_timer2(&self) -> bool {
147        *self == SOURCESEL_A::TIMER2
148    }
149    #[doc = "Checks if the value of the field is `USB`"]
150    #[inline(always)]
151    pub fn is_usb(&self) -> bool {
152        *self == SOURCESEL_A::USB
153    }
154    #[doc = "Checks if the value of the field is `RTC`"]
155    #[inline(always)]
156    pub fn is_rtc(&self) -> bool {
157        *self == SOURCESEL_A::RTC
158    }
159    #[doc = "Checks if the value of the field is `GPIOL`"]
160    #[inline(always)]
161    pub fn is_gpiol(&self) -> bool {
162        *self == SOURCESEL_A::GPIOL
163    }
164    #[doc = "Checks if the value of the field is `GPIOH`"]
165    #[inline(always)]
166    pub fn is_gpioh(&self) -> bool {
167        *self == SOURCESEL_A::GPIOH
168    }
169    #[doc = "Checks if the value of the field is `PCNT0`"]
170    #[inline(always)]
171    pub fn is_pcnt0(&self) -> bool {
172        *self == SOURCESEL_A::PCNT0
173    }
174}
175#[doc = "Field `SOURCESEL` writer - Source Select"]
176pub type SOURCESEL_W<'a> = crate::FieldWriter<'a, u32, CH1_CTRL_SPEC, u8, SOURCESEL_A, 6, 16>;
177impl<'a> SOURCESEL_W<'a> {
178    #[doc = "No source selected"]
179    #[inline(always)]
180    pub fn none(self) -> &'a mut W {
181        self.variant(SOURCESEL_A::NONE)
182    }
183    #[doc = "Voltage Comparator"]
184    #[inline(always)]
185    pub fn vcmp(self) -> &'a mut W {
186        self.variant(SOURCESEL_A::VCMP)
187    }
188    #[doc = "Analog Comparator 0"]
189    #[inline(always)]
190    pub fn acmp0(self) -> &'a mut W {
191        self.variant(SOURCESEL_A::ACMP0)
192    }
193    #[doc = "Analog to Digital Converter 0"]
194    #[inline(always)]
195    pub fn adc0(self) -> &'a mut W {
196        self.variant(SOURCESEL_A::ADC0)
197    }
198    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
199    #[inline(always)]
200    pub fn usart0(self) -> &'a mut W {
201        self.variant(SOURCESEL_A::USART0)
202    }
203    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
204    #[inline(always)]
205    pub fn usart1(self) -> &'a mut W {
206        self.variant(SOURCESEL_A::USART1)
207    }
208    #[doc = "Timer 0"]
209    #[inline(always)]
210    pub fn timer0(self) -> &'a mut W {
211        self.variant(SOURCESEL_A::TIMER0)
212    }
213    #[doc = "Timer 1"]
214    #[inline(always)]
215    pub fn timer1(self) -> &'a mut W {
216        self.variant(SOURCESEL_A::TIMER1)
217    }
218    #[doc = "Timer 2"]
219    #[inline(always)]
220    pub fn timer2(self) -> &'a mut W {
221        self.variant(SOURCESEL_A::TIMER2)
222    }
223    #[doc = "Universal Serial Bus Interface"]
224    #[inline(always)]
225    pub fn usb(self) -> &'a mut W {
226        self.variant(SOURCESEL_A::USB)
227    }
228    #[doc = "Real-Time Counter"]
229    #[inline(always)]
230    pub fn rtc(self) -> &'a mut W {
231        self.variant(SOURCESEL_A::RTC)
232    }
233    #[doc = "General purpose Input/Output"]
234    #[inline(always)]
235    pub fn gpiol(self) -> &'a mut W {
236        self.variant(SOURCESEL_A::GPIOL)
237    }
238    #[doc = "General purpose Input/Output"]
239    #[inline(always)]
240    pub fn gpioh(self) -> &'a mut W {
241        self.variant(SOURCESEL_A::GPIOH)
242    }
243    #[doc = "Pulse Counter 0"]
244    #[inline(always)]
245    pub fn pcnt0(self) -> &'a mut W {
246        self.variant(SOURCESEL_A::PCNT0)
247    }
248}
249#[doc = "Edge Detect Select\n\nValue on reset: 0"]
250#[derive(Clone, Copy, Debug, PartialEq)]
251#[repr(u8)]
252pub enum EDSEL_A {
253    #[doc = "0: Signal is left as it is"]
254    OFF = 0,
255    #[doc = "1: A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal"]
256    POSEDGE = 1,
257    #[doc = "2: A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
258    NEGEDGE = 2,
259    #[doc = "3: A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal"]
260    BOTHEDGES = 3,
261}
262impl From<EDSEL_A> for u8 {
263    #[inline(always)]
264    fn from(variant: EDSEL_A) -> Self {
265        variant as _
266    }
267}
268#[doc = "Field `EDSEL` reader - Edge Detect Select"]
269pub type EDSEL_R = crate::FieldReader<u8, EDSEL_A>;
270impl EDSEL_R {
271    #[doc = "Get enumerated values variant"]
272    #[inline(always)]
273    pub fn variant(&self) -> EDSEL_A {
274        match self.bits {
275            0 => EDSEL_A::OFF,
276            1 => EDSEL_A::POSEDGE,
277            2 => EDSEL_A::NEGEDGE,
278            3 => EDSEL_A::BOTHEDGES,
279            _ => unreachable!(),
280        }
281    }
282    #[doc = "Checks if the value of the field is `OFF`"]
283    #[inline(always)]
284    pub fn is_off(&self) -> bool {
285        *self == EDSEL_A::OFF
286    }
287    #[doc = "Checks if the value of the field is `POSEDGE`"]
288    #[inline(always)]
289    pub fn is_posedge(&self) -> bool {
290        *self == EDSEL_A::POSEDGE
291    }
292    #[doc = "Checks if the value of the field is `NEGEDGE`"]
293    #[inline(always)]
294    pub fn is_negedge(&self) -> bool {
295        *self == EDSEL_A::NEGEDGE
296    }
297    #[doc = "Checks if the value of the field is `BOTHEDGES`"]
298    #[inline(always)]
299    pub fn is_bothedges(&self) -> bool {
300        *self == EDSEL_A::BOTHEDGES
301    }
302}
303#[doc = "Field `EDSEL` writer - Edge Detect Select"]
304pub type EDSEL_W<'a> = crate::FieldWriterSafe<'a, u32, CH1_CTRL_SPEC, u8, EDSEL_A, 2, 24>;
305impl<'a> EDSEL_W<'a> {
306    #[doc = "Signal is left as it is"]
307    #[inline(always)]
308    pub fn off(self) -> &'a mut W {
309        self.variant(EDSEL_A::OFF)
310    }
311    #[doc = "A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal"]
312    #[inline(always)]
313    pub fn posedge(self) -> &'a mut W {
314        self.variant(EDSEL_A::POSEDGE)
315    }
316    #[doc = "A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
317    #[inline(always)]
318    pub fn negedge(self) -> &'a mut W {
319        self.variant(EDSEL_A::NEGEDGE)
320    }
321    #[doc = "A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal"]
322    #[inline(always)]
323    pub fn bothedges(self) -> &'a mut W {
324        self.variant(EDSEL_A::BOTHEDGES)
325    }
326}
327#[doc = "Field `ASYNC` reader - Asynchronous reflex"]
328pub type ASYNC_R = crate::BitReader<bool>;
329#[doc = "Field `ASYNC` writer - Asynchronous reflex"]
330pub type ASYNC_W<'a> = crate::BitWriter<'a, u32, CH1_CTRL_SPEC, bool, 28>;
331impl R {
332    #[doc = "Bits 0:2 - Signal Select"]
333    #[inline(always)]
334    pub fn sigsel(&self) -> SIGSEL_R {
335        SIGSEL_R::new((self.bits & 7) as u8)
336    }
337    #[doc = "Bits 16:21 - Source Select"]
338    #[inline(always)]
339    pub fn sourcesel(&self) -> SOURCESEL_R {
340        SOURCESEL_R::new(((self.bits >> 16) & 0x3f) as u8)
341    }
342    #[doc = "Bits 24:25 - Edge Detect Select"]
343    #[inline(always)]
344    pub fn edsel(&self) -> EDSEL_R {
345        EDSEL_R::new(((self.bits >> 24) & 3) as u8)
346    }
347    #[doc = "Bit 28 - Asynchronous reflex"]
348    #[inline(always)]
349    pub fn async_(&self) -> ASYNC_R {
350        ASYNC_R::new(((self.bits >> 28) & 1) != 0)
351    }
352}
353impl W {
354    #[doc = "Bits 0:2 - Signal Select"]
355    #[inline(always)]
356    pub fn sigsel(&mut self) -> SIGSEL_W {
357        SIGSEL_W::new(self)
358    }
359    #[doc = "Bits 16:21 - Source Select"]
360    #[inline(always)]
361    pub fn sourcesel(&mut self) -> SOURCESEL_W {
362        SOURCESEL_W::new(self)
363    }
364    #[doc = "Bits 24:25 - Edge Detect Select"]
365    #[inline(always)]
366    pub fn edsel(&mut self) -> EDSEL_W {
367        EDSEL_W::new(self)
368    }
369    #[doc = "Bit 28 - Asynchronous reflex"]
370    #[inline(always)]
371    pub fn async_(&mut self) -> ASYNC_W {
372        ASYNC_W::new(self)
373    }
374    #[doc = "Writes raw bits to the register."]
375    #[inline(always)]
376    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
377        self.0.bits(bits);
378        self
379    }
380}
381#[doc = "Channel Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch1_ctrl](index.html) module"]
382pub struct CH1_CTRL_SPEC;
383impl crate::RegisterSpec for CH1_CTRL_SPEC {
384    type Ux = u32;
385}
386#[doc = "`read()` method returns [ch1_ctrl::R](R) reader structure"]
387impl crate::Readable for CH1_CTRL_SPEC {
388    type Reader = R;
389}
390#[doc = "`write(|w| ..)` method takes [ch1_ctrl::W](W) writer structure"]
391impl crate::Writable for CH1_CTRL_SPEC {
392    type Writer = W;
393}
394#[doc = "`reset()` method sets CH1_CTRL to value 0"]
395impl crate::Resettable for CH1_CTRL_SPEC {
396    #[inline(always)]
397    fn reset_value() -> Self::Ux {
398        0
399    }
400}
efm32hg310_pac/prs/ch1_ctrl.rs

efm32hg310_pac/prs/
ch1_ctrl.rs
