efm32hg310_pac/mtb/
master.rs

1#[doc = "Register `MASTER` reader"]
2pub struct R(crate::R<MASTER_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<MASTER_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<MASTER_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<MASTER_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `MASTER` writer"]
17pub struct W(crate::W<MASTER_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<MASTER_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<MASTER_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<MASTER_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `MASK` reader - This value determines the maximum size of the trace buffer in SRAM."]
38pub type MASK_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `MASK` writer - This value determines the maximum size of the trace buffer in SRAM."]
40pub type MASK_W<'a> = crate::FieldWriter<'a, u32, MASTER_SPEC, u8, u8, 5, 0>;
41#[doc = "Field `TSTARTEN` reader - Trace start input enable."]
42pub type TSTARTEN_R = crate::BitReader<bool>;
43#[doc = "Field `TSTARTEN` writer - Trace start input enable."]
44pub type TSTARTEN_W<'a> = crate::BitWriter<'a, u32, MASTER_SPEC, bool, 5>;
45#[doc = "Field `TSTOPEN` reader - Trace stop input enable."]
46pub type TSTOPEN_R = crate::BitReader<bool>;
47#[doc = "Field `TSTOPEN` writer - Trace stop input enable."]
48pub type TSTOPEN_W<'a> = crate::BitWriter<'a, u32, MASTER_SPEC, bool, 6>;
49#[doc = "Field `HALTREQ` reader - Halt request bit."]
50pub type HALTREQ_R = crate::BitReader<bool>;
51#[doc = "Field `HALTREQ` writer - Halt request bit."]
52pub type HALTREQ_W<'a> = crate::BitWriter<'a, u32, MASTER_SPEC, bool, 9>;
53#[doc = "Field `EN` reader - Main trace enable bit."]
54pub type EN_R = crate::BitReader<bool>;
55#[doc = "Field `EN` writer - Main trace enable bit."]
56pub type EN_W<'a> = crate::BitWriter<'a, u32, MASTER_SPEC, bool, 31>;
57impl R {
58    #[doc = "Bits 0:4 - This value determines the maximum size of the trace buffer in SRAM."]
59    #[inline(always)]
60    pub fn mask(&self) -> MASK_R {
61        MASK_R::new((self.bits & 0x1f) as u8)
62    }
63    #[doc = "Bit 5 - Trace start input enable."]
64    #[inline(always)]
65    pub fn tstarten(&self) -> TSTARTEN_R {
66        TSTARTEN_R::new(((self.bits >> 5) & 1) != 0)
67    }
68    #[doc = "Bit 6 - Trace stop input enable."]
69    #[inline(always)]
70    pub fn tstopen(&self) -> TSTOPEN_R {
71        TSTOPEN_R::new(((self.bits >> 6) & 1) != 0)
72    }
73    #[doc = "Bit 9 - Halt request bit."]
74    #[inline(always)]
75    pub fn haltreq(&self) -> HALTREQ_R {
76        HALTREQ_R::new(((self.bits >> 9) & 1) != 0)
77    }
78    #[doc = "Bit 31 - Main trace enable bit."]
79    #[inline(always)]
80    pub fn en(&self) -> EN_R {
81        EN_R::new(((self.bits >> 31) & 1) != 0)
82    }
83}
84impl W {
85    #[doc = "Bits 0:4 - This value determines the maximum size of the trace buffer in SRAM."]
86    #[inline(always)]
87    pub fn mask(&mut self) -> MASK_W {
88        MASK_W::new(self)
89    }
90    #[doc = "Bit 5 - Trace start input enable."]
91    #[inline(always)]
92    pub fn tstarten(&mut self) -> TSTARTEN_W {
93        TSTARTEN_W::new(self)
94    }
95    #[doc = "Bit 6 - Trace stop input enable."]
96    #[inline(always)]
97    pub fn tstopen(&mut self) -> TSTOPEN_W {
98        TSTOPEN_W::new(self)
99    }
100    #[doc = "Bit 9 - Halt request bit."]
101    #[inline(always)]
102    pub fn haltreq(&mut self) -> HALTREQ_W {
103        HALTREQ_W::new(self)
104    }
105    #[doc = "Bit 31 - Main trace enable bit."]
106    #[inline(always)]
107    pub fn en(&mut self) -> EN_W {
108        EN_W::new(self)
109    }
110    #[doc = "Writes raw bits to the register."]
111    #[inline(always)]
112    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
113        self.0.bits(bits);
114        self
115    }
116}
117#[doc = "MTB Trace Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [master](index.html) module"]
118pub struct MASTER_SPEC;
119impl crate::RegisterSpec for MASTER_SPEC {
120    type Ux = u32;
121}
122#[doc = "`read()` method returns [master::R](R) reader structure"]
123impl crate::Readable for MASTER_SPEC {
124    type Reader = R;
125}
126#[doc = "`write(|w| ..)` method takes [master::W](W) writer structure"]
127impl crate::Writable for MASTER_SPEC {
128    type Writer = W;
129}
130#[doc = "`reset()` method sets MASTER to value 0"]
131impl crate::Resettable for MASTER_SPEC {
132    #[inline(always)]
133    fn reset_value() -> Self::Ux {
134        0
135    }
136}
efm32hg310_pac/mtb/master.rs

efm32hg310_pac/mtb/
master.rs
