efm32hg310_pac/cmu/
hfperclken0.rs1#[doc = "Register `HFPERCLKEN0` reader"]
2pub struct R(crate::R<HFPERCLKEN0_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<HFPERCLKEN0_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<HFPERCLKEN0_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<HFPERCLKEN0_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `HFPERCLKEN0` writer"]
17pub struct W(crate::W<HFPERCLKEN0_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<HFPERCLKEN0_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<HFPERCLKEN0_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<HFPERCLKEN0_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `TIMER0` reader - Timer 0 Clock Enable"]
38pub type TIMER0_R = crate::BitReader<bool>;
39#[doc = "Field `TIMER0` writer - Timer 0 Clock Enable"]
40pub type TIMER0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 0>;
41#[doc = "Field `TIMER1` reader - Timer 1 Clock Enable"]
42pub type TIMER1_R = crate::BitReader<bool>;
43#[doc = "Field `TIMER1` writer - Timer 1 Clock Enable"]
44pub type TIMER1_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 1>;
45#[doc = "Field `TIMER2` reader - Timer 2 Clock Enable"]
46pub type TIMER2_R = crate::BitReader<bool>;
47#[doc = "Field `TIMER2` writer - Timer 2 Clock Enable"]
48pub type TIMER2_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 2>;
49#[doc = "Field `USART0` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable"]
50pub type USART0_R = crate::BitReader<bool>;
51#[doc = "Field `USART0` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable"]
52pub type USART0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 3>;
53#[doc = "Field `USART1` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable"]
54pub type USART1_R = crate::BitReader<bool>;
55#[doc = "Field `USART1` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable"]
56pub type USART1_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 4>;
57#[doc = "Field `ACMP0` reader - Analog Comparator 0 Clock Enable"]
58pub type ACMP0_R = crate::BitReader<bool>;
59#[doc = "Field `ACMP0` writer - Analog Comparator 0 Clock Enable"]
60pub type ACMP0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 5>;
61#[doc = "Field `PRS` reader - Peripheral Reflex System Clock Enable"]
62pub type PRS_R = crate::BitReader<bool>;
63#[doc = "Field `PRS` writer - Peripheral Reflex System Clock Enable"]
64pub type PRS_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 6>;
65#[doc = "Field `IDAC0` reader - Current Digital to Analog Converter 0 Clock Enable"]
66pub type IDAC0_R = crate::BitReader<bool>;
67#[doc = "Field `IDAC0` writer - Current Digital to Analog Converter 0 Clock Enable"]
68pub type IDAC0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 7>;
69#[doc = "Field `GPIO` reader - General purpose Input/Output Clock Enable"]
70pub type GPIO_R = crate::BitReader<bool>;
71#[doc = "Field `GPIO` writer - General purpose Input/Output Clock Enable"]
72pub type GPIO_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 8>;
73#[doc = "Field `VCMP` reader - Voltage Comparator Clock Enable"]
74pub type VCMP_R = crate::BitReader<bool>;
75#[doc = "Field `VCMP` writer - Voltage Comparator Clock Enable"]
76pub type VCMP_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 9>;
77#[doc = "Field `ADC0` reader - Analog to Digital Converter 0 Clock Enable"]
78pub type ADC0_R = crate::BitReader<bool>;
79#[doc = "Field `ADC0` writer - Analog to Digital Converter 0 Clock Enable"]
80pub type ADC0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 10>;
81#[doc = "Field `I2C0` reader - I2C 0 Clock Enable"]
82pub type I2C0_R = crate::BitReader<bool>;
83#[doc = "Field `I2C0` writer - I2C 0 Clock Enable"]
84pub type I2C0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 11>;
85impl R {
86 #[doc = "Bit 0 - Timer 0 Clock Enable"]
87 #[inline(always)]
88 pub fn timer0(&self) -> TIMER0_R {
89 TIMER0_R::new((self.bits & 1) != 0)
90 }
91 #[doc = "Bit 1 - Timer 1 Clock Enable"]
92 #[inline(always)]
93 pub fn timer1(&self) -> TIMER1_R {
94 TIMER1_R::new(((self.bits >> 1) & 1) != 0)
95 }
96 #[doc = "Bit 2 - Timer 2 Clock Enable"]
97 #[inline(always)]
98 pub fn timer2(&self) -> TIMER2_R {
99 TIMER2_R::new(((self.bits >> 2) & 1) != 0)
100 }
101 #[doc = "Bit 3 - Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable"]
102 #[inline(always)]
103 pub fn usart0(&self) -> USART0_R {
104 USART0_R::new(((self.bits >> 3) & 1) != 0)
105 }
106 #[doc = "Bit 4 - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable"]
107 #[inline(always)]
108 pub fn usart1(&self) -> USART1_R {
109 USART1_R::new(((self.bits >> 4) & 1) != 0)
110 }
111 #[doc = "Bit 5 - Analog Comparator 0 Clock Enable"]
112 #[inline(always)]
113 pub fn acmp0(&self) -> ACMP0_R {
114 ACMP0_R::new(((self.bits >> 5) & 1) != 0)
115 }
116 #[doc = "Bit 6 - Peripheral Reflex System Clock Enable"]
117 #[inline(always)]
118 pub fn prs(&self) -> PRS_R {
119 PRS_R::new(((self.bits >> 6) & 1) != 0)
120 }
121 #[doc = "Bit 7 - Current Digital to Analog Converter 0 Clock Enable"]
122 #[inline(always)]
123 pub fn idac0(&self) -> IDAC0_R {
124 IDAC0_R::new(((self.bits >> 7) & 1) != 0)
125 }
126 #[doc = "Bit 8 - General purpose Input/Output Clock Enable"]
127 #[inline(always)]
128 pub fn gpio(&self) -> GPIO_R {
129 GPIO_R::new(((self.bits >> 8) & 1) != 0)
130 }
131 #[doc = "Bit 9 - Voltage Comparator Clock Enable"]
132 #[inline(always)]
133 pub fn vcmp(&self) -> VCMP_R {
134 VCMP_R::new(((self.bits >> 9) & 1) != 0)
135 }
136 #[doc = "Bit 10 - Analog to Digital Converter 0 Clock Enable"]
137 #[inline(always)]
138 pub fn adc0(&self) -> ADC0_R {
139 ADC0_R::new(((self.bits >> 10) & 1) != 0)
140 }
141 #[doc = "Bit 11 - I2C 0 Clock Enable"]
142 #[inline(always)]
143 pub fn i2c0(&self) -> I2C0_R {
144 I2C0_R::new(((self.bits >> 11) & 1) != 0)
145 }
146}
147impl W {
148 #[doc = "Bit 0 - Timer 0 Clock Enable"]
149 #[inline(always)]
150 pub fn timer0(&mut self) -> TIMER0_W {
151 TIMER0_W::new(self)
152 }
153 #[doc = "Bit 1 - Timer 1 Clock Enable"]
154 #[inline(always)]
155 pub fn timer1(&mut self) -> TIMER1_W {
156 TIMER1_W::new(self)
157 }
158 #[doc = "Bit 2 - Timer 2 Clock Enable"]
159 #[inline(always)]
160 pub fn timer2(&mut self) -> TIMER2_W {
161 TIMER2_W::new(self)
162 }
163 #[doc = "Bit 3 - Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable"]
164 #[inline(always)]
165 pub fn usart0(&mut self) -> USART0_W {
166 USART0_W::new(self)
167 }
168 #[doc = "Bit 4 - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable"]
169 #[inline(always)]
170 pub fn usart1(&mut self) -> USART1_W {
171 USART1_W::new(self)
172 }
173 #[doc = "Bit 5 - Analog Comparator 0 Clock Enable"]
174 #[inline(always)]
175 pub fn acmp0(&mut self) -> ACMP0_W {
176 ACMP0_W::new(self)
177 }
178 #[doc = "Bit 6 - Peripheral Reflex System Clock Enable"]
179 #[inline(always)]
180 pub fn prs(&mut self) -> PRS_W {
181 PRS_W::new(self)
182 }
183 #[doc = "Bit 7 - Current Digital to Analog Converter 0 Clock Enable"]
184 #[inline(always)]
185 pub fn idac0(&mut self) -> IDAC0_W {
186 IDAC0_W::new(self)
187 }
188 #[doc = "Bit 8 - General purpose Input/Output Clock Enable"]
189 #[inline(always)]
190 pub fn gpio(&mut self) -> GPIO_W {
191 GPIO_W::new(self)
192 }
193 #[doc = "Bit 9 - Voltage Comparator Clock Enable"]
194 #[inline(always)]
195 pub fn vcmp(&mut self) -> VCMP_W {
196 VCMP_W::new(self)
197 }
198 #[doc = "Bit 10 - Analog to Digital Converter 0 Clock Enable"]
199 #[inline(always)]
200 pub fn adc0(&mut self) -> ADC0_W {
201 ADC0_W::new(self)
202 }
203 #[doc = "Bit 11 - I2C 0 Clock Enable"]
204 #[inline(always)]
205 pub fn i2c0(&mut self) -> I2C0_W {
206 I2C0_W::new(self)
207 }
208 #[doc = "Writes raw bits to the register."]
209 #[inline(always)]
210 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
211 self.0.bits(bits);
212 self
213 }
214}
215#[doc = "High Frequency Peripheral Clock Enable Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfperclken0](index.html) module"]
216pub struct HFPERCLKEN0_SPEC;
217impl crate::RegisterSpec for HFPERCLKEN0_SPEC {
218 type Ux = u32;
219}
220#[doc = "`read()` method returns [hfperclken0::R](R) reader structure"]
221impl crate::Readable for HFPERCLKEN0_SPEC {
222 type Reader = R;
223}
224#[doc = "`write(|w| ..)` method takes [hfperclken0::W](W) writer structure"]
225impl crate::Writable for HFPERCLKEN0_SPEC {
226 type Writer = W;
227}
228#[doc = "`reset()` method sets HFPERCLKEN0 to value 0"]
229impl crate::Resettable for HFPERCLKEN0_SPEC {
230 #[inline(always)]
231 fn reset_value() -> Self::Ux {
232 0
233 }
234}