1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196
#[doc = "Reader of register READCTRL"] pub type R = crate::R<u32, super::READCTRL>; #[doc = "Writer for register READCTRL"] pub type W = crate::W<u32, super::READCTRL>; #[doc = "Register READCTRL `reset()`'s with value 0x01"] impl crate::ResetValue for super::READCTRL { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0x01 } } #[doc = "Read Mode\n\nValue on reset: 1"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum MODE_A { #[doc = "0: Zero wait-states inserted in fetch or read transfers."] WS0, #[doc = "1: One wait-state inserted for each fetch or read transfer. This mode is required for a core frequency above 16 MHz."] WS1, } impl From<MODE_A> for u8 { #[inline(always)] fn from(variant: MODE_A) -> Self { match variant { MODE_A::WS0 => 0, MODE_A::WS1 => 1, } } } #[doc = "Reader of field `MODE`"] pub type MODE_R = crate::R<u8, MODE_A>; impl MODE_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> crate::Variant<u8, MODE_A> { use crate::Variant::*; match self.bits { 0 => Val(MODE_A::WS0), 1 => Val(MODE_A::WS1), i => Res(i), } } #[doc = "Checks if the value of the field is `WS0`"] #[inline(always)] pub fn is_ws0(&self) -> bool { *self == MODE_A::WS0 } #[doc = "Checks if the value of the field is `WS1`"] #[inline(always)] pub fn is_ws1(&self) -> bool { *self == MODE_A::WS1 } } #[doc = "Write proxy for field `MODE`"] pub struct MODE_W<'a> { w: &'a mut W, } impl<'a> MODE_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: MODE_A) -> &'a mut W { unsafe { self.bits(variant.into()) } } #[doc = "Zero wait-states inserted in fetch or read transfers."] #[inline(always)] pub fn ws0(self) -> &'a mut W { self.variant(MODE_A::WS0) } #[doc = "One wait-state inserted for each fetch or read transfer. This mode is required for a core frequency above 16 MHz."] #[inline(always)] pub fn ws1(self) -> &'a mut W { self.variant(MODE_A::WS1) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07); self.w } } #[doc = "Reader of field `IFCDIS`"] pub type IFCDIS_R = crate::R<bool, bool>; #[doc = "Write proxy for field `IFCDIS`"] pub struct IFCDIS_W<'a> { w: &'a mut W, } impl<'a> IFCDIS_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); self.w } } #[doc = "Reader of field `AIDIS`"] pub type AIDIS_R = crate::R<bool, bool>; #[doc = "Write proxy for field `AIDIS`"] pub struct AIDIS_W<'a> { w: &'a mut W, } impl<'a> AIDIS_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4); self.w } } #[doc = "Reader of field `RAMCEN`"] pub type RAMCEN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `RAMCEN`"] pub struct RAMCEN_W<'a> { w: &'a mut W, } impl<'a> RAMCEN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7); self.w } } impl R { #[doc = "Bits 0:2 - Read Mode"] #[inline(always)] pub fn mode(&self) -> MODE_R { MODE_R::new((self.bits & 0x07) as u8) } #[doc = "Bit 3 - Internal Flash Cache Disable"] #[inline(always)] pub fn ifcdis(&self) -> IFCDIS_R { IFCDIS_R::new(((self.bits >> 3) & 0x01) != 0) } #[doc = "Bit 4 - Automatic Invalidate Disable"] #[inline(always)] pub fn aidis(&self) -> AIDIS_R { AIDIS_R::new(((self.bits >> 4) & 0x01) != 0) } #[doc = "Bit 7 - RAM Cache Enable"] #[inline(always)] pub fn ramcen(&self) -> RAMCEN_R { RAMCEN_R::new(((self.bits >> 7) & 0x01) != 0) } } impl W { #[doc = "Bits 0:2 - Read Mode"] #[inline(always)] pub fn mode(&mut self) -> MODE_W { MODE_W { w: self } } #[doc = "Bit 3 - Internal Flash Cache Disable"] #[inline(always)] pub fn ifcdis(&mut self) -> IFCDIS_W { IFCDIS_W { w: self } } #[doc = "Bit 4 - Automatic Invalidate Disable"] #[inline(always)] pub fn aidis(&mut self) -> AIDIS_W { AIDIS_W { w: self } } #[doc = "Bit 7 - RAM Cache Enable"] #[inline(always)] pub fn ramcen(&mut self) -> RAMCEN_W { RAMCEN_W { w: self } } }