efm32hg309_pac/dma/
ien.rs

1#[doc = "Register `IEN` reader"]
2pub struct R(crate::R<IEN_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<IEN_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<IEN_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<IEN_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `IEN` writer"]
17pub struct W(crate::W<IEN_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<IEN_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<IEN_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<IEN_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CH0DONE` reader - DMA Channel 0 Complete Interrupt Enable"]
38pub type CH0DONE_R = crate::BitReader<bool>;
39#[doc = "Field `CH0DONE` writer - DMA Channel 0 Complete Interrupt Enable"]
40pub type CH0DONE_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 0>;
41#[doc = "Field `CH1DONE` reader - DMA Channel 1 Complete Interrupt Enable"]
42pub type CH1DONE_R = crate::BitReader<bool>;
43#[doc = "Field `CH1DONE` writer - DMA Channel 1 Complete Interrupt Enable"]
44pub type CH1DONE_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 1>;
45#[doc = "Field `CH2DONE` reader - DMA Channel 2 Complete Interrupt Enable"]
46pub type CH2DONE_R = crate::BitReader<bool>;
47#[doc = "Field `CH2DONE` writer - DMA Channel 2 Complete Interrupt Enable"]
48pub type CH2DONE_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 2>;
49#[doc = "Field `CH3DONE` reader - DMA Channel 3 Complete Interrupt Enable"]
50pub type CH3DONE_R = crate::BitReader<bool>;
51#[doc = "Field `CH3DONE` writer - DMA Channel 3 Complete Interrupt Enable"]
52pub type CH3DONE_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 3>;
53#[doc = "Field `CH4DONE` reader - DMA Channel 4 Complete Interrupt Enable"]
54pub type CH4DONE_R = crate::BitReader<bool>;
55#[doc = "Field `CH4DONE` writer - DMA Channel 4 Complete Interrupt Enable"]
56pub type CH4DONE_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 4>;
57#[doc = "Field `CH5DONE` reader - DMA Channel 5 Complete Interrupt Enable"]
58pub type CH5DONE_R = crate::BitReader<bool>;
59#[doc = "Field `CH5DONE` writer - DMA Channel 5 Complete Interrupt Enable"]
60pub type CH5DONE_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 5>;
61#[doc = "Field `ERR` reader - DMA Error Interrupt Flag Enable"]
62pub type ERR_R = crate::BitReader<bool>;
63#[doc = "Field `ERR` writer - DMA Error Interrupt Flag Enable"]
64pub type ERR_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 31>;
65impl R {
66    #[doc = "Bit 0 - DMA Channel 0 Complete Interrupt Enable"]
67    #[inline(always)]
68    pub fn ch0done(&self) -> CH0DONE_R {
69        CH0DONE_R::new((self.bits & 1) != 0)
70    }
71    #[doc = "Bit 1 - DMA Channel 1 Complete Interrupt Enable"]
72    #[inline(always)]
73    pub fn ch1done(&self) -> CH1DONE_R {
74        CH1DONE_R::new(((self.bits >> 1) & 1) != 0)
75    }
76    #[doc = "Bit 2 - DMA Channel 2 Complete Interrupt Enable"]
77    #[inline(always)]
78    pub fn ch2done(&self) -> CH2DONE_R {
79        CH2DONE_R::new(((self.bits >> 2) & 1) != 0)
80    }
81    #[doc = "Bit 3 - DMA Channel 3 Complete Interrupt Enable"]
82    #[inline(always)]
83    pub fn ch3done(&self) -> CH3DONE_R {
84        CH3DONE_R::new(((self.bits >> 3) & 1) != 0)
85    }
86    #[doc = "Bit 4 - DMA Channel 4 Complete Interrupt Enable"]
87    #[inline(always)]
88    pub fn ch4done(&self) -> CH4DONE_R {
89        CH4DONE_R::new(((self.bits >> 4) & 1) != 0)
90    }
91    #[doc = "Bit 5 - DMA Channel 5 Complete Interrupt Enable"]
92    #[inline(always)]
93    pub fn ch5done(&self) -> CH5DONE_R {
94        CH5DONE_R::new(((self.bits >> 5) & 1) != 0)
95    }
96    #[doc = "Bit 31 - DMA Error Interrupt Flag Enable"]
97    #[inline(always)]
98    pub fn err(&self) -> ERR_R {
99        ERR_R::new(((self.bits >> 31) & 1) != 0)
100    }
101}
102impl W {
103    #[doc = "Bit 0 - DMA Channel 0 Complete Interrupt Enable"]
104    #[inline(always)]
105    pub fn ch0done(&mut self) -> CH0DONE_W {
106        CH0DONE_W::new(self)
107    }
108    #[doc = "Bit 1 - DMA Channel 1 Complete Interrupt Enable"]
109    #[inline(always)]
110    pub fn ch1done(&mut self) -> CH1DONE_W {
111        CH1DONE_W::new(self)
112    }
113    #[doc = "Bit 2 - DMA Channel 2 Complete Interrupt Enable"]
114    #[inline(always)]
115    pub fn ch2done(&mut self) -> CH2DONE_W {
116        CH2DONE_W::new(self)
117    }
118    #[doc = "Bit 3 - DMA Channel 3 Complete Interrupt Enable"]
119    #[inline(always)]
120    pub fn ch3done(&mut self) -> CH3DONE_W {
121        CH3DONE_W::new(self)
122    }
123    #[doc = "Bit 4 - DMA Channel 4 Complete Interrupt Enable"]
124    #[inline(always)]
125    pub fn ch4done(&mut self) -> CH4DONE_W {
126        CH4DONE_W::new(self)
127    }
128    #[doc = "Bit 5 - DMA Channel 5 Complete Interrupt Enable"]
129    #[inline(always)]
130    pub fn ch5done(&mut self) -> CH5DONE_W {
131        CH5DONE_W::new(self)
132    }
133    #[doc = "Bit 31 - DMA Error Interrupt Flag Enable"]
134    #[inline(always)]
135    pub fn err(&mut self) -> ERR_W {
136        ERR_W::new(self)
137    }
138    #[doc = "Writes raw bits to the register."]
139    #[inline(always)]
140    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
141        self.0.bits(bits);
142        self
143    }
144}
145#[doc = "Interrupt Enable register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ien](index.html) module"]
146pub struct IEN_SPEC;
147impl crate::RegisterSpec for IEN_SPEC {
148    type Ux = u32;
149}
150#[doc = "`read()` method returns [ien::R](R) reader structure"]
151impl crate::Readable for IEN_SPEC {
152    type Reader = R;
153}
154#[doc = "`write(|w| ..)` method takes [ien::W](W) writer structure"]
155impl crate::Writable for IEN_SPEC {
156    type Writer = W;
157}
158#[doc = "`reset()` method sets IEN to value 0"]
159impl crate::Resettable for IEN_SPEC {
160    #[inline(always)]
161    fn reset_value() -> Self::Ux {
162        0
163    }
164}
efm32hg309_pac/dma/ien.rs

efm32hg309_pac/dma/
ien.rs
