efm32hg309_pac/dma/
chsreqstatus.rs

1#[doc = "Register `CHSREQSTATUS` reader"]
2pub struct R(crate::R<CHSREQSTATUS_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CHSREQSTATUS_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CHSREQSTATUS_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CHSREQSTATUS_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `CH0SREQSTATUS` reader - Channel 0 Single Request Status"]
17pub type CH0SREQSTATUS_R = crate::BitReader<bool>;
18#[doc = "Field `CH1SREQSTATUS` reader - Channel 1 Single Request Status"]
19pub type CH1SREQSTATUS_R = crate::BitReader<bool>;
20#[doc = "Field `CH2SREQSTATUS` reader - Channel 2 Single Request Status"]
21pub type CH2SREQSTATUS_R = crate::BitReader<bool>;
22#[doc = "Field `CH3SREQSTATUS` reader - Channel 3 Single Request Status"]
23pub type CH3SREQSTATUS_R = crate::BitReader<bool>;
24#[doc = "Field `CH4SREQSTATUS` reader - Channel 4 Single Request Status"]
25pub type CH4SREQSTATUS_R = crate::BitReader<bool>;
26#[doc = "Field `CH5SREQSTATUS` reader - Channel 5 Single Request Status"]
27pub type CH5SREQSTATUS_R = crate::BitReader<bool>;
28impl R {
29    #[doc = "Bit 0 - Channel 0 Single Request Status"]
30    #[inline(always)]
31    pub fn ch0sreqstatus(&self) -> CH0SREQSTATUS_R {
32        CH0SREQSTATUS_R::new((self.bits & 1) != 0)
33    }
34    #[doc = "Bit 1 - Channel 1 Single Request Status"]
35    #[inline(always)]
36    pub fn ch1sreqstatus(&self) -> CH1SREQSTATUS_R {
37        CH1SREQSTATUS_R::new(((self.bits >> 1) & 1) != 0)
38    }
39    #[doc = "Bit 2 - Channel 2 Single Request Status"]
40    #[inline(always)]
41    pub fn ch2sreqstatus(&self) -> CH2SREQSTATUS_R {
42        CH2SREQSTATUS_R::new(((self.bits >> 2) & 1) != 0)
43    }
44    #[doc = "Bit 3 - Channel 3 Single Request Status"]
45    #[inline(always)]
46    pub fn ch3sreqstatus(&self) -> CH3SREQSTATUS_R {
47        CH3SREQSTATUS_R::new(((self.bits >> 3) & 1) != 0)
48    }
49    #[doc = "Bit 4 - Channel 4 Single Request Status"]
50    #[inline(always)]
51    pub fn ch4sreqstatus(&self) -> CH4SREQSTATUS_R {
52        CH4SREQSTATUS_R::new(((self.bits >> 4) & 1) != 0)
53    }
54    #[doc = "Bit 5 - Channel 5 Single Request Status"]
55    #[inline(always)]
56    pub fn ch5sreqstatus(&self) -> CH5SREQSTATUS_R {
57        CH5SREQSTATUS_R::new(((self.bits >> 5) & 1) != 0)
58    }
59}
60#[doc = "Channel Single Request Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chsreqstatus](index.html) module"]
61pub struct CHSREQSTATUS_SPEC;
62impl crate::RegisterSpec for CHSREQSTATUS_SPEC {
63    type Ux = u32;
64}
65#[doc = "`read()` method returns [chsreqstatus::R](R) reader structure"]
66impl crate::Readable for CHSREQSTATUS_SPEC {
67    type Reader = R;
68}
69#[doc = "`reset()` method sets CHSREQSTATUS to value 0"]
70impl crate::Resettable for CHSREQSTATUS_SPEC {
71    #[inline(always)]
72    fn reset_value() -> Self::Ux {
73        0
74    }
75}
efm32hg309_pac/dma/chsreqstatus.rs

efm32hg309_pac/dma/
chsreqstatus.rs
