efm32hg309_pac/dma/
ch1_ctrl.rs

1#[doc = "Register `CH1_CTRL` reader"]
2pub struct R(crate::R<CH1_CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CH1_CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CH1_CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CH1_CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CH1_CTRL` writer"]
17pub struct W(crate::W<CH1_CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CH1_CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CH1_CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CH1_CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SIGSEL` reader - Signal Select"]
38pub type SIGSEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `SIGSEL` writer - Signal Select"]
40pub type SIGSEL_W<'a> = crate::FieldWriter<'a, u32, CH1_CTRL_SPEC, u8, u8, 4, 0>;
41#[doc = "Source Select\n\nValue on reset: 0"]
42#[derive(Clone, Copy, Debug, PartialEq)]
43#[repr(u8)]
44pub enum SOURCESEL_A {
45    #[doc = "0: No source selected"]
46    NONE = 0,
47    #[doc = "8: Analog to Digital Converter 0"]
48    ADC0 = 8,
49    #[doc = "12: Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
50    USART0 = 12,
51    #[doc = "13: Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
52    USART1 = 13,
53    #[doc = "16: Low Energy UART 0"]
54    LEUART0 = 16,
55    #[doc = "20: I2C 0"]
56    I2C0 = 20,
57    #[doc = "24: Timer 0"]
58    TIMER0 = 24,
59    #[doc = "25: Timer 1"]
60    TIMER1 = 25,
61    #[doc = "26: Timer 2"]
62    TIMER2 = 26,
63    #[doc = "48: `110000`"]
64    MSC = 48,
65    #[doc = "49: Advanced Encryption Standard Accelerator"]
66    AES = 49,
67}
68impl From<SOURCESEL_A> for u8 {
69    #[inline(always)]
70    fn from(variant: SOURCESEL_A) -> Self {
71        variant as _
72    }
73}
74#[doc = "Field `SOURCESEL` reader - Source Select"]
75pub type SOURCESEL_R = crate::FieldReader<u8, SOURCESEL_A>;
76impl SOURCESEL_R {
77    #[doc = "Get enumerated values variant"]
78    #[inline(always)]
79    pub fn variant(&self) -> Option<SOURCESEL_A> {
80        match self.bits {
81            0 => Some(SOURCESEL_A::NONE),
82            8 => Some(SOURCESEL_A::ADC0),
83            12 => Some(SOURCESEL_A::USART0),
84            13 => Some(SOURCESEL_A::USART1),
85            16 => Some(SOURCESEL_A::LEUART0),
86            20 => Some(SOURCESEL_A::I2C0),
87            24 => Some(SOURCESEL_A::TIMER0),
88            25 => Some(SOURCESEL_A::TIMER1),
89            26 => Some(SOURCESEL_A::TIMER2),
90            48 => Some(SOURCESEL_A::MSC),
91            49 => Some(SOURCESEL_A::AES),
92            _ => None,
93        }
94    }
95    #[doc = "Checks if the value of the field is `NONE`"]
96    #[inline(always)]
97    pub fn is_none(&self) -> bool {
98        *self == SOURCESEL_A::NONE
99    }
100    #[doc = "Checks if the value of the field is `ADC0`"]
101    #[inline(always)]
102    pub fn is_adc0(&self) -> bool {
103        *self == SOURCESEL_A::ADC0
104    }
105    #[doc = "Checks if the value of the field is `USART0`"]
106    #[inline(always)]
107    pub fn is_usart0(&self) -> bool {
108        *self == SOURCESEL_A::USART0
109    }
110    #[doc = "Checks if the value of the field is `USART1`"]
111    #[inline(always)]
112    pub fn is_usart1(&self) -> bool {
113        *self == SOURCESEL_A::USART1
114    }
115    #[doc = "Checks if the value of the field is `LEUART0`"]
116    #[inline(always)]
117    pub fn is_leuart0(&self) -> bool {
118        *self == SOURCESEL_A::LEUART0
119    }
120    #[doc = "Checks if the value of the field is `I2C0`"]
121    #[inline(always)]
122    pub fn is_i2c0(&self) -> bool {
123        *self == SOURCESEL_A::I2C0
124    }
125    #[doc = "Checks if the value of the field is `TIMER0`"]
126    #[inline(always)]
127    pub fn is_timer0(&self) -> bool {
128        *self == SOURCESEL_A::TIMER0
129    }
130    #[doc = "Checks if the value of the field is `TIMER1`"]
131    #[inline(always)]
132    pub fn is_timer1(&self) -> bool {
133        *self == SOURCESEL_A::TIMER1
134    }
135    #[doc = "Checks if the value of the field is `TIMER2`"]
136    #[inline(always)]
137    pub fn is_timer2(&self) -> bool {
138        *self == SOURCESEL_A::TIMER2
139    }
140    #[doc = "Checks if the value of the field is `MSC`"]
141    #[inline(always)]
142    pub fn is_msc(&self) -> bool {
143        *self == SOURCESEL_A::MSC
144    }
145    #[doc = "Checks if the value of the field is `AES`"]
146    #[inline(always)]
147    pub fn is_aes(&self) -> bool {
148        *self == SOURCESEL_A::AES
149    }
150}
151#[doc = "Field `SOURCESEL` writer - Source Select"]
152pub type SOURCESEL_W<'a> = crate::FieldWriter<'a, u32, CH1_CTRL_SPEC, u8, SOURCESEL_A, 6, 16>;
153impl<'a> SOURCESEL_W<'a> {
154    #[doc = "No source selected"]
155    #[inline(always)]
156    pub fn none(self) -> &'a mut W {
157        self.variant(SOURCESEL_A::NONE)
158    }
159    #[doc = "Analog to Digital Converter 0"]
160    #[inline(always)]
161    pub fn adc0(self) -> &'a mut W {
162        self.variant(SOURCESEL_A::ADC0)
163    }
164    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
165    #[inline(always)]
166    pub fn usart0(self) -> &'a mut W {
167        self.variant(SOURCESEL_A::USART0)
168    }
169    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
170    #[inline(always)]
171    pub fn usart1(self) -> &'a mut W {
172        self.variant(SOURCESEL_A::USART1)
173    }
174    #[doc = "Low Energy UART 0"]
175    #[inline(always)]
176    pub fn leuart0(self) -> &'a mut W {
177        self.variant(SOURCESEL_A::LEUART0)
178    }
179    #[doc = "I2C 0"]
180    #[inline(always)]
181    pub fn i2c0(self) -> &'a mut W {
182        self.variant(SOURCESEL_A::I2C0)
183    }
184    #[doc = "Timer 0"]
185    #[inline(always)]
186    pub fn timer0(self) -> &'a mut W {
187        self.variant(SOURCESEL_A::TIMER0)
188    }
189    #[doc = "Timer 1"]
190    #[inline(always)]
191    pub fn timer1(self) -> &'a mut W {
192        self.variant(SOURCESEL_A::TIMER1)
193    }
194    #[doc = "Timer 2"]
195    #[inline(always)]
196    pub fn timer2(self) -> &'a mut W {
197        self.variant(SOURCESEL_A::TIMER2)
198    }
199    #[doc = "`110000`"]
200    #[inline(always)]
201    pub fn msc(self) -> &'a mut W {
202        self.variant(SOURCESEL_A::MSC)
203    }
204    #[doc = "Advanced Encryption Standard Accelerator"]
205    #[inline(always)]
206    pub fn aes(self) -> &'a mut W {
207        self.variant(SOURCESEL_A::AES)
208    }
209}
210impl R {
211    #[doc = "Bits 0:3 - Signal Select"]
212    #[inline(always)]
213    pub fn sigsel(&self) -> SIGSEL_R {
214        SIGSEL_R::new((self.bits & 0x0f) as u8)
215    }
216    #[doc = "Bits 16:21 - Source Select"]
217    #[inline(always)]
218    pub fn sourcesel(&self) -> SOURCESEL_R {
219        SOURCESEL_R::new(((self.bits >> 16) & 0x3f) as u8)
220    }
221}
222impl W {
223    #[doc = "Bits 0:3 - Signal Select"]
224    #[inline(always)]
225    pub fn sigsel(&mut self) -> SIGSEL_W {
226        SIGSEL_W::new(self)
227    }
228    #[doc = "Bits 16:21 - Source Select"]
229    #[inline(always)]
230    pub fn sourcesel(&mut self) -> SOURCESEL_W {
231        SOURCESEL_W::new(self)
232    }
233    #[doc = "Writes raw bits to the register."]
234    #[inline(always)]
235    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
236        self.0.bits(bits);
237        self
238    }
239}
240#[doc = "Channel Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch1_ctrl](index.html) module"]
241pub struct CH1_CTRL_SPEC;
242impl crate::RegisterSpec for CH1_CTRL_SPEC {
243    type Ux = u32;
244}
245#[doc = "`read()` method returns [ch1_ctrl::R](R) reader structure"]
246impl crate::Readable for CH1_CTRL_SPEC {
247    type Reader = R;
248}
249#[doc = "`write(|w| ..)` method takes [ch1_ctrl::W](W) writer structure"]
250impl crate::Writable for CH1_CTRL_SPEC {
251    type Writer = W;
252}
253#[doc = "`reset()` method sets CH1_CTRL to value 0"]
254impl crate::Resettable for CH1_CTRL_SPEC {
255    #[inline(always)]
256    fn reset_value() -> Self::Ux {
257        0
258    }
259}
efm32hg309_pac/dma/ch1_ctrl.rs

efm32hg309_pac/dma/
ch1_ctrl.rs
