efm32hg308_pac/usb/
diepmsk.rs

1#[doc = "Register `DIEPMSK` reader"]
2pub struct R(crate::R<DIEPMSK_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DIEPMSK_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DIEPMSK_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DIEPMSK_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `DIEPMSK` writer"]
17pub struct W(crate::W<DIEPMSK_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DIEPMSK_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DIEPMSK_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DIEPMSK_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `XFERCOMPLMSK` reader - Transfer Completed Interrupt Mask"]
38pub type XFERCOMPLMSK_R = crate::BitReader<bool>;
39#[doc = "Field `XFERCOMPLMSK` writer - Transfer Completed Interrupt Mask"]
40pub type XFERCOMPLMSK_W<'a> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, 0>;
41#[doc = "Field `EPDISBLDMSK` reader - Endpoint Disabled Interrupt Mask"]
42pub type EPDISBLDMSK_R = crate::BitReader<bool>;
43#[doc = "Field `EPDISBLDMSK` writer - Endpoint Disabled Interrupt Mask"]
44pub type EPDISBLDMSK_W<'a> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, 1>;
45#[doc = "Field `AHBERRMSK` reader - AHB Error Mask"]
46pub type AHBERRMSK_R = crate::BitReader<bool>;
47#[doc = "Field `AHBERRMSK` writer - AHB Error Mask"]
48pub type AHBERRMSK_W<'a> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, 2>;
49#[doc = "Field `TIMEOUTMSK` reader - Timeout Condition Mask"]
50pub type TIMEOUTMSK_R = crate::BitReader<bool>;
51#[doc = "Field `TIMEOUTMSK` writer - Timeout Condition Mask"]
52pub type TIMEOUTMSK_W<'a> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, 3>;
53#[doc = "Field `INTKNTXFEMPMSK` reader - IN Token Received When TxFIFO Empty Mask"]
54pub type INTKNTXFEMPMSK_R = crate::BitReader<bool>;
55#[doc = "Field `INTKNTXFEMPMSK` writer - IN Token Received When TxFIFO Empty Mask"]
56pub type INTKNTXFEMPMSK_W<'a> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, 4>;
57#[doc = "Field `INEPNAKEFFMSK` reader - IN Endpoint NAK Effective Mask"]
58pub type INEPNAKEFFMSK_R = crate::BitReader<bool>;
59#[doc = "Field `INEPNAKEFFMSK` writer - IN Endpoint NAK Effective Mask"]
60pub type INEPNAKEFFMSK_W<'a> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, 6>;
61#[doc = "Field `TXFIFOUNDRNMSK` reader - Fifo Underrun Mask"]
62pub type TXFIFOUNDRNMSK_R = crate::BitReader<bool>;
63#[doc = "Field `TXFIFOUNDRNMSK` writer - Fifo Underrun Mask"]
64pub type TXFIFOUNDRNMSK_W<'a> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, 8>;
65#[doc = "Field `NAKMSK` reader - NAK interrupt Mask"]
66pub type NAKMSK_R = crate::BitReader<bool>;
67#[doc = "Field `NAKMSK` writer - NAK interrupt Mask"]
68pub type NAKMSK_W<'a> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, 13>;
69impl R {
70    #[doc = "Bit 0 - Transfer Completed Interrupt Mask"]
71    #[inline(always)]
72    pub fn xfercomplmsk(&self) -> XFERCOMPLMSK_R {
73        XFERCOMPLMSK_R::new((self.bits & 1) != 0)
74    }
75    #[doc = "Bit 1 - Endpoint Disabled Interrupt Mask"]
76    #[inline(always)]
77    pub fn epdisbldmsk(&self) -> EPDISBLDMSK_R {
78        EPDISBLDMSK_R::new(((self.bits >> 1) & 1) != 0)
79    }
80    #[doc = "Bit 2 - AHB Error Mask"]
81    #[inline(always)]
82    pub fn ahberrmsk(&self) -> AHBERRMSK_R {
83        AHBERRMSK_R::new(((self.bits >> 2) & 1) != 0)
84    }
85    #[doc = "Bit 3 - Timeout Condition Mask"]
86    #[inline(always)]
87    pub fn timeoutmsk(&self) -> TIMEOUTMSK_R {
88        TIMEOUTMSK_R::new(((self.bits >> 3) & 1) != 0)
89    }
90    #[doc = "Bit 4 - IN Token Received When TxFIFO Empty Mask"]
91    #[inline(always)]
92    pub fn intkntxfempmsk(&self) -> INTKNTXFEMPMSK_R {
93        INTKNTXFEMPMSK_R::new(((self.bits >> 4) & 1) != 0)
94    }
95    #[doc = "Bit 6 - IN Endpoint NAK Effective Mask"]
96    #[inline(always)]
97    pub fn inepnakeffmsk(&self) -> INEPNAKEFFMSK_R {
98        INEPNAKEFFMSK_R::new(((self.bits >> 6) & 1) != 0)
99    }
100    #[doc = "Bit 8 - Fifo Underrun Mask"]
101    #[inline(always)]
102    pub fn txfifoundrnmsk(&self) -> TXFIFOUNDRNMSK_R {
103        TXFIFOUNDRNMSK_R::new(((self.bits >> 8) & 1) != 0)
104    }
105    #[doc = "Bit 13 - NAK interrupt Mask"]
106    #[inline(always)]
107    pub fn nakmsk(&self) -> NAKMSK_R {
108        NAKMSK_R::new(((self.bits >> 13) & 1) != 0)
109    }
110}
111impl W {
112    #[doc = "Bit 0 - Transfer Completed Interrupt Mask"]
113    #[inline(always)]
114    pub fn xfercomplmsk(&mut self) -> XFERCOMPLMSK_W {
115        XFERCOMPLMSK_W::new(self)
116    }
117    #[doc = "Bit 1 - Endpoint Disabled Interrupt Mask"]
118    #[inline(always)]
119    pub fn epdisbldmsk(&mut self) -> EPDISBLDMSK_W {
120        EPDISBLDMSK_W::new(self)
121    }
122    #[doc = "Bit 2 - AHB Error Mask"]
123    #[inline(always)]
124    pub fn ahberrmsk(&mut self) -> AHBERRMSK_W {
125        AHBERRMSK_W::new(self)
126    }
127    #[doc = "Bit 3 - Timeout Condition Mask"]
128    #[inline(always)]
129    pub fn timeoutmsk(&mut self) -> TIMEOUTMSK_W {
130        TIMEOUTMSK_W::new(self)
131    }
132    #[doc = "Bit 4 - IN Token Received When TxFIFO Empty Mask"]
133    #[inline(always)]
134    pub fn intkntxfempmsk(&mut self) -> INTKNTXFEMPMSK_W {
135        INTKNTXFEMPMSK_W::new(self)
136    }
137    #[doc = "Bit 6 - IN Endpoint NAK Effective Mask"]
138    #[inline(always)]
139    pub fn inepnakeffmsk(&mut self) -> INEPNAKEFFMSK_W {
140        INEPNAKEFFMSK_W::new(self)
141    }
142    #[doc = "Bit 8 - Fifo Underrun Mask"]
143    #[inline(always)]
144    pub fn txfifoundrnmsk(&mut self) -> TXFIFOUNDRNMSK_W {
145        TXFIFOUNDRNMSK_W::new(self)
146    }
147    #[doc = "Bit 13 - NAK interrupt Mask"]
148    #[inline(always)]
149    pub fn nakmsk(&mut self) -> NAKMSK_W {
150        NAKMSK_W::new(self)
151    }
152    #[doc = "Writes raw bits to the register."]
153    #[inline(always)]
154    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
155        self.0.bits(bits);
156        self
157    }
158}
159#[doc = "Device IN Endpoint Common Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diepmsk](index.html) module"]
160pub struct DIEPMSK_SPEC;
161impl crate::RegisterSpec for DIEPMSK_SPEC {
162    type Ux = u32;
163}
164#[doc = "`read()` method returns [diepmsk::R](R) reader structure"]
165impl crate::Readable for DIEPMSK_SPEC {
166    type Reader = R;
167}
168#[doc = "`write(|w| ..)` method takes [diepmsk::W](W) writer structure"]
169impl crate::Writable for DIEPMSK_SPEC {
170    type Writer = W;
171}
172#[doc = "`reset()` method sets DIEPMSK to value 0"]
173impl crate::Resettable for DIEPMSK_SPEC {
174    #[inline(always)]
175    fn reset_value() -> Self::Ux {
176        0
177    }
178}
efm32hg308_pac/usb/diepmsk.rs

efm32hg308_pac/usb/
diepmsk.rs
