efm32hg308_pac/msc/
readctrl.rs

1#[doc = "Register `READCTRL` reader"]
2pub struct R(crate::R<READCTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<READCTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<READCTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<READCTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `READCTRL` writer"]
17pub struct W(crate::W<READCTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<READCTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<READCTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<READCTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Read Mode\n\nValue on reset: 1"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u8)]
40pub enum MODE_A {
41    #[doc = "0: Zero wait-states inserted in fetch or read transfers."]
42    WS0 = 0,
43    #[doc = "1: One wait-state inserted for each fetch or read transfer. This mode is required for a core frequency above 16 MHz."]
44    WS1 = 1,
45}
46impl From<MODE_A> for u8 {
47    #[inline(always)]
48    fn from(variant: MODE_A) -> Self {
49        variant as _
50    }
51}
52#[doc = "Field `MODE` reader - Read Mode"]
53pub type MODE_R = crate::FieldReader<u8, MODE_A>;
54impl MODE_R {
55    #[doc = "Get enumerated values variant"]
56    #[inline(always)]
57    pub fn variant(&self) -> Option<MODE_A> {
58        match self.bits {
59            0 => Some(MODE_A::WS0),
60            1 => Some(MODE_A::WS1),
61            _ => None,
62        }
63    }
64    #[doc = "Checks if the value of the field is `WS0`"]
65    #[inline(always)]
66    pub fn is_ws0(&self) -> bool {
67        *self == MODE_A::WS0
68    }
69    #[doc = "Checks if the value of the field is `WS1`"]
70    #[inline(always)]
71    pub fn is_ws1(&self) -> bool {
72        *self == MODE_A::WS1
73    }
74}
75#[doc = "Field `MODE` writer - Read Mode"]
76pub type MODE_W<'a> = crate::FieldWriter<'a, u32, READCTRL_SPEC, u8, MODE_A, 3, 0>;
77impl<'a> MODE_W<'a> {
78    #[doc = "Zero wait-states inserted in fetch or read transfers."]
79    #[inline(always)]
80    pub fn ws0(self) -> &'a mut W {
81        self.variant(MODE_A::WS0)
82    }
83    #[doc = "One wait-state inserted for each fetch or read transfer. This mode is required for a core frequency above 16 MHz."]
84    #[inline(always)]
85    pub fn ws1(self) -> &'a mut W {
86        self.variant(MODE_A::WS1)
87    }
88}
89#[doc = "Field `IFCDIS` reader - Internal Flash Cache Disable"]
90pub type IFCDIS_R = crate::BitReader<bool>;
91#[doc = "Field `IFCDIS` writer - Internal Flash Cache Disable"]
92pub type IFCDIS_W<'a> = crate::BitWriter<'a, u32, READCTRL_SPEC, bool, 3>;
93#[doc = "Field `AIDIS` reader - Automatic Invalidate Disable"]
94pub type AIDIS_R = crate::BitReader<bool>;
95#[doc = "Field `AIDIS` writer - Automatic Invalidate Disable"]
96pub type AIDIS_W<'a> = crate::BitWriter<'a, u32, READCTRL_SPEC, bool, 4>;
97#[doc = "Field `RAMCEN` reader - RAM Cache Enable"]
98pub type RAMCEN_R = crate::BitReader<bool>;
99#[doc = "Field `RAMCEN` writer - RAM Cache Enable"]
100pub type RAMCEN_W<'a> = crate::BitWriter<'a, u32, READCTRL_SPEC, bool, 7>;
101impl R {
102    #[doc = "Bits 0:2 - Read Mode"]
103    #[inline(always)]
104    pub fn mode(&self) -> MODE_R {
105        MODE_R::new((self.bits & 7) as u8)
106    }
107    #[doc = "Bit 3 - Internal Flash Cache Disable"]
108    #[inline(always)]
109    pub fn ifcdis(&self) -> IFCDIS_R {
110        IFCDIS_R::new(((self.bits >> 3) & 1) != 0)
111    }
112    #[doc = "Bit 4 - Automatic Invalidate Disable"]
113    #[inline(always)]
114    pub fn aidis(&self) -> AIDIS_R {
115        AIDIS_R::new(((self.bits >> 4) & 1) != 0)
116    }
117    #[doc = "Bit 7 - RAM Cache Enable"]
118    #[inline(always)]
119    pub fn ramcen(&self) -> RAMCEN_R {
120        RAMCEN_R::new(((self.bits >> 7) & 1) != 0)
121    }
122}
123impl W {
124    #[doc = "Bits 0:2 - Read Mode"]
125    #[inline(always)]
126    pub fn mode(&mut self) -> MODE_W {
127        MODE_W::new(self)
128    }
129    #[doc = "Bit 3 - Internal Flash Cache Disable"]
130    #[inline(always)]
131    pub fn ifcdis(&mut self) -> IFCDIS_W {
132        IFCDIS_W::new(self)
133    }
134    #[doc = "Bit 4 - Automatic Invalidate Disable"]
135    #[inline(always)]
136    pub fn aidis(&mut self) -> AIDIS_W {
137        AIDIS_W::new(self)
138    }
139    #[doc = "Bit 7 - RAM Cache Enable"]
140    #[inline(always)]
141    pub fn ramcen(&mut self) -> RAMCEN_W {
142        RAMCEN_W::new(self)
143    }
144    #[doc = "Writes raw bits to the register."]
145    #[inline(always)]
146    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
147        self.0.bits(bits);
148        self
149    }
150}
151#[doc = "Read Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [readctrl](index.html) module"]
152pub struct READCTRL_SPEC;
153impl crate::RegisterSpec for READCTRL_SPEC {
154    type Ux = u32;
155}
156#[doc = "`read()` method returns [readctrl::R](R) reader structure"]
157impl crate::Readable for READCTRL_SPEC {
158    type Reader = R;
159}
160#[doc = "`write(|w| ..)` method takes [readctrl::W](W) writer structure"]
161impl crate::Writable for READCTRL_SPEC {
162    type Writer = W;
163}
164#[doc = "`reset()` method sets READCTRL to value 0x01"]
165impl crate::Resettable for READCTRL_SPEC {
166    #[inline(always)]
167    fn reset_value() -> Self::Ux {
168        0x01
169    }
170}
efm32hg308_pac/msc/readctrl.rs

efm32hg308_pac/msc/
readctrl.rs
