efm32hg210_pac/cmu/
ushfrcoconf.rs

1#[doc = "Register `USHFRCOCONF` reader"]
2pub struct R(crate::R<USHFRCOCONF_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<USHFRCOCONF_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<USHFRCOCONF_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<USHFRCOCONF_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `USHFRCOCONF` writer"]
17pub struct W(crate::W<USHFRCOCONF_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<USHFRCOCONF_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<USHFRCOCONF_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<USHFRCOCONF_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "USHFRCO Band Select\n\nValue on reset: 1"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u8)]
40pub enum BAND_A {
41    #[doc = "1: 48 MHz band. NOTE: Also set the TUNING and FINETUNING value when changing band."]
42    _48MHZ = 1,
43    #[doc = "3: 24 MHz band. NOTE: Also set the TUNING and FINETUNING value when changing band."]
44    _24MHZ = 3,
45}
46impl From<BAND_A> for u8 {
47    #[inline(always)]
48    fn from(variant: BAND_A) -> Self {
49        variant as _
50    }
51}
52#[doc = "Field `BAND` reader - USHFRCO Band Select"]
53pub type BAND_R = crate::FieldReader<u8, BAND_A>;
54impl BAND_R {
55    #[doc = "Get enumerated values variant"]
56    #[inline(always)]
57    pub fn variant(&self) -> Option<BAND_A> {
58        match self.bits {
59            1 => Some(BAND_A::_48MHZ),
60            3 => Some(BAND_A::_24MHZ),
61            _ => None,
62        }
63    }
64    #[doc = "Checks if the value of the field is `_48MHZ`"]
65    #[inline(always)]
66    pub fn is_48mhz(&self) -> bool {
67        *self == BAND_A::_48MHZ
68    }
69    #[doc = "Checks if the value of the field is `_24MHZ`"]
70    #[inline(always)]
71    pub fn is_24mhz(&self) -> bool {
72        *self == BAND_A::_24MHZ
73    }
74}
75#[doc = "Field `BAND` writer - USHFRCO Band Select"]
76pub type BAND_W<'a> = crate::FieldWriter<'a, u32, USHFRCOCONF_SPEC, u8, BAND_A, 3, 0>;
77impl<'a> BAND_W<'a> {
78    #[doc = "48 MHz band. NOTE: Also set the TUNING and FINETUNING value when changing band."]
79    #[inline(always)]
80    pub fn _48mhz(self) -> &'a mut W {
81        self.variant(BAND_A::_48MHZ)
82    }
83    #[doc = "24 MHz band. NOTE: Also set the TUNING and FINETUNING value when changing band."]
84    #[inline(always)]
85    pub fn _24mhz(self) -> &'a mut W {
86        self.variant(BAND_A::_24MHZ)
87    }
88}
89#[doc = "Field `USHFRCODIV2DIS` reader - USHFRCO divider for HFCLK disable"]
90pub type USHFRCODIV2DIS_R = crate::BitReader<bool>;
91#[doc = "Field `USHFRCODIV2DIS` writer - USHFRCO divider for HFCLK disable"]
92pub type USHFRCODIV2DIS_W<'a> = crate::BitWriter<'a, u32, USHFRCOCONF_SPEC, bool, 4>;
93impl R {
94    #[doc = "Bits 0:2 - USHFRCO Band Select"]
95    #[inline(always)]
96    pub fn band(&self) -> BAND_R {
97        BAND_R::new((self.bits & 7) as u8)
98    }
99    #[doc = "Bit 4 - USHFRCO divider for HFCLK disable"]
100    #[inline(always)]
101    pub fn ushfrcodiv2dis(&self) -> USHFRCODIV2DIS_R {
102        USHFRCODIV2DIS_R::new(((self.bits >> 4) & 1) != 0)
103    }
104}
105impl W {
106    #[doc = "Bits 0:2 - USHFRCO Band Select"]
107    #[inline(always)]
108    pub fn band(&mut self) -> BAND_W {
109        BAND_W::new(self)
110    }
111    #[doc = "Bit 4 - USHFRCO divider for HFCLK disable"]
112    #[inline(always)]
113    pub fn ushfrcodiv2dis(&mut self) -> USHFRCODIV2DIS_W {
114        USHFRCODIV2DIS_W::new(self)
115    }
116    #[doc = "Writes raw bits to the register."]
117    #[inline(always)]
118    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
119        self.0.bits(bits);
120        self
121    }
122}
123#[doc = "USHFRCO Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ushfrcoconf](index.html) module"]
124pub struct USHFRCOCONF_SPEC;
125impl crate::RegisterSpec for USHFRCOCONF_SPEC {
126    type Ux = u32;
127}
128#[doc = "`read()` method returns [ushfrcoconf::R](R) reader structure"]
129impl crate::Readable for USHFRCOCONF_SPEC {
130    type Reader = R;
131}
132#[doc = "`write(|w| ..)` method takes [ushfrcoconf::W](W) writer structure"]
133impl crate::Writable for USHFRCOCONF_SPEC {
134    type Writer = W;
135}
136#[doc = "`reset()` method sets USHFRCOCONF to value 0x01"]
137impl crate::Resettable for USHFRCOCONF_SPEC {
138    #[inline(always)]
139    fn reset_value() -> Self::Ux {
140        0x01
141    }
142}
efm32hg210_pac/cmu/ushfrcoconf.rs

efm32hg210_pac/cmu/
ushfrcoconf.rs
