efm32hg110_pac/prs/
ch5_ctrl.rs

1#[doc = "Register `CH5_CTRL` reader"]
2pub struct R(crate::R<CH5_CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CH5_CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CH5_CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CH5_CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CH5_CTRL` writer"]
17pub struct W(crate::W<CH5_CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CH5_CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CH5_CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CH5_CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SIGSEL` reader - Signal Select"]
38pub type SIGSEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `SIGSEL` writer - Signal Select"]
40pub type SIGSEL_W<'a> = crate::FieldWriter<'a, u32, CH5_CTRL_SPEC, u8, u8, 3, 0>;
41#[doc = "Source Select\n\nValue on reset: 0"]
42#[derive(Clone, Copy, Debug, PartialEq)]
43#[repr(u8)]
44pub enum SOURCESEL_A {
45    #[doc = "0: No source selected"]
46    NONE = 0,
47    #[doc = "1: Voltage Comparator"]
48    VCMP = 1,
49    #[doc = "2: Analog Comparator 0"]
50    ACMP0 = 2,
51    #[doc = "8: Analog to Digital Converter 0"]
52    ADC0 = 8,
53    #[doc = "16: Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
54    USART0 = 16,
55    #[doc = "17: Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
56    USART1 = 17,
57    #[doc = "28: Timer 0"]
58    TIMER0 = 28,
59    #[doc = "29: Timer 1"]
60    TIMER1 = 29,
61    #[doc = "30: Timer 2"]
62    TIMER2 = 30,
63    #[doc = "40: Real-Time Counter"]
64    RTC = 40,
65    #[doc = "48: General purpose Input/Output"]
66    GPIOL = 48,
67    #[doc = "49: General purpose Input/Output"]
68    GPIOH = 49,
69    #[doc = "54: Pulse Counter 0"]
70    PCNT0 = 54,
71}
72impl From<SOURCESEL_A> for u8 {
73    #[inline(always)]
74    fn from(variant: SOURCESEL_A) -> Self {
75        variant as _
76    }
77}
78#[doc = "Field `SOURCESEL` reader - Source Select"]
79pub type SOURCESEL_R = crate::FieldReader<u8, SOURCESEL_A>;
80impl SOURCESEL_R {
81    #[doc = "Get enumerated values variant"]
82    #[inline(always)]
83    pub fn variant(&self) -> Option<SOURCESEL_A> {
84        match self.bits {
85            0 => Some(SOURCESEL_A::NONE),
86            1 => Some(SOURCESEL_A::VCMP),
87            2 => Some(SOURCESEL_A::ACMP0),
88            8 => Some(SOURCESEL_A::ADC0),
89            16 => Some(SOURCESEL_A::USART0),
90            17 => Some(SOURCESEL_A::USART1),
91            28 => Some(SOURCESEL_A::TIMER0),
92            29 => Some(SOURCESEL_A::TIMER1),
93            30 => Some(SOURCESEL_A::TIMER2),
94            40 => Some(SOURCESEL_A::RTC),
95            48 => Some(SOURCESEL_A::GPIOL),
96            49 => Some(SOURCESEL_A::GPIOH),
97            54 => Some(SOURCESEL_A::PCNT0),
98            _ => None,
99        }
100    }
101    #[doc = "Checks if the value of the field is `NONE`"]
102    #[inline(always)]
103    pub fn is_none(&self) -> bool {
104        *self == SOURCESEL_A::NONE
105    }
106    #[doc = "Checks if the value of the field is `VCMP`"]
107    #[inline(always)]
108    pub fn is_vcmp(&self) -> bool {
109        *self == SOURCESEL_A::VCMP
110    }
111    #[doc = "Checks if the value of the field is `ACMP0`"]
112    #[inline(always)]
113    pub fn is_acmp0(&self) -> bool {
114        *self == SOURCESEL_A::ACMP0
115    }
116    #[doc = "Checks if the value of the field is `ADC0`"]
117    #[inline(always)]
118    pub fn is_adc0(&self) -> bool {
119        *self == SOURCESEL_A::ADC0
120    }
121    #[doc = "Checks if the value of the field is `USART0`"]
122    #[inline(always)]
123    pub fn is_usart0(&self) -> bool {
124        *self == SOURCESEL_A::USART0
125    }
126    #[doc = "Checks if the value of the field is `USART1`"]
127    #[inline(always)]
128    pub fn is_usart1(&self) -> bool {
129        *self == SOURCESEL_A::USART1
130    }
131    #[doc = "Checks if the value of the field is `TIMER0`"]
132    #[inline(always)]
133    pub fn is_timer0(&self) -> bool {
134        *self == SOURCESEL_A::TIMER0
135    }
136    #[doc = "Checks if the value of the field is `TIMER1`"]
137    #[inline(always)]
138    pub fn is_timer1(&self) -> bool {
139        *self == SOURCESEL_A::TIMER1
140    }
141    #[doc = "Checks if the value of the field is `TIMER2`"]
142    #[inline(always)]
143    pub fn is_timer2(&self) -> bool {
144        *self == SOURCESEL_A::TIMER2
145    }
146    #[doc = "Checks if the value of the field is `RTC`"]
147    #[inline(always)]
148    pub fn is_rtc(&self) -> bool {
149        *self == SOURCESEL_A::RTC
150    }
151    #[doc = "Checks if the value of the field is `GPIOL`"]
152    #[inline(always)]
153    pub fn is_gpiol(&self) -> bool {
154        *self == SOURCESEL_A::GPIOL
155    }
156    #[doc = "Checks if the value of the field is `GPIOH`"]
157    #[inline(always)]
158    pub fn is_gpioh(&self) -> bool {
159        *self == SOURCESEL_A::GPIOH
160    }
161    #[doc = "Checks if the value of the field is `PCNT0`"]
162    #[inline(always)]
163    pub fn is_pcnt0(&self) -> bool {
164        *self == SOURCESEL_A::PCNT0
165    }
166}
167#[doc = "Field `SOURCESEL` writer - Source Select"]
168pub type SOURCESEL_W<'a> = crate::FieldWriter<'a, u32, CH5_CTRL_SPEC, u8, SOURCESEL_A, 6, 16>;
169impl<'a> SOURCESEL_W<'a> {
170    #[doc = "No source selected"]
171    #[inline(always)]
172    pub fn none(self) -> &'a mut W {
173        self.variant(SOURCESEL_A::NONE)
174    }
175    #[doc = "Voltage Comparator"]
176    #[inline(always)]
177    pub fn vcmp(self) -> &'a mut W {
178        self.variant(SOURCESEL_A::VCMP)
179    }
180    #[doc = "Analog Comparator 0"]
181    #[inline(always)]
182    pub fn acmp0(self) -> &'a mut W {
183        self.variant(SOURCESEL_A::ACMP0)
184    }
185    #[doc = "Analog to Digital Converter 0"]
186    #[inline(always)]
187    pub fn adc0(self) -> &'a mut W {
188        self.variant(SOURCESEL_A::ADC0)
189    }
190    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
191    #[inline(always)]
192    pub fn usart0(self) -> &'a mut W {
193        self.variant(SOURCESEL_A::USART0)
194    }
195    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
196    #[inline(always)]
197    pub fn usart1(self) -> &'a mut W {
198        self.variant(SOURCESEL_A::USART1)
199    }
200    #[doc = "Timer 0"]
201    #[inline(always)]
202    pub fn timer0(self) -> &'a mut W {
203        self.variant(SOURCESEL_A::TIMER0)
204    }
205    #[doc = "Timer 1"]
206    #[inline(always)]
207    pub fn timer1(self) -> &'a mut W {
208        self.variant(SOURCESEL_A::TIMER1)
209    }
210    #[doc = "Timer 2"]
211    #[inline(always)]
212    pub fn timer2(self) -> &'a mut W {
213        self.variant(SOURCESEL_A::TIMER2)
214    }
215    #[doc = "Real-Time Counter"]
216    #[inline(always)]
217    pub fn rtc(self) -> &'a mut W {
218        self.variant(SOURCESEL_A::RTC)
219    }
220    #[doc = "General purpose Input/Output"]
221    #[inline(always)]
222    pub fn gpiol(self) -> &'a mut W {
223        self.variant(SOURCESEL_A::GPIOL)
224    }
225    #[doc = "General purpose Input/Output"]
226    #[inline(always)]
227    pub fn gpioh(self) -> &'a mut W {
228        self.variant(SOURCESEL_A::GPIOH)
229    }
230    #[doc = "Pulse Counter 0"]
231    #[inline(always)]
232    pub fn pcnt0(self) -> &'a mut W {
233        self.variant(SOURCESEL_A::PCNT0)
234    }
235}
236#[doc = "Edge Detect Select\n\nValue on reset: 0"]
237#[derive(Clone, Copy, Debug, PartialEq)]
238#[repr(u8)]
239pub enum EDSEL_A {
240    #[doc = "0: Signal is left as it is"]
241    OFF = 0,
242    #[doc = "1: A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal"]
243    POSEDGE = 1,
244    #[doc = "2: A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
245    NEGEDGE = 2,
246    #[doc = "3: A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal"]
247    BOTHEDGES = 3,
248}
249impl From<EDSEL_A> for u8 {
250    #[inline(always)]
251    fn from(variant: EDSEL_A) -> Self {
252        variant as _
253    }
254}
255#[doc = "Field `EDSEL` reader - Edge Detect Select"]
256pub type EDSEL_R = crate::FieldReader<u8, EDSEL_A>;
257impl EDSEL_R {
258    #[doc = "Get enumerated values variant"]
259    #[inline(always)]
260    pub fn variant(&self) -> EDSEL_A {
261        match self.bits {
262            0 => EDSEL_A::OFF,
263            1 => EDSEL_A::POSEDGE,
264            2 => EDSEL_A::NEGEDGE,
265            3 => EDSEL_A::BOTHEDGES,
266            _ => unreachable!(),
267        }
268    }
269    #[doc = "Checks if the value of the field is `OFF`"]
270    #[inline(always)]
271    pub fn is_off(&self) -> bool {
272        *self == EDSEL_A::OFF
273    }
274    #[doc = "Checks if the value of the field is `POSEDGE`"]
275    #[inline(always)]
276    pub fn is_posedge(&self) -> bool {
277        *self == EDSEL_A::POSEDGE
278    }
279    #[doc = "Checks if the value of the field is `NEGEDGE`"]
280    #[inline(always)]
281    pub fn is_negedge(&self) -> bool {
282        *self == EDSEL_A::NEGEDGE
283    }
284    #[doc = "Checks if the value of the field is `BOTHEDGES`"]
285    #[inline(always)]
286    pub fn is_bothedges(&self) -> bool {
287        *self == EDSEL_A::BOTHEDGES
288    }
289}
290#[doc = "Field `EDSEL` writer - Edge Detect Select"]
291pub type EDSEL_W<'a> = crate::FieldWriterSafe<'a, u32, CH5_CTRL_SPEC, u8, EDSEL_A, 2, 24>;
292impl<'a> EDSEL_W<'a> {
293    #[doc = "Signal is left as it is"]
294    #[inline(always)]
295    pub fn off(self) -> &'a mut W {
296        self.variant(EDSEL_A::OFF)
297    }
298    #[doc = "A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal"]
299    #[inline(always)]
300    pub fn posedge(self) -> &'a mut W {
301        self.variant(EDSEL_A::POSEDGE)
302    }
303    #[doc = "A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
304    #[inline(always)]
305    pub fn negedge(self) -> &'a mut W {
306        self.variant(EDSEL_A::NEGEDGE)
307    }
308    #[doc = "A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal"]
309    #[inline(always)]
310    pub fn bothedges(self) -> &'a mut W {
311        self.variant(EDSEL_A::BOTHEDGES)
312    }
313}
314#[doc = "Field `ASYNC` reader - Asynchronous reflex"]
315pub type ASYNC_R = crate::BitReader<bool>;
316#[doc = "Field `ASYNC` writer - Asynchronous reflex"]
317pub type ASYNC_W<'a> = crate::BitWriter<'a, u32, CH5_CTRL_SPEC, bool, 28>;
318impl R {
319    #[doc = "Bits 0:2 - Signal Select"]
320    #[inline(always)]
321    pub fn sigsel(&self) -> SIGSEL_R {
322        SIGSEL_R::new((self.bits & 7) as u8)
323    }
324    #[doc = "Bits 16:21 - Source Select"]
325    #[inline(always)]
326    pub fn sourcesel(&self) -> SOURCESEL_R {
327        SOURCESEL_R::new(((self.bits >> 16) & 0x3f) as u8)
328    }
329    #[doc = "Bits 24:25 - Edge Detect Select"]
330    #[inline(always)]
331    pub fn edsel(&self) -> EDSEL_R {
332        EDSEL_R::new(((self.bits >> 24) & 3) as u8)
333    }
334    #[doc = "Bit 28 - Asynchronous reflex"]
335    #[inline(always)]
336    pub fn async_(&self) -> ASYNC_R {
337        ASYNC_R::new(((self.bits >> 28) & 1) != 0)
338    }
339}
340impl W {
341    #[doc = "Bits 0:2 - Signal Select"]
342    #[inline(always)]
343    pub fn sigsel(&mut self) -> SIGSEL_W {
344        SIGSEL_W::new(self)
345    }
346    #[doc = "Bits 16:21 - Source Select"]
347    #[inline(always)]
348    pub fn sourcesel(&mut self) -> SOURCESEL_W {
349        SOURCESEL_W::new(self)
350    }
351    #[doc = "Bits 24:25 - Edge Detect Select"]
352    #[inline(always)]
353    pub fn edsel(&mut self) -> EDSEL_W {
354        EDSEL_W::new(self)
355    }
356    #[doc = "Bit 28 - Asynchronous reflex"]
357    #[inline(always)]
358    pub fn async_(&mut self) -> ASYNC_W {
359        ASYNC_W::new(self)
360    }
361    #[doc = "Writes raw bits to the register."]
362    #[inline(always)]
363    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
364        self.0.bits(bits);
365        self
366    }
367}
368#[doc = "Channel Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch5_ctrl](index.html) module"]
369pub struct CH5_CTRL_SPEC;
370impl crate::RegisterSpec for CH5_CTRL_SPEC {
371    type Ux = u32;
372}
373#[doc = "`read()` method returns [ch5_ctrl::R](R) reader structure"]
374impl crate::Readable for CH5_CTRL_SPEC {
375    type Reader = R;
376}
377#[doc = "`write(|w| ..)` method takes [ch5_ctrl::W](W) writer structure"]
378impl crate::Writable for CH5_CTRL_SPEC {
379    type Writer = W;
380}
381#[doc = "`reset()` method sets CH5_CTRL to value 0"]
382impl crate::Resettable for CH5_CTRL_SPEC {
383    #[inline(always)]
384    fn reset_value() -> Self::Ux {
385        0
386    }
387}
efm32hg110_pac/prs/ch5_ctrl.rs

efm32hg110_pac/prs/
ch5_ctrl.rs
