efm32hg108_pac/prs/
ch5_ctrl.rs

1#[doc = "Register `CH5_CTRL` reader"]
2pub struct R(crate::R<CH5_CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CH5_CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CH5_CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CH5_CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CH5_CTRL` writer"]
17pub struct W(crate::W<CH5_CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CH5_CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CH5_CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CH5_CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SIGSEL` reader - Signal Select"]
38pub type SIGSEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `SIGSEL` writer - Signal Select"]
40pub type SIGSEL_W<'a> = crate::FieldWriter<'a, u32, CH5_CTRL_SPEC, u8, u8, 3, 0>;
41#[doc = "Source Select\n\nValue on reset: 0"]
42#[derive(Clone, Copy, Debug, PartialEq)]
43#[repr(u8)]
44pub enum SOURCESEL_A {
45    #[doc = "0: No source selected"]
46    NONE = 0,
47    #[doc = "1: Voltage Comparator"]
48    VCMP = 1,
49    #[doc = "2: Analog Comparator 0"]
50    ACMP0 = 2,
51    #[doc = "16: Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
52    USART0 = 16,
53    #[doc = "17: Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
54    USART1 = 17,
55    #[doc = "28: Timer 0"]
56    TIMER0 = 28,
57    #[doc = "29: Timer 1"]
58    TIMER1 = 29,
59    #[doc = "30: Timer 2"]
60    TIMER2 = 30,
61    #[doc = "40: Real-Time Counter"]
62    RTC = 40,
63    #[doc = "48: General purpose Input/Output"]
64    GPIOL = 48,
65    #[doc = "49: General purpose Input/Output"]
66    GPIOH = 49,
67    #[doc = "54: Pulse Counter 0"]
68    PCNT0 = 54,
69}
70impl From<SOURCESEL_A> for u8 {
71    #[inline(always)]
72    fn from(variant: SOURCESEL_A) -> Self {
73        variant as _
74    }
75}
76#[doc = "Field `SOURCESEL` reader - Source Select"]
77pub type SOURCESEL_R = crate::FieldReader<u8, SOURCESEL_A>;
78impl SOURCESEL_R {
79    #[doc = "Get enumerated values variant"]
80    #[inline(always)]
81    pub fn variant(&self) -> Option<SOURCESEL_A> {
82        match self.bits {
83            0 => Some(SOURCESEL_A::NONE),
84            1 => Some(SOURCESEL_A::VCMP),
85            2 => Some(SOURCESEL_A::ACMP0),
86            16 => Some(SOURCESEL_A::USART0),
87            17 => Some(SOURCESEL_A::USART1),
88            28 => Some(SOURCESEL_A::TIMER0),
89            29 => Some(SOURCESEL_A::TIMER1),
90            30 => Some(SOURCESEL_A::TIMER2),
91            40 => Some(SOURCESEL_A::RTC),
92            48 => Some(SOURCESEL_A::GPIOL),
93            49 => Some(SOURCESEL_A::GPIOH),
94            54 => Some(SOURCESEL_A::PCNT0),
95            _ => None,
96        }
97    }
98    #[doc = "Checks if the value of the field is `NONE`"]
99    #[inline(always)]
100    pub fn is_none(&self) -> bool {
101        *self == SOURCESEL_A::NONE
102    }
103    #[doc = "Checks if the value of the field is `VCMP`"]
104    #[inline(always)]
105    pub fn is_vcmp(&self) -> bool {
106        *self == SOURCESEL_A::VCMP
107    }
108    #[doc = "Checks if the value of the field is `ACMP0`"]
109    #[inline(always)]
110    pub fn is_acmp0(&self) -> bool {
111        *self == SOURCESEL_A::ACMP0
112    }
113    #[doc = "Checks if the value of the field is `USART0`"]
114    #[inline(always)]
115    pub fn is_usart0(&self) -> bool {
116        *self == SOURCESEL_A::USART0
117    }
118    #[doc = "Checks if the value of the field is `USART1`"]
119    #[inline(always)]
120    pub fn is_usart1(&self) -> bool {
121        *self == SOURCESEL_A::USART1
122    }
123    #[doc = "Checks if the value of the field is `TIMER0`"]
124    #[inline(always)]
125    pub fn is_timer0(&self) -> bool {
126        *self == SOURCESEL_A::TIMER0
127    }
128    #[doc = "Checks if the value of the field is `TIMER1`"]
129    #[inline(always)]
130    pub fn is_timer1(&self) -> bool {
131        *self == SOURCESEL_A::TIMER1
132    }
133    #[doc = "Checks if the value of the field is `TIMER2`"]
134    #[inline(always)]
135    pub fn is_timer2(&self) -> bool {
136        *self == SOURCESEL_A::TIMER2
137    }
138    #[doc = "Checks if the value of the field is `RTC`"]
139    #[inline(always)]
140    pub fn is_rtc(&self) -> bool {
141        *self == SOURCESEL_A::RTC
142    }
143    #[doc = "Checks if the value of the field is `GPIOL`"]
144    #[inline(always)]
145    pub fn is_gpiol(&self) -> bool {
146        *self == SOURCESEL_A::GPIOL
147    }
148    #[doc = "Checks if the value of the field is `GPIOH`"]
149    #[inline(always)]
150    pub fn is_gpioh(&self) -> bool {
151        *self == SOURCESEL_A::GPIOH
152    }
153    #[doc = "Checks if the value of the field is `PCNT0`"]
154    #[inline(always)]
155    pub fn is_pcnt0(&self) -> bool {
156        *self == SOURCESEL_A::PCNT0
157    }
158}
159#[doc = "Field `SOURCESEL` writer - Source Select"]
160pub type SOURCESEL_W<'a> = crate::FieldWriter<'a, u32, CH5_CTRL_SPEC, u8, SOURCESEL_A, 6, 16>;
161impl<'a> SOURCESEL_W<'a> {
162    #[doc = "No source selected"]
163    #[inline(always)]
164    pub fn none(self) -> &'a mut W {
165        self.variant(SOURCESEL_A::NONE)
166    }
167    #[doc = "Voltage Comparator"]
168    #[inline(always)]
169    pub fn vcmp(self) -> &'a mut W {
170        self.variant(SOURCESEL_A::VCMP)
171    }
172    #[doc = "Analog Comparator 0"]
173    #[inline(always)]
174    pub fn acmp0(self) -> &'a mut W {
175        self.variant(SOURCESEL_A::ACMP0)
176    }
177    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
178    #[inline(always)]
179    pub fn usart0(self) -> &'a mut W {
180        self.variant(SOURCESEL_A::USART0)
181    }
182    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
183    #[inline(always)]
184    pub fn usart1(self) -> &'a mut W {
185        self.variant(SOURCESEL_A::USART1)
186    }
187    #[doc = "Timer 0"]
188    #[inline(always)]
189    pub fn timer0(self) -> &'a mut W {
190        self.variant(SOURCESEL_A::TIMER0)
191    }
192    #[doc = "Timer 1"]
193    #[inline(always)]
194    pub fn timer1(self) -> &'a mut W {
195        self.variant(SOURCESEL_A::TIMER1)
196    }
197    #[doc = "Timer 2"]
198    #[inline(always)]
199    pub fn timer2(self) -> &'a mut W {
200        self.variant(SOURCESEL_A::TIMER2)
201    }
202    #[doc = "Real-Time Counter"]
203    #[inline(always)]
204    pub fn rtc(self) -> &'a mut W {
205        self.variant(SOURCESEL_A::RTC)
206    }
207    #[doc = "General purpose Input/Output"]
208    #[inline(always)]
209    pub fn gpiol(self) -> &'a mut W {
210        self.variant(SOURCESEL_A::GPIOL)
211    }
212    #[doc = "General purpose Input/Output"]
213    #[inline(always)]
214    pub fn gpioh(self) -> &'a mut W {
215        self.variant(SOURCESEL_A::GPIOH)
216    }
217    #[doc = "Pulse Counter 0"]
218    #[inline(always)]
219    pub fn pcnt0(self) -> &'a mut W {
220        self.variant(SOURCESEL_A::PCNT0)
221    }
222}
223#[doc = "Edge Detect Select\n\nValue on reset: 0"]
224#[derive(Clone, Copy, Debug, PartialEq)]
225#[repr(u8)]
226pub enum EDSEL_A {
227    #[doc = "0: Signal is left as it is"]
228    OFF = 0,
229    #[doc = "1: A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal"]
230    POSEDGE = 1,
231    #[doc = "2: A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
232    NEGEDGE = 2,
233    #[doc = "3: A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal"]
234    BOTHEDGES = 3,
235}
236impl From<EDSEL_A> for u8 {
237    #[inline(always)]
238    fn from(variant: EDSEL_A) -> Self {
239        variant as _
240    }
241}
242#[doc = "Field `EDSEL` reader - Edge Detect Select"]
243pub type EDSEL_R = crate::FieldReader<u8, EDSEL_A>;
244impl EDSEL_R {
245    #[doc = "Get enumerated values variant"]
246    #[inline(always)]
247    pub fn variant(&self) -> EDSEL_A {
248        match self.bits {
249            0 => EDSEL_A::OFF,
250            1 => EDSEL_A::POSEDGE,
251            2 => EDSEL_A::NEGEDGE,
252            3 => EDSEL_A::BOTHEDGES,
253            _ => unreachable!(),
254        }
255    }
256    #[doc = "Checks if the value of the field is `OFF`"]
257    #[inline(always)]
258    pub fn is_off(&self) -> bool {
259        *self == EDSEL_A::OFF
260    }
261    #[doc = "Checks if the value of the field is `POSEDGE`"]
262    #[inline(always)]
263    pub fn is_posedge(&self) -> bool {
264        *self == EDSEL_A::POSEDGE
265    }
266    #[doc = "Checks if the value of the field is `NEGEDGE`"]
267    #[inline(always)]
268    pub fn is_negedge(&self) -> bool {
269        *self == EDSEL_A::NEGEDGE
270    }
271    #[doc = "Checks if the value of the field is `BOTHEDGES`"]
272    #[inline(always)]
273    pub fn is_bothedges(&self) -> bool {
274        *self == EDSEL_A::BOTHEDGES
275    }
276}
277#[doc = "Field `EDSEL` writer - Edge Detect Select"]
278pub type EDSEL_W<'a> = crate::FieldWriterSafe<'a, u32, CH5_CTRL_SPEC, u8, EDSEL_A, 2, 24>;
279impl<'a> EDSEL_W<'a> {
280    #[doc = "Signal is left as it is"]
281    #[inline(always)]
282    pub fn off(self) -> &'a mut W {
283        self.variant(EDSEL_A::OFF)
284    }
285    #[doc = "A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal"]
286    #[inline(always)]
287    pub fn posedge(self) -> &'a mut W {
288        self.variant(EDSEL_A::POSEDGE)
289    }
290    #[doc = "A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
291    #[inline(always)]
292    pub fn negedge(self) -> &'a mut W {
293        self.variant(EDSEL_A::NEGEDGE)
294    }
295    #[doc = "A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal"]
296    #[inline(always)]
297    pub fn bothedges(self) -> &'a mut W {
298        self.variant(EDSEL_A::BOTHEDGES)
299    }
300}
301#[doc = "Field `ASYNC` reader - Asynchronous reflex"]
302pub type ASYNC_R = crate::BitReader<bool>;
303#[doc = "Field `ASYNC` writer - Asynchronous reflex"]
304pub type ASYNC_W<'a> = crate::BitWriter<'a, u32, CH5_CTRL_SPEC, bool, 28>;
305impl R {
306    #[doc = "Bits 0:2 - Signal Select"]
307    #[inline(always)]
308    pub fn sigsel(&self) -> SIGSEL_R {
309        SIGSEL_R::new((self.bits & 7) as u8)
310    }
311    #[doc = "Bits 16:21 - Source Select"]
312    #[inline(always)]
313    pub fn sourcesel(&self) -> SOURCESEL_R {
314        SOURCESEL_R::new(((self.bits >> 16) & 0x3f) as u8)
315    }
316    #[doc = "Bits 24:25 - Edge Detect Select"]
317    #[inline(always)]
318    pub fn edsel(&self) -> EDSEL_R {
319        EDSEL_R::new(((self.bits >> 24) & 3) as u8)
320    }
321    #[doc = "Bit 28 - Asynchronous reflex"]
322    #[inline(always)]
323    pub fn async_(&self) -> ASYNC_R {
324        ASYNC_R::new(((self.bits >> 28) & 1) != 0)
325    }
326}
327impl W {
328    #[doc = "Bits 0:2 - Signal Select"]
329    #[inline(always)]
330    pub fn sigsel(&mut self) -> SIGSEL_W {
331        SIGSEL_W::new(self)
332    }
333    #[doc = "Bits 16:21 - Source Select"]
334    #[inline(always)]
335    pub fn sourcesel(&mut self) -> SOURCESEL_W {
336        SOURCESEL_W::new(self)
337    }
338    #[doc = "Bits 24:25 - Edge Detect Select"]
339    #[inline(always)]
340    pub fn edsel(&mut self) -> EDSEL_W {
341        EDSEL_W::new(self)
342    }
343    #[doc = "Bit 28 - Asynchronous reflex"]
344    #[inline(always)]
345    pub fn async_(&mut self) -> ASYNC_W {
346        ASYNC_W::new(self)
347    }
348    #[doc = "Writes raw bits to the register."]
349    #[inline(always)]
350    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
351        self.0.bits(bits);
352        self
353    }
354}
355#[doc = "Channel Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch5_ctrl](index.html) module"]
356pub struct CH5_CTRL_SPEC;
357impl crate::RegisterSpec for CH5_CTRL_SPEC {
358    type Ux = u32;
359}
360#[doc = "`read()` method returns [ch5_ctrl::R](R) reader structure"]
361impl crate::Readable for CH5_CTRL_SPEC {
362    type Reader = R;
363}
364#[doc = "`write(|w| ..)` method takes [ch5_ctrl::W](W) writer structure"]
365impl crate::Writable for CH5_CTRL_SPEC {
366    type Writer = W;
367}
368#[doc = "`reset()` method sets CH5_CTRL to value 0"]
369impl crate::Resettable for CH5_CTRL_SPEC {
370    #[inline(always)]
371    fn reset_value() -> Self::Ux {
372        0
373    }
374}
efm32hg108_pac/prs/ch5_ctrl.rs

efm32hg108_pac/prs/
ch5_ctrl.rs
