Struct efm32gg990::dma::RegisterBlock[−][src]

#[repr(C)]

pub struct RegisterBlock {
    pub status: STATUS,
    pub config: CONFIG,
    pub ctrlbase: CTRLBASE,
    pub altctrlbase: ALTCTRLBASE,
    pub chwaitstatus: CHWAITSTATUS,
    pub chswreq: CHSWREQ,
    pub chusebursts: CHUSEBURSTS,
    pub chuseburstc: CHUSEBURSTC,
    pub chreqmasks: CHREQMASKS,
    pub chreqmaskc: CHREQMASKC,
    pub chens: CHENS,
    pub chenc: CHENC,
    pub chalts: CHALTS,
    pub chaltc: CHALTC,
    pub chpris: CHPRIS,
    pub chpric: CHPRIC,
    pub errorc: ERRORC,
    pub chreqstatus: CHREQSTATUS,
    pub chsreqstatus: CHSREQSTATUS,
    pub if_: IF,
    pub ifs: IFS,
    pub ifc: IFC,
    pub ien: IEN,
    pub ctrl: CTRL,
    pub rds: RDS,
    pub loop0: LOOP0,
    pub loop1: LOOP1,
    pub rect0: RECT0,
    pub ch0_ctrl: CH0_CTRL,
    pub ch1_ctrl: CH1_CTRL,
    pub ch2_ctrl: CH2_CTRL,
    pub ch3_ctrl: CH3_CTRL,
    pub ch4_ctrl: CH4_CTRL,
    pub ch5_ctrl: CH5_CTRL,
    pub ch6_ctrl: CH6_CTRL,
    pub ch7_ctrl: CH7_CTRL,
    pub ch8_ctrl: CH8_CTRL,
    pub ch9_ctrl: CH9_CTRL,
    pub ch10_ctrl: CH10_CTRL,
    pub ch11_ctrl: CH11_CTRL,
    // some fields omitted
}

Register block

Fields

0x00 - DMA Status Registers

0x04 - DMA Configuration Register

0x08 - Channel Control Data Base Pointer Register

0x0c - Channel Alternate Control Data Base Pointer Register

0x10 - Channel Wait on Request Status Register

0x14 - Channel Software Request Register

0x18 - Channel Useburst Set Register

0x1c - Channel Useburst Clear Register

0x20 - Channel Request Mask Set Register

0x24 - Channel Request Mask Clear Register

0x28 - Channel Enable Set Register

0x2c - Channel Enable Clear Register

0x30 - Channel Alternate Set Register

0x34 - Channel Alternate Clear Register

0x38 - Channel Priority Set Register

0x3c - Channel Priority Clear Register

0x4c - Bus Error Clear Register

0xe10 - Channel Request Status

0xe18 - Channel Single Request Status

0x1000 - Interrupt Flag Register

0x1004 - Interrupt Flag Set Register

0x1008 - Interrupt Flag Clear Register

0x100c - Interrupt Enable register

0x1010 - DMA Control Register

0x1014 - DMA Retain Descriptor State

0x1020 - Channel 0 Loop Register

0x1024 - Channel 1 Loop Register

0x1060 - Channel 0 Rectangle Register

0x1100 - Channel Control Register

0x1104 - Channel Control Register

0x1108 - Channel Control Register

0x110c - Channel Control Register

0x1110 - Channel Control Register

0x1114 - Channel Control Register

0x1118 - Channel Control Register

0x111c - Channel Control Register

0x1120 - Channel Control Register

0x1124 - Channel Control Register

0x1128 - Channel Control Register

0x112c - Channel Control Register

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